dr_proc.h File Reference

Utility routines for identifying features of the processor. More...

Data Structures

struct  features_t
 
struct  features_t
 

Macros

#define DR_FPSTATE_BUF_SIZE   512
 
#define DR_FPSTATE_ALIGN   16
 
#define FAMILY_LLANO   18
 
#define FAMILY_ITANIUM_2_DC   17
 
#define FAMILY_K8_MOBILE   17
 
#define FAMILY_ITANIUM_2   16
 
#define FAMILY_K8L   16
 
#define FAMILY_K8   15
 
#define FAMILY_PENTIUM_4   15
 
#define FAMILY_P4   15
 
#define FAMILY_ITANIUM   7
 
#define FAMILY_P6   6
 
#define FAMILY_IVYBRIDGE   6
 
#define FAMILY_SANDYBRIDGE   6
 
#define FAMILY_NEHALEM   6
 
#define FAMILY_CORE_I7   6
 
#define FAMILY_CORE_2   6
 
#define FAMILY_CORE   6
 
#define FAMILY_PENTIUM_M   6
 
#define FAMILY_PENTIUM_3   6
 
#define FAMILY_PENTIUM_2   6
 
#define FAMILY_PENTIUM_PRO   6
 
#define FAMILY_ATHLON   6
 
#define FAMILY_K7   6
 
#define FAMILY_P5   5
 
#define FAMILY_PENTIUM   5
 
#define FAMILY_K6   5
 
#define FAMILY_K5   5
 
#define FAMILY_486   4
 
#define MODEL_HASWELL   60
 
#define MODEL_IVYBRIDGE   58
 
#define MODEL_I7_WESTMERE_EX   47
 
#define MODEL_SANDYBRIDGE_E   45
 
#define MODEL_I7_WESTMERE   44
 
#define MODEL_SANDYBRIDGE   42
 
#define MODEL_I7_CLARKDALE   37
 
#define MODEL_I7_HAVENDALE   31
 
#define MODEL_I7_CLARKSFIELD   30
 
#define MODEL_ATOM_CEDARVIEW   54
 
#define MODEL_ATOM_LINCROFT   38
 
#define MODEL_ATOM   28
 
#define MODEL_I7_GAINESTOWN   26
 
#define MODEL_CORE_PENRYN   23
 
#define MODEL_CORE_2   15
 
#define MODEL_CORE_MEROM   15
 
#define MODEL_CORE   14
 
#define MODEL_PENTIUM_M   13
 
#define MODEL_PENTIUM_M_1MB   9
 

Enumerations

enum  {
  VENDOR_INTEL,
  VENDOR_AMD,
  VENDOR_ARM,
  VENDOR_UNKNOWN
}
 
enum  feature_reg_idx_t {
  AA64ISAR0,
  AA64ISAR1,
  AA64PFR0,
  AA64MMFR1,
  AA64DFR0,
  AA64ZFR0,
  AA64PFR1,
  AA64ISAR2,
  AA64MMFR2,
  AA64_NUM_FEAT_REGS
}
 
enum  feature_bit_t {
  FEATURE_FPU = 0,
  FEATURE_VME = 1,
  FEATURE_DE = 2,
  FEATURE_PSE = 3,
  FEATURE_TSC = 4,
  FEATURE_MSR = 5,
  FEATURE_PAE = 6,
  FEATURE_MCE = 7,
  FEATURE_CX8 = 8,
  FEATURE_APIC = 9,
  FEATURE_SEP = 11,
  FEATURE_MTRR = 12,
  FEATURE_PGE = 13,
  FEATURE_MCA = 14,
  FEATURE_CMOV = 15,
  FEATURE_PAT = 16,
  FEATURE_PSE_36 = 17,
  FEATURE_PSN = 18,
  FEATURE_CLFSH = 19,
  FEATURE_DS = 21,
  FEATURE_ACPI = 22,
  FEATURE_MMX = 23,
  FEATURE_FXSR = 24,
  FEATURE_SSE = 25,
  FEATURE_SSE2 = 26,
  FEATURE_SS = 27,
  FEATURE_HTT = 28,
  FEATURE_TM = 29,
  FEATURE_IA64 = 30,
  FEATURE_PBE = 31,
  FEATURE_SSE3 = 0 + 32,
  FEATURE_PCLMULQDQ = 1 + 32,
  FEATURE_DTES64 = 2 + 32,
  FEATURE_MONITOR = 3 + 32,
  FEATURE_DS_CPL = 4 + 32,
  FEATURE_VMX = 5 + 32,
  FEATURE_SMX = 6 + 32,
  FEATURE_EST = 7 + 32,
  FEATURE_TM2 = 8 + 32,
  FEATURE_SSSE3 = 9 + 32,
  FEATURE_CID = 10 + 32,
  FEATURE_FMA = 12 + 32,
  FEATURE_CX16 = 13 + 32,
  FEATURE_xTPR = 14 + 32,
  FEATURE_PDCM = 15 + 32,
  FEATURE_PCID = 17 + 32,
  FEATURE_DCA = 18 + 32,
  FEATURE_SSE41 = 19 + 32,
  FEATURE_SSE42 = 20 + 32,
  FEATURE_x2APIC = 21 + 32,
  FEATURE_MOVBE = 22 + 32,
  FEATURE_POPCNT = 23 + 32,
  FEATURE_AES = 25 + 32,
  FEATURE_XSAVE = 26 + 32,
  FEATURE_OSXSAVE = 27 + 32,
  FEATURE_AVX = 28 + 32,
  FEATURE_F16C = 29 + 32,
  FEATURE_RDRAND = 30 + 32,
  FEATURE_SYSCALL = 11 + 64,
  FEATURE_XD_Bit = 20 + 64,
  FEATURE_MMX_EXT = 22 + 64,
  FEATURE_PDPE1GB = 26 + 64,
  FEATURE_RDTSCP = 27 + 64,
  FEATURE_EM64T = 29 + 64,
  FEATURE_3DNOW_EXT = 30 + 64,
  FEATURE_3DNOW = 31 + 64,
  FEATURE_LAHF = 0 + 96,
  FEATURE_SVM = 2 + 96,
  FEATURE_LZCNT = 5 + 96,
  FEATURE_SSE4A = 6 + 96,
  FEATURE_PRFCHW = 8 + 96,
  FEATURE_XOP = 11 + 96,
  FEATURE_SKINIT = 12 + 96,
  FEATURE_FMA4 = 16 + 96,
  FEATURE_TBM = 21 + 96,
  FEATURE_FSGSBASE = 0 + 128,
  FEATURE_BMI1 = 3 + 128,
  FEATURE_HLE = 4 + 128,
  FEATURE_AVX2 = 5 + 128,
  FEATURE_BMI2 = 8 + 128,
  FEATURE_ERMSB = 9 + 128,
  FEATURE_INVPCID = 10 + 128,
  FEATURE_RTM = 11 + 128,
  FEATURE_AVX512F = 16 + 128,
  FEATURE_AVX512BW = 30 + 128,
  FEATURE_AESX = DEF_FEAT(AA64ISAR0, 1, 1, FEAT_GR_EQ),
  FEATURE_PMULL = DEF_FEAT(AA64ISAR0, 1, 2, FEAT_EQ),
  FEATURE_SHA1 = DEF_FEAT(AA64ISAR0, 2, 1, FEAT_EQ),
  FEATURE_SHA256 = DEF_FEAT(AA64ISAR0, 3, 1, FEAT_GR_EQ),
  FEATURE_SHA512 = DEF_FEAT(AA64ISAR0, 3, 2, FEAT_EQ),
  FEATURE_CRC32 = DEF_FEAT(AA64ISAR0, 4, 1, FEAT_EQ),
  FEATURE_LSE = DEF_FEAT(AA64ISAR0, 5, 1, FEAT_GR_EQ),
  FEATURE_RDM = DEF_FEAT(AA64ISAR0, 7, 1, FEAT_EQ),
  FEATURE_SHA3,
  FEATURE_SM3 = DEF_FEAT(AA64ISAR0, 9, 1, FEAT_EQ),
  FEATURE_SM4 = DEF_FEAT(AA64ISAR0, 10, 1, FEAT_EQ),
  FEATURE_DotProd = DEF_FEAT(AA64ISAR0, 11, 1, FEAT_EQ),
  FEATURE_FHM = DEF_FEAT(AA64ISAR0, 12, 1, FEAT_EQ),
  FEATURE_FlagM,
  FEATURE_FlagM2 = DEF_FEAT(AA64ISAR0, 13, 2, FEAT_EQ),
  FEATURE_RNG = DEF_FEAT(AA64ISAR0, 15, 1, FEAT_EQ),
  FEATURE_DPB = DEF_FEAT(AA64ISAR1, 0, 1, FEAT_GR_EQ),
  FEATURE_DPB2 = DEF_FEAT(AA64ISAR1, 0, 2, FEAT_EQ),
  FEATURE_JSCVT = DEF_FEAT(AA64ISAR1, 3, 1, FEAT_EQ),
  FEATURE_FP16 = DEF_FEAT(AA64PFR0, 4, 1, FEAT_NS),
  FEATURE_RAS = DEF_FEAT(AA64PFR0, 7, 1, FEAT_GR_EQ),
  FEATURE_SVE = DEF_FEAT(AA64PFR0, 8, 1, FEAT_EQ),
  FEATURE_LOR,
  FEATURE_SPE,
  FEATURE_PAUTH,
  FEATURE_LRCPC,
  FEATURE_LRCPC2,
  FEATURE_FRINTTS,
  FEATURE_BF16 = DEF_FEAT(AA64ZFR0, 5, 1, FEAT_GR_EQ),
  FEATURE_I8MM,
  FEATURE_F64MM,
  FEATURE_SVE2,
  FEATURE_SVEAES = DEF_FEAT(AA64ZFR0, 1, 1, FEAT_GR_EQ),
  FEATURE_SVESHA3 = DEF_FEAT(AA64ZFR0, 8, 1, FEAT_EQ),
  FEATURE_SVESM4 = DEF_FEAT(AA64ZFR0, 10, 1, FEAT_EQ),
  FEATURE_SVEBitPerm,
  FEATURE_MTE,
  FEATURE_MTE2,
  FEATURE_BTI,
  FEATURE_PAUTH2,
  FEATURE_CONSTPACFIELD,
  FEATURE_SSBS,
  FEATURE_SSBS2,
  FEATURE_DIT,
  FEATURE_LSE2,
  FEATURE_WFxT,
  FEATURE_FPAC,
  FEATURE_FPACCOMBINE
}
 
enum  feature_bit_t {
  FEATURE_FPU = 0,
  FEATURE_VME = 1,
  FEATURE_DE = 2,
  FEATURE_PSE = 3,
  FEATURE_TSC = 4,
  FEATURE_MSR = 5,
  FEATURE_PAE = 6,
  FEATURE_MCE = 7,
  FEATURE_CX8 = 8,
  FEATURE_APIC = 9,
  FEATURE_SEP = 11,
  FEATURE_MTRR = 12,
  FEATURE_PGE = 13,
  FEATURE_MCA = 14,
  FEATURE_CMOV = 15,
  FEATURE_PAT = 16,
  FEATURE_PSE_36 = 17,
  FEATURE_PSN = 18,
  FEATURE_CLFSH = 19,
  FEATURE_DS = 21,
  FEATURE_ACPI = 22,
  FEATURE_MMX = 23,
  FEATURE_FXSR = 24,
  FEATURE_SSE = 25,
  FEATURE_SSE2 = 26,
  FEATURE_SS = 27,
  FEATURE_HTT = 28,
  FEATURE_TM = 29,
  FEATURE_IA64 = 30,
  FEATURE_PBE = 31,
  FEATURE_SSE3 = 0 + 32,
  FEATURE_PCLMULQDQ = 1 + 32,
  FEATURE_DTES64 = 2 + 32,
  FEATURE_MONITOR = 3 + 32,
  FEATURE_DS_CPL = 4 + 32,
  FEATURE_VMX = 5 + 32,
  FEATURE_SMX = 6 + 32,
  FEATURE_EST = 7 + 32,
  FEATURE_TM2 = 8 + 32,
  FEATURE_SSSE3 = 9 + 32,
  FEATURE_CID = 10 + 32,
  FEATURE_FMA = 12 + 32,
  FEATURE_CX16 = 13 + 32,
  FEATURE_xTPR = 14 + 32,
  FEATURE_PDCM = 15 + 32,
  FEATURE_PCID = 17 + 32,
  FEATURE_DCA = 18 + 32,
  FEATURE_SSE41 = 19 + 32,
  FEATURE_SSE42 = 20 + 32,
  FEATURE_x2APIC = 21 + 32,
  FEATURE_MOVBE = 22 + 32,
  FEATURE_POPCNT = 23 + 32,
  FEATURE_AES = 25 + 32,
  FEATURE_XSAVE = 26 + 32,
  FEATURE_OSXSAVE = 27 + 32,
  FEATURE_AVX = 28 + 32,
  FEATURE_F16C = 29 + 32,
  FEATURE_RDRAND = 30 + 32,
  FEATURE_SYSCALL = 11 + 64,
  FEATURE_XD_Bit = 20 + 64,
  FEATURE_MMX_EXT = 22 + 64,
  FEATURE_PDPE1GB = 26 + 64,
  FEATURE_RDTSCP = 27 + 64,
  FEATURE_EM64T = 29 + 64,
  FEATURE_3DNOW_EXT = 30 + 64,
  FEATURE_3DNOW = 31 + 64,
  FEATURE_LAHF = 0 + 96,
  FEATURE_SVM = 2 + 96,
  FEATURE_LZCNT = 5 + 96,
  FEATURE_SSE4A = 6 + 96,
  FEATURE_PRFCHW = 8 + 96,
  FEATURE_XOP = 11 + 96,
  FEATURE_SKINIT = 12 + 96,
  FEATURE_FMA4 = 16 + 96,
  FEATURE_TBM = 21 + 96,
  FEATURE_FSGSBASE = 0 + 128,
  FEATURE_BMI1 = 3 + 128,
  FEATURE_HLE = 4 + 128,
  FEATURE_AVX2 = 5 + 128,
  FEATURE_BMI2 = 8 + 128,
  FEATURE_ERMSB = 9 + 128,
  FEATURE_INVPCID = 10 + 128,
  FEATURE_RTM = 11 + 128,
  FEATURE_AVX512F = 16 + 128,
  FEATURE_AVX512BW = 30 + 128,
  FEATURE_AESX = DEF_FEAT(AA64ISAR0, 1, 1, FEAT_GR_EQ),
  FEATURE_PMULL = DEF_FEAT(AA64ISAR0, 1, 2, FEAT_EQ),
  FEATURE_SHA1 = DEF_FEAT(AA64ISAR0, 2, 1, FEAT_EQ),
  FEATURE_SHA256 = DEF_FEAT(AA64ISAR0, 3, 1, FEAT_GR_EQ),
  FEATURE_SHA512 = DEF_FEAT(AA64ISAR0, 3, 2, FEAT_EQ),
  FEATURE_CRC32 = DEF_FEAT(AA64ISAR0, 4, 1, FEAT_EQ),
  FEATURE_LSE = DEF_FEAT(AA64ISAR0, 5, 1, FEAT_GR_EQ),
  FEATURE_RDM = DEF_FEAT(AA64ISAR0, 7, 1, FEAT_EQ),
  FEATURE_SHA3,
  FEATURE_SM3 = DEF_FEAT(AA64ISAR0, 9, 1, FEAT_EQ),
  FEATURE_SM4 = DEF_FEAT(AA64ISAR0, 10, 1, FEAT_EQ),
  FEATURE_DotProd = DEF_FEAT(AA64ISAR0, 11, 1, FEAT_EQ),
  FEATURE_FHM = DEF_FEAT(AA64ISAR0, 12, 1, FEAT_EQ),
  FEATURE_FlagM,
  FEATURE_FlagM2 = DEF_FEAT(AA64ISAR0, 13, 2, FEAT_EQ),
  FEATURE_RNG = DEF_FEAT(AA64ISAR0, 15, 1, FEAT_EQ),
  FEATURE_DPB = DEF_FEAT(AA64ISAR1, 0, 1, FEAT_GR_EQ),
  FEATURE_DPB2 = DEF_FEAT(AA64ISAR1, 0, 2, FEAT_EQ),
  FEATURE_JSCVT = DEF_FEAT(AA64ISAR1, 3, 1, FEAT_EQ),
  FEATURE_FP16 = DEF_FEAT(AA64PFR0, 4, 1, FEAT_NS),
  FEATURE_RAS = DEF_FEAT(AA64PFR0, 7, 1, FEAT_GR_EQ),
  FEATURE_SVE = DEF_FEAT(AA64PFR0, 8, 1, FEAT_EQ),
  FEATURE_LOR,
  FEATURE_SPE,
  FEATURE_PAUTH,
  FEATURE_LRCPC,
  FEATURE_LRCPC2,
  FEATURE_FRINTTS,
  FEATURE_BF16 = DEF_FEAT(AA64ZFR0, 5, 1, FEAT_GR_EQ),
  FEATURE_I8MM,
  FEATURE_F64MM,
  FEATURE_SVE2,
  FEATURE_SVEAES = DEF_FEAT(AA64ZFR0, 1, 1, FEAT_GR_EQ),
  FEATURE_SVESHA3 = DEF_FEAT(AA64ZFR0, 8, 1, FEAT_EQ),
  FEATURE_SVESM4 = DEF_FEAT(AA64ZFR0, 10, 1, FEAT_EQ),
  FEATURE_SVEBitPerm,
  FEATURE_MTE,
  FEATURE_MTE2,
  FEATURE_BTI,
  FEATURE_PAUTH2,
  FEATURE_CONSTPACFIELD,
  FEATURE_SSBS,
  FEATURE_SSBS2,
  FEATURE_DIT,
  FEATURE_LSE2,
  FEATURE_WFxT,
  FEATURE_FPAC,
  FEATURE_FPACCOMBINE
}
 
enum  cache_size_t {
  CACHE_SIZE_8_KB,
  CACHE_SIZE_16_KB,
  CACHE_SIZE_32_KB,
  CACHE_SIZE_64_KB,
  CACHE_SIZE_128_KB,
  CACHE_SIZE_256_KB,
  CACHE_SIZE_512_KB,
  CACHE_SIZE_1_MB,
  CACHE_SIZE_2_MB,
  CACHE_SIZE_UNKNOWN
}
 

Functions

DR_API size_t proc_get_cache_line_size (void)
 
DR_API bool proc_is_cache_aligned (void *addr)
 
DR_API ptr_uint_t proc_bump_to_end_of_cache_line (ptr_uint_t sz)
 
DR_API void * proc_get_containing_page (void *addr)
 
DR_API uint proc_get_vendor (void)
 
DR_API int proc_set_vendor (uint new_vendor)
 
DR_API uint proc_get_family (void)
 
DR_API uint proc_get_type (void)
 
DR_API uint proc_get_model (void)
 
DR_API uint proc_get_stepping (void)
 
DR_API bool proc_has_feature (feature_bit_t feature)
 
DR_API features_tproc_get_all_feature_bits (void)
 
DR_API char * proc_get_brand_string (void)
 
DR_API cache_size_t proc_get_L1_icache_size (void)
 
DR_API cache_size_t proc_get_L1_dcache_size (void)
 
DR_API cache_size_t proc_get_L2_cache_size (void)
 
const DR_API char * proc_get_cache_size_str (cache_size_t size)
 
DR_API uint proc_get_vector_length_bytes (void)
 
DR_API size_t proc_fpstate_save_size (void)
 
DR_API int proc_num_simd_saved (void)
 
DR_API int proc_num_simd_registers (void)
 
DR_API int proc_num_opmask_registers (void)
 
DR_API size_t proc_save_fpstate (byte *buf)
 
DR_API void proc_restore_fpstate (byte *buf)
 
DR_API bool proc_avx_enabled (void)
 
DR_API bool proc_avx512_enabled (void)
 

Detailed Description

Utility routines for identifying features of the processor.

Macro Definition Documentation

◆ DR_FPSTATE_ALIGN

#define DR_FPSTATE_ALIGN   16

The alignment requirements of floating point state buffer.

◆ DR_FPSTATE_BUF_SIZE

#define DR_FPSTATE_BUF_SIZE   512

The maximum possible required size of floating point state buffer for processors with different features (i.e., the processors with the FXSR feature on x86, or the processors with the VFPv3 feature on ARM).

Note
The actual required buffer size may vary depending on the processor feature.
proc_fpstate_save_size() can be used to determine the particular size needed.

◆ FAMILY_486

#define FAMILY_486   4

proc_get_family() processor family: 486

◆ FAMILY_ATHLON

#define FAMILY_ATHLON   6

proc_get_family() processor family: Athlon

◆ FAMILY_CORE

#define FAMILY_CORE   6

proc_get_family() processor family: Core

◆ FAMILY_CORE_2

#define FAMILY_CORE_2   6

proc_get_family() processor family: Core 2

◆ FAMILY_CORE_I7

#define FAMILY_CORE_I7   6

proc_get_family() processor family: Core i7

◆ FAMILY_ITANIUM

#define FAMILY_ITANIUM   7

proc_get_family() processor family: Itanium

◆ FAMILY_ITANIUM_2

#define FAMILY_ITANIUM_2   16

proc_get_family() processor family: Itanium 2

◆ FAMILY_ITANIUM_2_DC

#define FAMILY_ITANIUM_2_DC   17

proc_get_family() processor family: Itanium 2 DC

◆ FAMILY_IVYBRIDGE

#define FAMILY_IVYBRIDGE   6

proc_get_family() processor family: IvyBridge

◆ FAMILY_K5

#define FAMILY_K5   5

proc_get_family() processor family: K5

◆ FAMILY_K6

#define FAMILY_K6   5

proc_get_family() processor family: K6

◆ FAMILY_K7

#define FAMILY_K7   6

proc_get_family() processor family: AMD K7

◆ FAMILY_K8

#define FAMILY_K8   15

proc_get_family() processor family: AMD K8

◆ FAMILY_K8_MOBILE

#define FAMILY_K8_MOBILE   17

proc_get_family() processor family: AMD K8 Mobile

◆ FAMILY_K8L

#define FAMILY_K8L   16

proc_get_family() processor family: AMD K8L

◆ FAMILY_LLANO

#define FAMILY_LLANO   18

proc_get_family() processor family: AMD Llano

◆ FAMILY_NEHALEM

#define FAMILY_NEHALEM   6

proc_get_family() processor family: Nehalem

◆ FAMILY_P4

#define FAMILY_P4   15

proc_get_family() processor family: P4 family

◆ FAMILY_P5

#define FAMILY_P5   5

proc_get_family() processor family: P5 family

◆ FAMILY_P6

#define FAMILY_P6   6

proc_get_family() processor family: P6 family

◆ FAMILY_PENTIUM

#define FAMILY_PENTIUM   5

proc_get_family() processor family: Pentium

◆ FAMILY_PENTIUM_2

#define FAMILY_PENTIUM_2   6

proc_get_family() processor family: Pentium 2

◆ FAMILY_PENTIUM_3

#define FAMILY_PENTIUM_3   6

proc_get_family() processor family: Pentium 3

◆ FAMILY_PENTIUM_4

#define FAMILY_PENTIUM_4   15

proc_get_family() processor family: Pentium 4

◆ FAMILY_PENTIUM_M

#define FAMILY_PENTIUM_M   6

proc_get_family() processor family: Pentium M

◆ FAMILY_PENTIUM_PRO

#define FAMILY_PENTIUM_PRO   6

proc_get_family() processor family: Pentium Pro

◆ FAMILY_SANDYBRIDGE

#define FAMILY_SANDYBRIDGE   6

proc_get_family() processor family: SandyBridge

◆ MODEL_ATOM

#define MODEL_ATOM   28

◆ MODEL_ATOM_CEDARVIEW

#define MODEL_ATOM_CEDARVIEW   54

proc_get_model(): Atom Cedarview

◆ MODEL_ATOM_LINCROFT

#define MODEL_ATOM_LINCROFT   38

proc_get_model(): Atom Lincroft

◆ MODEL_CORE

#define MODEL_CORE   14

proc_get_model(): Core Yonah

◆ MODEL_CORE_2

#define MODEL_CORE_2   15

proc_get_model(): Core 2 Merom/Conroe

◆ MODEL_CORE_MEROM

#define MODEL_CORE_MEROM   15

proc_get_model(): Core 2 Merom

◆ MODEL_CORE_PENRYN

#define MODEL_CORE_PENRYN   23

proc_get_model(): Core 2 Penryn

◆ MODEL_HASWELL

#define MODEL_HASWELL   60

proc_get_model(): Haswell

◆ MODEL_I7_CLARKDALE

#define MODEL_I7_CLARKDALE   37

proc_get_model(): Westmere Clarkdale/Arrandale

◆ MODEL_I7_CLARKSFIELD

#define MODEL_I7_CLARKSFIELD   30

proc_get_model(): Core i7 Clarksfield/Lynnfield

◆ MODEL_I7_GAINESTOWN

#define MODEL_I7_GAINESTOWN   26

proc_get_model(): Core i7 Gainestown (Nehalem)

◆ MODEL_I7_HAVENDALE

#define MODEL_I7_HAVENDALE   31

proc_get_model(): Core i7 Havendale/Auburndale

◆ MODEL_I7_WESTMERE

#define MODEL_I7_WESTMERE   44

proc_get_model(): Westmere

◆ MODEL_I7_WESTMERE_EX

#define MODEL_I7_WESTMERE_EX   47

proc_get_model(): Sandybridge Westmere Ex

◆ MODEL_IVYBRIDGE

#define MODEL_IVYBRIDGE   58

proc_get_model(): Ivybridge

◆ MODEL_PENTIUM_M

#define MODEL_PENTIUM_M   13

proc_get_model(): Pentium M 2MB L2

◆ MODEL_PENTIUM_M_1MB

#define MODEL_PENTIUM_M_1MB   9

proc_get_model(): Pentium M 1MB L2

◆ MODEL_SANDYBRIDGE

#define MODEL_SANDYBRIDGE   42

proc_get_model(): Sandybridge

◆ MODEL_SANDYBRIDGE_E

#define MODEL_SANDYBRIDGE_E   45

proc_get_model(): Sandybridge-E, -EN, -EP

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Constants returned by proc_get_vendor().

Enumerator
VENDOR_INTEL 

proc_get_vendor() processor identification: Intel

VENDOR_AMD 

proc_get_vendor() processor identification: AMD

VENDOR_ARM 

proc_get_vendor() processor identification: ARM

VENDOR_UNKNOWN 

proc_get_vendor() processor identification: unknown

◆ cache_size_t

L1 and L2 cache sizes, used by proc_get_L1_icache_size(), proc_get_L1_dcache_size(), proc_get_L2_cache_size(), and proc_get_cache_size_str().

Enumerator
CACHE_SIZE_8_KB 

L1 or L2 cache size of 8 KB.

CACHE_SIZE_16_KB 

L1 or L2 cache size of 16 KB.

CACHE_SIZE_32_KB 

L1 or L2 cache size of 32 KB.

CACHE_SIZE_64_KB 

L1 or L2 cache size of 64 KB.

CACHE_SIZE_128_KB 

L1 or L2 cache size of 128 KB.

CACHE_SIZE_256_KB 

L1 or L2 cache size of 256 KB.

CACHE_SIZE_512_KB 

L1 or L2 cache size of 512 KB.

CACHE_SIZE_1_MB 

L1 or L2 cache size of 1 MB.

CACHE_SIZE_2_MB 

L1 or L2 cache size of 2 MB.

CACHE_SIZE_UNKNOWN 

Unknown L1 or L2 cache size.

◆ feature_bit_t [1/2]

Feature bits returned by cpuid for X86 and mrs for AArch64. Pass one of these values to proc_has_feature() to determine whether the underlying processor has the feature.

Enumerator
FEATURE_FPU 

Floating-point unit on chip (X86)

FEATURE_VME 

Virtual Mode Extension (X86)

FEATURE_DE 

Debugging Extension (X86)

FEATURE_PSE 

Page Size Extension (X86)

FEATURE_TSC 

Time-Stamp Counter (X86)

FEATURE_MSR 

Model Specific Registers (X86)

FEATURE_PAE 

Physical Address Extension (X86)

FEATURE_MCE 

Machine Check Exception (X86)

FEATURE_CX8 

OP_cmpxchg8b supported (X86)

FEATURE_APIC 

On-chip APIC Hardware supported (X86)

FEATURE_SEP 

Fast System Call (X86)

FEATURE_MTRR 

Memory Type Range Registers (X86)

FEATURE_PGE 

Page Global Enable (X86)

FEATURE_MCA 

Machine Check Architecture (X86)

FEATURE_CMOV 

Conditional Move Instruction (X86)

FEATURE_PAT 

Page Attribute Table (X86)

FEATURE_PSE_36 

36-bit Page Size Extension (X86)

FEATURE_PSN 

Processor serial # present & enabled (X86)

FEATURE_CLFSH 

OP_clflush supported (X86)

FEATURE_DS 

Debug Store (X86)

FEATURE_ACPI 

Thermal monitor & SCC supported (X86)

FEATURE_MMX 

MMX technology supported (X86)

FEATURE_FXSR 

Fast FP save and restore (X86)

FEATURE_SSE 

SSE Extensions supported (X86)

FEATURE_SSE2 

SSE2 Extensions supported (X86)

FEATURE_SS 

Self-snoop (X86)

FEATURE_HTT 

Hyper-threading Technology (X86)

FEATURE_TM 

Thermal Monitor supported (X86)

FEATURE_IA64 

IA64 Capabilities (X86)

FEATURE_PBE 

Pending Break Enable (X86)

FEATURE_SSE3 

SSE3 Extensions supported (X86)

FEATURE_PCLMULQDQ 

OP_pclmulqdq supported (X86)

FEATURE_DTES64 

64-bit debug store supported (X86)

FEATURE_MONITOR 

OP_monitor/OP_mwait supported (X86)

FEATURE_DS_CPL 

CPL Qualified Debug Store (X86)

FEATURE_VMX 

Virtual Machine Extensions (X86)

FEATURE_SMX 

Safer Mode Extensions (X86)

FEATURE_EST 

Enhanced Speedstep Technology (X86)

FEATURE_TM2 

Thermal Monitor 2 (X86)

FEATURE_SSSE3 

SSSE3 Extensions supported (X86)

FEATURE_CID 

Context ID (X86)

FEATURE_FMA 

FMA instructions supported (X86)

FEATURE_CX16 

OP_cmpxchg16b supported (X86)

FEATURE_xTPR 

Send Task Priority Messages (X86)

FEATURE_PDCM 

Perfmon and Debug Capability (X86)

FEATURE_PCID 

Process-context identifiers (X86)

FEATURE_DCA 

Prefetch from memory-mapped devices (X86)

FEATURE_SSE41 

SSE4.1 Extensions supported (X86)

FEATURE_SSE42 

SSE4.2 Extensions supported (X86)

FEATURE_x2APIC 

x2APIC supported (X86)

FEATURE_MOVBE 

OP_movbe supported (X86)

FEATURE_POPCNT 

OP_popcnt supported (X86)

FEATURE_AES 

AES instructions supported (X86)

FEATURE_XSAVE 

OP_xsave* supported (X86)

FEATURE_OSXSAVE 

OP_xgetbv supported in user mode (X86)

FEATURE_AVX 

AVX instructions supported (X86)

FEATURE_F16C 

16-bit floating-point conversion supported (X86)

FEATURE_RDRAND 

OP_rdrand supported (X86)

FEATURE_SYSCALL 

OP_syscall/OP_sysret supported (X86)

FEATURE_XD_Bit 

Execution Disable bit (X86)

FEATURE_MMX_EXT 

AMD MMX Extensions (X86)

FEATURE_PDPE1GB 

Gigabyte pages (X86)

FEATURE_RDTSCP 

OP_rdtscp supported (X86)

FEATURE_EM64T 

Extended Memory 64 Technology (X86)

FEATURE_3DNOW_EXT 

AMD 3DNow! Extensions (X86)

FEATURE_3DNOW 

AMD 3DNow! instructions supported (X86)

FEATURE_LAHF 

OP_lahf/OP_sahf available in 64-bit mode (X86)

FEATURE_SVM 

AMD Secure Virtual Machine (X86)

FEATURE_LZCNT 

OP_lzcnt supported (X86)

FEATURE_SSE4A 

AMD SSE4A Extensions supported (X86)

FEATURE_PRFCHW 

OP_prefetchw supported (X86)

FEATURE_XOP 

AMD XOP supported (X86)

FEATURE_SKINIT 

AMD OP_skinit/OP_stgi supported (X86)

FEATURE_FMA4 

AMD FMA4 supported (X86)

FEATURE_TBM 

AMD Trailing Bit Manipulation supported (X86)

FEATURE_FSGSBASE 

OP_rdfsbase, etc. supported (X86)

FEATURE_BMI1 

BMI1 instructions supported (X86)

FEATURE_HLE 

Hardware Lock Elision supported (X86)

FEATURE_AVX2 

AVX2 instructions supported (X86)

FEATURE_BMI2 

BMI2 instructions supported (X86)

FEATURE_ERMSB 

Enhanced rep movsb/stosb supported (X86)

FEATURE_INVPCID 

OP_invpcid supported (X86)

FEATURE_RTM 

Restricted Transactional Memory supported (X86)

FEATURE_AVX512F 

AVX-512F instructions supported (X86)

FEATURE_AVX512BW 

AVX-512BW instructions supported (X86)

FEATURE_AESX 

AES<x> (AArch64)

FEATURE_PMULL 

PMULL/PMULL2 (AArch64)

FEATURE_SHA1 

SHA1<x> (AArch64)

FEATURE_SHA256 

SHA256<x> (AArch64)

FEATURE_SHA512 

SHA512<x> (AArch64)

FEATURE_CRC32 

CRC32<x> (AArch64)

FEATURE_LSE 

Atomics (AArch64)

FEATURE_RDM 

SQRDMLAH,SQRDMLSH (AArch64)

FEATURE_SHA3 

EOR3,RAX1,XAR,BCAX (AArch64)

FEATURE_SM3 

SM3<x> (AArch64)

FEATURE_SM4 

SM4E, SM4EKEY (AArch64)

FEATURE_DotProd 

UDOT, SDOT (AArch64)

FEATURE_FHM 

FMLAL, FMLSL (AArch64)

FEATURE_FlagM 

CFINV,RMIF,SETF<x> (AArch64)

FEATURE_FlagM2 

AXFLAG, XAFLAG (AArch64)

FEATURE_RNG 

RNDR, RNDRRS (AArch64)

FEATURE_DPB 

DC CVAP (AArch64)

FEATURE_DPB2 

DC CVAP, DC CVADP (AArch64)

FEATURE_JSCVT 

FJCVTZS (AArch64)

FEATURE_FP16 

Half-precision FP (AArch64)

FEATURE_RAS 

RAS extension (AArch64)

FEATURE_SVE 

Scalable Vectors (AArch64)

FEATURE_LOR 

Limited order regions (AArch64)

FEATURE_SPE 

Profiling extension (AArch64)

FEATURE_PAUTH 

PAuth extension (AArch64)

FEATURE_LRCPC 

LDAPR, LDAPRB, LDAPRH (AArch64)

FEATURE_LRCPC2 

LDAPUR*, STLUR* (AArch64)

FEATURE_FRINTTS 

FRINT(32/64)(X/Z) (AArch64)

FEATURE_BF16 

SVE BFloat16 (AArch64)

FEATURE_I8MM 

SVE Int8 matrix multiplication (AArch64)

FEATURE_F64MM 

SVE FP64 matrix multiplication (AArch64)

FEATURE_SVE2 

Scalable vectors 2 (AArch64)

FEATURE_SVEAES 

SVE2 + AES (AArch64)

FEATURE_SVESHA3 

SVE2 + SHA3 (AArch64)

FEATURE_SVESM4 

SVE2 + SM4 (AArch64)

FEATURE_SVEBitPerm 

SVE2 + BitPerm (AArch64)

FEATURE_MTE 

Instruction-only Memory Tagging (AArch64)

FEATURE_MTE2 

Full Memory Tagging (AArch64)

FEATURE_BTI 

Branch Target Identification (AArch64)

FEATURE_PAUTH2 

PAuth2 extension (AArch64)

FEATURE_CONSTPACFIELD 

PAC algorithm enhancement (AArch64)

FEATURE_SSBS 

Speculative Store Bypass Safe (AArch64)

FEATURE_SSBS2 

MRS and MSR instructions for SSBS (AArch64)

FEATURE_DIT 

Data Independent Timing instructions (AArch64)

FEATURE_LSE2 

Atomicity requirements for loads and stores (AArch64)

FEATURE_WFxT 

Wait for event / interrupt with timeout (AArch64)

FEATURE_FPAC 

Faulting on AUTI* instructions (AArch64)

FEATURE_FPACCOMBINE 

Faulting on combined branch pointer authentication instructions (AArch64)

◆ feature_bit_t [2/2]

Feature bits returned by mrs for AArch64. Pass one of these values to proc_has_feature() to determine whether the underlying processor has the feature.

Enumerator
FEATURE_FPU 

Floating-point unit on chip (X86)

FEATURE_VME 

Virtual Mode Extension (X86)

FEATURE_DE 

Debugging Extension (X86)

FEATURE_PSE 

Page Size Extension (X86)

FEATURE_TSC 

Time-Stamp Counter (X86)

FEATURE_MSR 

Model Specific Registers (X86)

FEATURE_PAE 

Physical Address Extension (X86)

FEATURE_MCE 

Machine Check Exception (X86)

FEATURE_CX8 

OP_cmpxchg8b supported (X86)

FEATURE_APIC 

On-chip APIC Hardware supported (X86)

FEATURE_SEP 

Fast System Call (X86)

FEATURE_MTRR 

Memory Type Range Registers (X86)

FEATURE_PGE 

Page Global Enable (X86)

FEATURE_MCA 

Machine Check Architecture (X86)

FEATURE_CMOV 

Conditional Move Instruction (X86)

FEATURE_PAT 

Page Attribute Table (X86)

FEATURE_PSE_36 

36-bit Page Size Extension (X86)

FEATURE_PSN 

Processor serial # present & enabled (X86)

FEATURE_CLFSH 

OP_clflush supported (X86)

FEATURE_DS 

Debug Store (X86)

FEATURE_ACPI 

Thermal monitor & SCC supported (X86)

FEATURE_MMX 

MMX technology supported (X86)

FEATURE_FXSR 

Fast FP save and restore (X86)

FEATURE_SSE 

SSE Extensions supported (X86)

FEATURE_SSE2 

SSE2 Extensions supported (X86)

FEATURE_SS 

Self-snoop (X86)

FEATURE_HTT 

Hyper-threading Technology (X86)

FEATURE_TM 

Thermal Monitor supported (X86)

FEATURE_IA64 

IA64 Capabilities (X86)

FEATURE_PBE 

Pending Break Enable (X86)

FEATURE_SSE3 

SSE3 Extensions supported (X86)

FEATURE_PCLMULQDQ 

OP_pclmulqdq supported (X86)

FEATURE_DTES64 

64-bit debug store supported (X86)

FEATURE_MONITOR 

OP_monitor/OP_mwait supported (X86)

FEATURE_DS_CPL 

CPL Qualified Debug Store (X86)

FEATURE_VMX 

Virtual Machine Extensions (X86)

FEATURE_SMX 

Safer Mode Extensions (X86)

FEATURE_EST 

Enhanced Speedstep Technology (X86)

FEATURE_TM2 

Thermal Monitor 2 (X86)

FEATURE_SSSE3 

SSSE3 Extensions supported (X86)

FEATURE_CID 

Context ID (X86)

FEATURE_FMA 

FMA instructions supported (X86)

FEATURE_CX16 

OP_cmpxchg16b supported (X86)

FEATURE_xTPR 

Send Task Priority Messages (X86)

FEATURE_PDCM 

Perfmon and Debug Capability (X86)

FEATURE_PCID 

Process-context identifiers (X86)

FEATURE_DCA 

Prefetch from memory-mapped devices (X86)

FEATURE_SSE41 

SSE4.1 Extensions supported (X86)

FEATURE_SSE42 

SSE4.2 Extensions supported (X86)

FEATURE_x2APIC 

x2APIC supported (X86)

FEATURE_MOVBE 

OP_movbe supported (X86)

FEATURE_POPCNT 

OP_popcnt supported (X86)

FEATURE_AES 

AES instructions supported (X86)

FEATURE_XSAVE 

OP_xsave* supported (X86)

FEATURE_OSXSAVE 

OP_xgetbv supported in user mode (X86)

FEATURE_AVX 

AVX instructions supported (X86)

FEATURE_F16C 

16-bit floating-point conversion supported (X86)

FEATURE_RDRAND 

OP_rdrand supported (X86)

FEATURE_SYSCALL 

OP_syscall/OP_sysret supported (X86)

FEATURE_XD_Bit 

Execution Disable bit (X86)

FEATURE_MMX_EXT 

AMD MMX Extensions (X86)

FEATURE_PDPE1GB 

Gigabyte pages (X86)

FEATURE_RDTSCP 

OP_rdtscp supported (X86)

FEATURE_EM64T 

Extended Memory 64 Technology (X86)

FEATURE_3DNOW_EXT 

AMD 3DNow! Extensions (X86)

FEATURE_3DNOW 

AMD 3DNow! instructions supported (X86)

FEATURE_LAHF 

OP_lahf/OP_sahf available in 64-bit mode (X86)

FEATURE_SVM 

AMD Secure Virtual Machine (X86)

FEATURE_LZCNT 

OP_lzcnt supported (X86)

FEATURE_SSE4A 

AMD SSE4A Extensions supported (X86)

FEATURE_PRFCHW 

OP_prefetchw supported (X86)

FEATURE_XOP 

AMD XOP supported (X86)

FEATURE_SKINIT 

AMD OP_skinit/OP_stgi supported (X86)

FEATURE_FMA4 

AMD FMA4 supported (X86)

FEATURE_TBM 

AMD Trailing Bit Manipulation supported (X86)

FEATURE_FSGSBASE 

OP_rdfsbase, etc. supported (X86)

FEATURE_BMI1 

BMI1 instructions supported (X86)

FEATURE_HLE 

Hardware Lock Elision supported (X86)

FEATURE_AVX2 

AVX2 instructions supported (X86)

FEATURE_BMI2 

BMI2 instructions supported (X86)

FEATURE_ERMSB 

Enhanced rep movsb/stosb supported (X86)

FEATURE_INVPCID 

OP_invpcid supported (X86)

FEATURE_RTM 

Restricted Transactional Memory supported (X86)

FEATURE_AVX512F 

AVX-512F instructions supported (X86)

FEATURE_AVX512BW 

AVX-512BW instructions supported (X86)

FEATURE_AESX 

AES<x> (AArch64)

FEATURE_PMULL 

PMULL/PMULL2 (AArch64)

FEATURE_SHA1 

SHA1<x> (AArch64)

FEATURE_SHA256 

SHA256<x> (AArch64)

FEATURE_SHA512 

SHA512<x> (AArch64)

FEATURE_CRC32 

CRC32<x> (AArch64)

FEATURE_LSE 

Atomics (AArch64)

FEATURE_RDM 

SQRDMLAH,SQRDMLSH (AArch64)

FEATURE_SHA3 

EOR3,RAX1,XAR,BCAX (AArch64)

FEATURE_SM3 

SM3<x> (AArch64)

FEATURE_SM4 

SM4E, SM4EKEY (AArch64)

FEATURE_DotProd 

UDOT, SDOT (AArch64)

FEATURE_FHM 

FMLAL, FMLSL (AArch64)

FEATURE_FlagM 

CFINV,RMIF,SETF<x> (AArch64)

FEATURE_FlagM2 

AXFLAG, XAFLAG (AArch64)

FEATURE_RNG 

RNDR, RNDRRS (AArch64)

FEATURE_DPB 

DC CVAP (AArch64)

FEATURE_DPB2 

DC CVAP, DC CVADP (AArch64)

FEATURE_JSCVT 

FJCVTZS (AArch64)

FEATURE_FP16 

Half-precision FP (AArch64)

FEATURE_RAS 

RAS extension (AArch64)

FEATURE_SVE 

Scalable Vectors (AArch64)

FEATURE_LOR 

Limited order regions (AArch64)

FEATURE_SPE 

Profiling extension (AArch64)

FEATURE_PAUTH 

PAuth extension (AArch64)

FEATURE_LRCPC 

LDAPR, LDAPRB, LDAPRH (AArch64)

FEATURE_LRCPC2 

LDAPUR*, STLUR* (AArch64)

FEATURE_FRINTTS 

FRINT(32/64)(X/Z) (AArch64)

FEATURE_BF16 

SVE BFloat16 (AArch64)

FEATURE_I8MM 

SVE Int8 matrix multiplication (AArch64)

FEATURE_F64MM 

SVE FP64 matrix multiplication (AArch64)

FEATURE_SVE2 

Scalable vectors 2 (AArch64)

FEATURE_SVEAES 

SVE2 + AES (AArch64)

FEATURE_SVESHA3 

SVE2 + SHA3 (AArch64)

FEATURE_SVESM4 

SVE2 + SM4 (AArch64)

FEATURE_SVEBitPerm 

SVE2 + BitPerm (AArch64)

FEATURE_MTE 

Instruction-only Memory Tagging (AArch64)

FEATURE_MTE2 

Full Memory Tagging (AArch64)

FEATURE_BTI 

Branch Target Identification (AArch64)

FEATURE_PAUTH2 

PAuth2 extension (AArch64)

FEATURE_CONSTPACFIELD 

PAC algorithm enhancement (AArch64)

FEATURE_SSBS 

Speculative Store Bypass Safe (AArch64)

FEATURE_SSBS2 

MRS and MSR instructions for SSBS (AArch64)

FEATURE_DIT 

Data Independent Timing instructions (AArch64)

FEATURE_LSE2 

Atomicity requirements for loads and stores (AArch64)

FEATURE_WFxT 

Wait for event / interrupt with timeout (AArch64)

FEATURE_FPAC 

Faulting on AUTI* instructions (AArch64)

FEATURE_FPACCOMBINE 

Faulting on combined branch pointer authentication instructions (AArch64)

◆ feature_reg_idx_t

For AArch64 this enum represents the feature registers read by MRS instructions. Used by proc_has_feature().

Enumerator
AA64ISAR0 

AArch64 Instruction Set Attribute Register 0.

AA64ISAR1 

AArch64 Instruction Set Attribute Register 1.

AA64PFR0 

AArch64 Processor Feature Register 0.

AA64MMFR1 

AArch64 Memory Model Feature Register 1.

AA64DFR0 

AArch64 Debug Feature Register 0.

AA64ZFR0 

SVE Feature ID Register 0.

AA64PFR1 

AArch64 Processor Feature Register 1.

AA64ISAR2 

AArch64 Instruction Set Attribute Register 2.

AA64MMFR2 

AArch64 Memory Model Feature Register 2.

AA64_NUM_FEAT_REGS 

Number of feature registers.

Function Documentation

◆ proc_avx512_enabled()

DR_API bool proc_avx512_enabled ( void  )

Returns whether AVX-512 is enabled by both the processor and the OS. Even if the processor supports AVX-512, if the OS does not enable AVX-512, then AVX-512 instructions will fault.

◆ proc_avx_enabled()

DR_API bool proc_avx_enabled ( void  )

Returns whether AVX (or AVX2) is enabled by both the processor and the OS. Even if the processor supports AVX, if the OS does not enable AVX, then AVX instructions will fault.

◆ proc_bump_to_end_of_cache_line()

DR_API ptr_uint_t proc_bump_to_end_of_cache_line ( ptr_uint_t  sz)

Returns n >= sz such that n is a multiple of the cache line size.

◆ proc_fpstate_save_size()

DR_API size_t proc_fpstate_save_size ( void  )

Returns the size in bytes needed for a buffer for saving the x87 floating point state.

◆ proc_get_all_feature_bits()

DR_API features_t* proc_get_all_feature_bits ( void  )

Returns all 4 32-bit feature values on X86 and architectural feature registers' values on AArch64. Use proc_has_feature() to test for specific features.

◆ proc_get_brand_string()

DR_API char* proc_get_brand_string ( void  )

Returns the processor brand string as given by the cpuid instruction.

◆ proc_get_cache_line_size()

DR_API size_t proc_get_cache_line_size ( void  )

Returns the cache line size in bytes of the processor.

◆ proc_get_cache_size_str()

const DR_API char* proc_get_cache_size_str ( cache_size_t  size)

Converts a cache_size_t type to a string.

◆ proc_get_containing_page()

DR_API void* proc_get_containing_page ( void *  addr)

Returns n <= addr such that n is a multiple of the page size.

◆ proc_get_family()

DR_API uint proc_get_family ( void  )

Returns the processor family as given by the cpuid instruction, adjusted by the extended family as described in the Intel documentation. The FAMILY_ constants identify important family values.

◆ proc_get_L1_dcache_size()

DR_API cache_size_t proc_get_L1_dcache_size ( void  )

Returns the size of the L1 data cache.

◆ proc_get_L1_icache_size()

DR_API cache_size_t proc_get_L1_icache_size ( void  )

Returns the size of the L1 instruction cache.

◆ proc_get_L2_cache_size()

DR_API cache_size_t proc_get_L2_cache_size ( void  )

Returns the size of the L2 cache.

◆ proc_get_model()

DR_API uint proc_get_model ( void  )

Returns the processor model as given by the cpuid instruction, adjusted by the extended model as described in the Intel documentation. The MODEL_ constants identify important model values.

◆ proc_get_stepping()

DR_API uint proc_get_stepping ( void  )

Returns the processor stepping ID.

◆ proc_get_type()

DR_API uint proc_get_type ( void  )

Returns the processor type as given by the cpuid instruction.

◆ proc_get_vector_length_bytes()

DR_API uint proc_get_vector_length_bytes ( void  )

Returns the size in bytes of the SVE registers' vector length set by the AArch64 hardware implementor. Length can be from 128 to 2048 bits in multiples of 128 bits: 128 256 384 512 640 768 896 1024 1152 1280 1408 1536 1664 1792 1920 2048 Currently DynamoRIO supports implementations of up to 512 bits.

◆ proc_get_vendor()

DR_API uint proc_get_vendor ( void  )

Returns one of the VENDOR_ constants.

◆ proc_has_feature()

DR_API bool proc_has_feature ( feature_bit_t  feature)

Tests if processor has selected feature.

◆ proc_is_cache_aligned()

DR_API bool proc_is_cache_aligned ( void *  addr)

Returns true only if addr is cache-line-aligned.

◆ proc_num_opmask_registers()

DR_API int proc_num_opmask_registers ( void  )

Returns the number of AVX-512 mask registers. The number returned here depends on the processor and OS feature bits on a given machine.

◆ proc_num_simd_registers()

DR_API int proc_num_simd_registers ( void  )

Returns the number of SIMD registers. The number returned here depends on the processor and OS feature bits on a given machine. For x86 this only includes xmm/ymm/zmm.

◆ proc_num_simd_saved()

DR_API int proc_num_simd_saved ( void  )

Returns the number of SIMD registers preserved for a context switch. DynamoRIO may decide to optimize the number of registers saved, in which case this number may be less than proc_num_simd_registers(). For x86 this only includes xmm/ymm/zmm.

The number of saved SIMD registers may be variable. For example, we may decide to optimize the number of saved registers in a context switch to avoid frequency scaling (https://github.com/DynamoRIO/dynamorio/issues/3169).

◆ proc_restore_fpstate()

DR_API void proc_restore_fpstate ( byte *  buf)

Restores the x87 floating point state from the buffer buf. On x86, the buffer must be 16-byte-aligned, and it must be 512 (DR_FPSTATE_BUF_SIZE) bytes for processors with the FXSR feature, and 108 bytes for those without (where this routine does not support 16-bit operand sizing). On ARM/AArch64, nothing needs to be restored as the SIMD/FP registers are restored together with the general-purpose registers.

Note
proc_fpstate_save_size() can be used to determine the particular size needed.

When the FXSR feature is present, the fxsave format matches the bitwidth of the ISA mode of the current thread (see dr_get_isa_mode()).

◆ proc_save_fpstate()

DR_API size_t proc_save_fpstate ( byte *  buf)

Saves the x87 floating point state into the buffer buf.

On x86, the buffer must be 16-byte-aligned, and it must be 512 (DR_FPSTATE_BUF_SIZE) bytes for processors with the FXSR feature, and 108 bytes for those without (where this routine does not support 16-bit operand sizing). On ARM/AArch64, nothing needs to be saved as the SIMD/FP registers are saved together with the general-purpose registers.

Note
proc_fpstate_save_size() can be used to determine the particular size needed.

When the FXSR feature is present, the fxsave format matches the bitwidth of the ISA mode of the current thread (see dr_get_isa_mode()).

The last floating-point instruction address is left in an untranslated state (i.e., it may point into the code cache).

DR does NOT save the application's x87 floating-point or MMX state on context switches! Thus if a client performs any floating-point operations in its main routines called by DR and cannot prove that its compiler will not use x87 operations, the client must save and restore the x87 floating-point/MMX state. If the client needs to do so inside the code cache the client should implement that itself. Returns number of bytes written.

◆ proc_set_vendor()

DR_API int proc_set_vendor ( uint  new_vendor)

Sets the vendor to the given VENDOR_ constant. This function is supplied to support decoding or encoding with respect to other than the current processor being executed on. The change in vendor will be seen by the decoder and encoder, as well as the rest of the system.

Returns
the prior vendor, or -1 on an invalid argument.