dr_ir_macros_aarch64.h File Reference

AArch64-specific instruction creation convenience macros. More...

Macros

#define VECTOR_ELEM_WIDTH_BYTE   0
 
#define VECTOR_ELEM_WIDTH_HALF   1
 
#define VECTOR_ELEM_WIDTH_SINGLE   2
 
#define VECTOR_ELEM_WIDTH_DOUBLE   3
 
#define VECTOR_ELEM_WIDTH_QUAD   4
 
#define OPND_CREATE_BYTE()   OPND_CREATE_INT8(VECTOR_ELEM_WIDTH_BYTE)
 
#define OPND_CREATE_HALF()   OPND_CREATE_INT8(VECTOR_ELEM_WIDTH_HALF)
 
#define OPND_CREATE_SINGLE()   OPND_CREATE_INT8(VECTOR_ELEM_WIDTH_SINGLE)
 
#define OPND_CREATE_DOUBLE()   OPND_CREATE_INT8(VECTOR_ELEM_WIDTH_DOUBLE)
 
#define OPND_CREATE_ABSMEM(addr, size)   opnd_create_rel_addr(addr, size)
 
#define OPND_CREATE_INT(val)   OPND_CREATE_INTPTR(val)
 
#define OPND_CREATE_ZR(reg)   opnd_create_reg(opnd_get_size(reg) == OPSZ_4 ? DR_REG_WZR : DR_REG_XZR)
 
#define OPND_CREATE_LSL()   opnd_add_flags(OPND_CREATE_INT(DR_SHIFT_LSL), DR_OPND_IS_SHIFT)
 
#define INSTR_CREATE_and(dc, rd, rn, rm_or_imm)
 
#define INSTR_CREATE_ands(dc, rd, rn, rm_or_imm)
 
#define INSTR_CREATE_bcond(dc, pc)   instr_create_0dst_1src((dc), OP_bcond, (pc))
 
#define INSTR_CREATE_bl(dc, pc)   instr_create_1dst_1src((dc), OP_bl, opnd_create_reg(DR_REG_X30), (pc))
 
#define INSTR_CREATE_ccmp(dc, Rn, Op, nzcv, cond)   (INSTR_PRED(instr_create_0dst_3src(dc, OP_ccmp, Rn, Op, nzcv), (cond)))
 
#define INSTR_CREATE_ccmn(dc, Rn, Op, nzcv, cond)   (INSTR_PRED(instr_create_0dst_3src(dc, OP_ccmn, Rn, Op, nzcv), (cond)))
 
#define INSTR_CREATE_fmov_general(dc, Rd, Rn)   instr_create_1dst_1src(dc, OP_fmov, Rd, Rn)
 
#define INSTR_CREATE_fmov_upper_vec(dc, Rd, Rn)
 
#define INSTR_CREATE_shadd_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_shadd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sqadd_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sqadd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_srhadd_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_srhadd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_shsub_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_shsub, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sqsub_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sqsub, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_cmgt_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_cmgt, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_cmge_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_cmge, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sshl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sshl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sqshl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sqshl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_srshl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_srshl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sqrshl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sqrshl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_smax_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_smax, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_smin_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_smin, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sabd_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sabd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_saba_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_saba, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_add_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_add, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_cmtst_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_cmtst, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_mla_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_4src(dc, OP_mla, Rd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_mul_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_mul, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_smaxp_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_smaxp, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sminp_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sminp, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sqdmulh_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sqdmulh, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_addp_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_addp, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_fmaxnm_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_fmaxnm, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_fmla_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_4src(dc, OP_fmla, Rd, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_fmla_vector_idx(dc, Rd, Rn, Rm, index, Rm_elsz)   instr_create_1dst_5src(dc, OP_fmla, Rd, Rd, Rn, Rm, index, Rm_elsz)
 
#define INSTR_CREATE_fadd_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_fadd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_fmulx_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_fmulx, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_fmulx_vector_idx(dc, Rd, Rn, Rm, index, Rm_elsz)   instr_create_1dst_4src(dc, OP_fmulx, Rd, Rn, Rm, index, Rm_elsz)
 
#define INSTR_CREATE_fmulx(dc, Rd, Rn, Rm)   instr_create_1dst_2src(dc, OP_fmulx, Rd, Rn, Rm)
 
#define INSTR_CREATE_fcmeq_vector_zero(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_3src(dc, OP_fcmeq, Rd, Rn, opnd_create_immed_float(0), Rn_elsz)
 
#define INSTR_CREATE_fcmeq_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_fcmeq, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_fcmeq_zero(dc, Rd, Rn)   instr_create_1dst_2src(dc, OP_fcmeq, Rd, Rn, opnd_create_immed_float(0))
 
#define INSTR_CREATE_fcmeq(dc, Rd, Rn, Rm)   instr_create_1dst_2src(dc, OP_fcmeq, Rd, Rn, Rm)
 
#define INSTR_CREATE_fmlal_vector(dc, Rd, Rn, Rm)   instr_create_1dst_4src(dc, OP_fmlal, Rd, Rd, Rn, Rm, OPND_CREATE_HALF())
 
#define INSTR_CREATE_fmlal_vector_idx(dc, Rd, Rn, Rm, index)   instr_create_1dst_5src(dc, OP_fmlal, Rd, Rd, Rn, Rm, index, OPND_CREATE_HALF())
 
#define INSTR_CREATE_fmax_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_fmax, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_frecpe_vector(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_2src(dc, OP_frecpe, Rd, Rn, Rn_elsz)
 
#define INSTR_CREATE_frecpe(dc, Rd, Rn)   instr_create_1dst_1src(dc, OP_frecpe, Rd, Rn)
 
#define INSTR_CREATE_frecps_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_frecps, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_frecps(dc, Rd, Rn, Rm)   instr_create_1dst_2src(dc, OP_frecps, Rd, Rn, Rm)
 
#define INSTR_CREATE_frsqrte_vector(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_2src(dc, OP_frsqrte, Rd, Rn, Rn_elsz)
 
#define INSTR_CREATE_frsqrte(dc, Rd, Rn)   instr_create_1dst_1src(dc, OP_frsqrte, Rd, Rn)
 
#define INSTR_CREATE_and_vector(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_and, Rd, Rm, Rn)
 
#define INSTR_CREATE_bic_vector(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_bic, Rd, Rm, Rn)
 
#define INSTR_CREATE_fminnm_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_fminnm, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_fmls_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_4src(dc, OP_fmls, Rd, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_fmls_vector_idx(dc, Rd, Rn, Rm, index, Rm_elsz)   instr_create_1dst_5src(dc, OP_fmls, Rd, Rd, Rn, Rm, index, Rm_elsz)
 
#define INSTR_CREATE_fsub_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_fsub, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_fmlsl_vector(dc, Rd, Rm, Rn)   instr_create_1dst_4src(dc, OP_fmlsl, Rd, Rd, Rm, Rn, OPND_CREATE_HALF())
 
#define INSTR_CREATE_fmlsl_vector_idx(dc, Rd, Rm, Rn, index)   instr_create_1dst_5src(dc, OP_fmlsl, Rd, Rd, Rm, Rn, index, OPND_CREATE_HALF())
 
#define INSTR_CREATE_fmin_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_fmin, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_frsqrts_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_frsqrts, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_frsqrts(dc, Rd, Rn, Rm)   instr_create_1dst_2src(dc, OP_frsqrts, Rd, Rn, Rm)
 
#define INSTR_CREATE_orr_vector(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_orr, Rd, Rm, Rn)
 
#define INSTR_CREATE_orn_vector(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_orn, Rd, Rm, Rn)
 
#define INSTR_CREATE_uhadd_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uhadd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uqadd_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uqadd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_urhadd_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_urhadd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uhsub_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uhsub, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uqsub_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uqsub, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_cmhi_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_cmhi, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_cmhs_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_cmhs, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_ushl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_ushl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uqshl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uqshl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_urshl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_urshl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uqrshl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uqrshl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_umax_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_umax, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_umin_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_umin, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uabd_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uabd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uaba_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uaba, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sub_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sub, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_cmeq_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_cmeq, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_mls_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_4src(dc, OP_mls, Rd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_pmul_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_pmul, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_umaxp_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_umaxp, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uminp_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uminp, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sqrdmulh_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sqrdmulh, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sqrdmlsh_scalar(dc, Rd, Rm, Rn)   instr_create_1dst_3src(dc, OP_sqrdmlsh, Rd, Rd, Rm, Rn)
 
#define INSTR_CREATE_sqrdmlsh_scalar_idx(dc, Rd, Rm, Rn, index, elsz)   instr_create_1dst_5src(dc, OP_sqrdmlsh, Rd, Rd, Rm, Rn, index, elsz)
 
#define INSTR_CREATE_sqrdmlsh_vector(dc, Rd, Rm, Rn, elsz)   instr_create_1dst_4src(dc, OP_sqrdmlsh, Rd, Rd, Rm, Rn, elsz)
 
#define INSTR_CREATE_sqrdmlsh_vector_idx(dc, Rd, Rm, Rn, index, elsz)   instr_create_1dst_5src(dc, OP_sqrdmlsh, Rd, Rd, Rm, Rn, index, elsz)
 
#define INSTR_CREATE_fmlal2_vector(dc, Rd, Rn, Rm)   instr_create_1dst_4src(dc, OP_fmlal2, Rd, Rd, Rn, Rm, OPND_CREATE_HALF())
 
#define INSTR_CREATE_fmlal2_vector_idx(dc, Rd, Rn, Rm, index)   instr_create_1dst_5src(dc, OP_fmlal2, Rd, Rd, Rn, Rm, index, OPND_CREATE_HALF())
 
#define INSTR_CREATE_faddp_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_faddp, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_faddp_scalar(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_2src(dc, OP_faddp, Rd, Rn, Rn_elsz)
 
#define INSTR_CREATE_fmul_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_fmul, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_fcmge_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_fcmge, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_fmaxnmp_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_fmaxnmp, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_fmaxnmp_scalar(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_2src(dc, OP_fmaxnmp, Rd, Rn, Rn_elsz)
 
#define INSTR_CREATE_fmaxp_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_fmaxp, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_fmaxp_scalar(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_2src(dc, OP_fmaxp, Rd, Rn, Rn_elsz)
 
#define INSTR_CREATE_facge_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_facge, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_facge(dc, Rd, Rn, Rm)   instr_create_1dst_2src(dc, OP_facge, Rd, Rn, Rm)
 
#define INSTR_CREATE_fcmle_vector_zero(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_3src(dc, OP_fcmle, Rd, Rn, opnd_create_immed_float(0.0), Rn_elsz)
 
#define INSTR_CREATE_fcmle_zero(dc, Rd, Rn)   instr_create_1dst_2src(dc, OP_fcmle, Rd, Rn, opnd_create_immed_float(0.0))
 
#define INSTR_CREATE_fcmlt_vector_zero(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_3src(dc, OP_fcmlt, Rd, Rn, opnd_create_immed_float(0.0), Rn_elsz)
 
#define INSTR_CREATE_fcmlt_zero(dc, Rd, Rn)   instr_create_1dst_2src(dc, OP_fcmlt, Rd, Rn, opnd_create_immed_float(0.0))
 
#define INSTR_CREATE_fdiv_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_fdiv, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_eor_vector(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_eor, Rd, Rm, Rn)
 
#define INSTR_CREATE_bsl_vector(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_bsl, Rd, Rm, Rn)
 
#define INSTR_CREATE_fminnmp_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_fminnmp, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_fminnmp_scalar(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_2src(dc, OP_fminnmp, Rd, Rn, Rn_elsz)
 
#define INSTR_CREATE_fminnmv_vector(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_2src(dc, OP_fminnmv, Rd, Rn, Rn_elsz)
 
#define INSTR_CREATE_fmlsl2_vector(dc, Rd, Rm, Rn)   instr_create_1dst_4src(dc, OP_fmlsl2, Rd, Rd, Rm, Rn, OPND_CREATE_HALF())
 
#define INSTR_CREATE_fmlsl2_vector_idx(dc, Rd, Rm, Rn, index)   instr_create_1dst_5src(dc, OP_fmlsl2, Rd, Rd, Rm, Rn, index, OPND_CREATE_HALF())
 
#define INSTR_CREATE_fabd_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_fabd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_facgt_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_facgt, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_facgt(dc, Rd, Rn, Rm)   instr_create_1dst_2src(dc, OP_facgt, Rd, Rn, Rm)
 
#define INSTR_CREATE_fcmgt_vector_zero(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_3src(dc, OP_fcmgt, Rd, Rn, opnd_create_immed_float(0.0), Rn_elsz)
 
#define INSTR_CREATE_fcmgt_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_fcmgt, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_fcmgt_zero(dc, Rd, Rn)   instr_create_1dst_2src(dc, OP_fcmgt, Rd, Rn, opnd_create_immed_float(0.0))
 
#define INSTR_CREATE_fcmgt(dc, Rd, Rn, Rm)   instr_create_1dst_2src(dc, OP_fcmgt, Rd, Rn, Rm)
 
#define INSTR_CREATE_fminp_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_fminp, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_fminp_scalar(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_2src(dc, OP_fminp, Rd, Rn, Rn_elsz)
 
#define INSTR_CREATE_bit_vector(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_bit, Rd, Rm, Rn)
 
#define INSTR_CREATE_bif_vector(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_bif, Rd, Rm, Rn)
 
#define INSTR_CREATE_fcvtas_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_fcvtas, Rd, Rm, width)
 
#define INSTR_CREATE_fcvtau_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_fcvtau, Rd, Rm, width)
 
#define INSTR_CREATE_fcvtms_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_fcvtms, Rd, Rm, width)
 
#define INSTR_CREATE_fcvtmu_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_fcvtmu, Rd, Rm, width)
 
#define INSTR_CREATE_fcvtns_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_fcvtns, Rd, Rm, width)
 
#define INSTR_CREATE_fcvtnu_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_fcvtnu, Rd, Rm, width)
 
#define INSTR_CREATE_fcvtps_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_fcvtps, Rd, Rm, width)
 
#define INSTR_CREATE_fcvtpu_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_fcvtpu, Rd, Rm, width)
 
#define INSTR_CREATE_fcvtzs_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_fcvtzs, Rd, Rm, width)
 
#define INSTR_CREATE_fcvtzu_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_fcvtzu, Rd, Rm, width)
 
#define INSTR_CREATE_fcvtzu_vector_fixed(dc, Rd, Rm, width, fbits)   instr_create_1dst_3src(dc, OP_fcvtzu, Rd, Rm, width, fbits)
 
#define INSTR_CREATE_sli_vector(dc, Rd, Rn, width, shift)   instr_create_1dst_3src(dc, OP_sli, Rd, Rn, width, shift)
 
#define INSTR_CREATE_uqshrn_vector(dc, Rd, Rn, width, shift)   instr_create_1dst_3src(dc, OP_uqshrn, Rd, Rn, width, shift)
 
#define INSTR_CREATE_ucvtf_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_ucvtf, Rd, Rm, width)
 
#define INSTR_CREATE_ucvtf_vector_fixed(dc, Rd, Rm, width, fbits)   instr_create_1dst_3src(dc, OP_ucvtf, Rd, Rm, width, fbits)
 
#define INSTR_CREATE_scvtf_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_scvtf, Rd, Rm, width)
 
#define INSTR_CREATE_scvtf_vector_fixed(dc, Rd, Rm, width, fbits)   instr_create_1dst_3src(dc, OP_scvtf, Rd, Rm, width, fbits)
 
#define INSTR_CREATE_sha512h(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_4src(dc, OP_sha512h, Rd, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_sha512h2(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_4src(dc, OP_sha512h2, Rd, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_sha512su0(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_3src(dc, OP_sha512su0, Rd, Rd, Rn, Rn_elsz)
 
#define INSTR_CREATE_sha512su1(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_4src(dc, OP_sha512su1, Rd, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_rax1(dc, Rd, Rn, Rm)   instr_create_1dst_3src(dc, OP_rax1, Rd, Rn, Rm, OPND_CREATE_DOUBLE())
 
#define INSTR_CREATE_xar(dc, Rd, Rn, Rm, imm6)   instr_create_1dst_4src(dc, OP_xar, Rd, Rn, Rm, imm6, OPND_CREATE_DOUBLE())
 
#define INSTR_CREATE_ldr_imm(dc, Rt, Xn, Rn, imm)   instr_create_2dst_3src(dc, OP_ldr, Rt, Xn, Rn, Xn, imm)
 
#define INSTR_CREATE_str_imm(dc, Rt, Xt, Xn, imm)   instr_create_2dst_3src(dc, OP_str, Rt, Xn, Xt, Xn, imm)
 
#define INSTR_CREATE_fmov_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fmov, Rd, Rm)
 
#define INSTR_CREATE_fabs_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fabs, Rd, Rm)
 
#define INSTR_CREATE_fneg_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fneg, Rd, Rm)
 
#define INSTR_CREATE_fsqrt_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fsqrt, Rd, Rm)
 
#define INSTR_CREATE_fsqrt_vector(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_2src(dc, OP_fsqrt, Rd, Rn, Rn_elsz)
 
#define INSTR_CREATE_fcvt_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fcvt, Rd, Rm)
 
#define INSTR_CREATE_fcvtas_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fcvtas, Rd, Rm)
 
#define INSTR_CREATE_fcvtau_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fcvtau, Rd, Rm)
 
#define INSTR_CREATE_fcvtms_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fcvtms, Rd, Rm)
 
#define INSTR_CREATE_fcvtmu_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fcvtmu, Rd, Rm)
 
#define INSTR_CREATE_fcvtns_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fcvtns, Rd, Rm)
 
#define INSTR_CREATE_fcvtnu_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fcvtnu, Rd, Rm)
 
#define INSTR_CREATE_fcvtps_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fcvtps, Rd, Rm)
 
#define INSTR_CREATE_fcvtpu_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fcvtpu, Rd, Rm)
 
#define INSTR_CREATE_fcvtzs_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fcvtzs, Rd, Rm)
 
#define INSTR_CREATE_fcvtzs_scalar_fixed(dc, Rd, Rm, fbits)   instr_create_1dst_2src(dc, OP_fcvtzs, Rd, Rm, fbits)
 
#define INSTR_CREATE_fcvtzu_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fcvtzu, Rd, Rm)
 
#define INSTR_CREATE_fcvtzu_scalar_fixed(dc, Rd, Rm, fbits)   instr_create_1dst_2src(dc, OP_fcvtzu, Rd, Rm, fbits)
 
#define INSTR_CREATE_ucvtf_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_ucvtf, Rd, Rm)
 
#define INSTR_CREATE_ucvtf_scalar_fixed(dc, Rd, Rm, fbits)   instr_create_1dst_2src(dc, OP_ucvtf, Rd, Rm, fbits)
 
#define INSTR_CREATE_scvtf_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_scvtf, Rd, Rm)
 
#define INSTR_CREATE_scvtf_scalar_fixed(dc, Rd, Rm, fbits)   instr_create_1dst_2src(dc, OP_scvtf, Rd, Rm, fbits)
 
#define INSTR_CREATE_frintn_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_frintn, Rd, Rm)
 
#define INSTR_CREATE_frintn_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_frintn, Rd, Rm, width)
 
#define INSTR_CREATE_frintp_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_frintp, Rd, Rm)
 
#define INSTR_CREATE_frintp_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_frintp, Rd, Rm, width)
 
#define INSTR_CREATE_frintm_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_frintm, Rd, Rm)
 
#define INSTR_CREATE_frintm_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_frintm, Rd, Rm, width)
 
#define INSTR_CREATE_frintz_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_frintz, Rd, Rm)
 
#define INSTR_CREATE_frintz_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_frintz, Rd, Rm, width)
 
#define INSTR_CREATE_frinta_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_frinta, Rd, Rm)
 
#define INSTR_CREATE_frinta_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_frinta, Rd, Rm, width)
 
#define INSTR_CREATE_frintx_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_frintx, Rd, Rm)
 
#define INSTR_CREATE_frintx_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_frintx, Rd, Rm, width)
 
#define INSTR_CREATE_frinti_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_frinti, Rd, Rm)
 
#define INSTR_CREATE_frinti_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_frinti, Rd, Rm, width)
 
#define INSTR_CREATE_ldpsw(dc, Xt1, Xt2, Xn, Xr, imm)   instr_create_3dst_3src(dc, OP_ldpsw, Xt1, Xt2, Xn, Xr, Xn, imm)
 
#define INSTR_CREATE_ldpsw_2(dc, Xt1, Xt2, Xn)   instr_create_2dst_1src(dc, OP_ldpsw, Xt1, Xt2, Xn)
 
#define INSTR_CREATE_fmul_scalar(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_fmul, Rd, Rm, Rn)
 
#define INSTR_CREATE_fdiv_scalar(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_fdiv, Rd, Rm, Rn)
 
#define INSTR_CREATE_fadd_scalar(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_fadd, Rd, Rm, Rn)
 
#define INSTR_CREATE_fsub_scalar(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_fsub, Rd, Rm, Rn)
 
#define INSTR_CREATE_fmax_scalar(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_fmax, Rd, Rm, Rn)
 
#define INSTR_CREATE_fmin_scalar(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_fmin, Rd, Rm, Rn)
 
#define INSTR_CREATE_fmaxnm_scalar(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_fmaxnm, Rd, Rm, Rn)
 
#define INSTR_CREATE_fminnm_scalar(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_fminnm, Rd, Rm, Rn)
 
#define INSTR_CREATE_fnmul_scalar(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_fnmul, Rd, Rm, Rn)
 
#define INSTR_CREATE_fmadd_scalar(dc, Rd, Rm, Rn, Ra)   instr_create_1dst_3src(dc, OP_fmadd, Rd, Rm, Rn, Ra)
 
#define INSTR_CREATE_fmsub_scalar(dc, Rd, Rm, Rn, Ra)   instr_create_1dst_3src(dc, OP_fmsub, Rd, Rm, Rn, Ra)
 
#define INSTR_CREATE_fnmadd_scalar(dc, Rd, Rm, Rn, Ra)   instr_create_1dst_3src(dc, OP_fnmadd, Rd, Rm, Rn, Ra)
 
#define INSTR_CREATE_fnmsub_scalar(dc, Rd, Rm, Rn, Ra)   instr_create_1dst_3src(dc, OP_fnmsub, Rd, Rm, Rn, Ra)
 
#define INSTR_CREATE_ld2_multi_2(dc, Vt1, Vt2, Xn, disp, offset, elsz)   instr_create_3dst_4src(dc, OP_ld2, Vt1, Vt2, Xn, disp, Xn, offset, elsz)
 
#define INSTR_CREATE_ld2(dc, Vt1, Vt2, Xn, index, elsz)   instr_create_2dst_3src(dc, OP_ld2, Vt1, Vt2, Xn, index, elsz)
 
#define INSTR_CREATE_ld2_2(dc, Vt1, Vt2, Xn, Xnd, index, offset, elsz)   instr_create_3dst_5src(dc, OP_ld2, Vt1, Vt2, Xn, Xnd, index, Xn, offset, elsz)
 
#define INSTR_CREATE_ld2r(dc, Vt1, Vt2, Xn, elsz)   instr_create_2dst_2src(dc, OP_ld2r, Vt1, Vt2, Xn, elsz)
 
#define INSTR_CREATE_ld2r_2(dc, Vt1, Vt2, Xn, Xnd, Xm, elsz)   instr_create_3dst_4src(dc, OP_ld2r, Vt1, Vt2, Xn, Xnd, Xn, Xm, elsz)
 
#define INSTR_CREATE_ld3_multi(dc, Vt1, Vt2, Vt3, Xn, elsz)   instr_create_3dst_2src(dc, OP_ld3, Vt1, Vt2, Vt3, Xn, elsz)
 
#define INSTR_CREATE_ld3_multi_2(dc, Vt1, Vt2, Vt3, Xn, Xnd, Xm, elsz)   instr_create_4dst_4src(dc, OP_ld3, Vt1, Vt2, Vt3, Xn, Xnd, Xn, Xm, elsz)
 
#define INSTR_CREATE_ld3(dc, Vt1, Vt2, Vt3, Xn, index, elsz)   instr_create_3dst_3src(dc, OP_ld3, Vt1, Vt2, Vt3, Xn, index, elsz)
 
#define INSTR_CREATE_ld3_2(dc, Vt1, Vt2, Vt3, Xn, Xnd, index, offset, elsz)   instr_create_4dst_5src(dc, OP_ld3, Vt1, Vt2, Vt3, Xn, Xnd, index, Xn, offset, elsz)
 
#define INSTR_CREATE_ld3r(dc, Vt1, Vt2, Vt3, Xn, elsz)   instr_create_3dst_2src(dc, OP_ld3r, Vt1, Vt2, Vt3, Xn, elsz)
 
#define INSTR_CREATE_ld3r_2(dc, Vt1, Vt2, Vt3, Xn, Xnd, offset, elsz)   instr_create_4dst_4src(dc, OP_ld3r, Vt1, Vt2, Vt3, Xn, Xnd, Xn, offset, elsz)
 
#define INSTR_CREATE_ld4_multi(dc, Vt1, Vt2, Vt3, Vt4, Xn, elsz)   instr_create_4dst_2src(dc, OP_ld4, Vt1, Vt2, Vt3, Vt4, Xn, elsz)
 
#define INSTR_CREATE_ld4_multi_2(dc, Vt1, Vt2, Vt3, Vt4, Xn, Xnd, offset, elsz)   instr_create_5dst_4src(dc, OP_ld4, Vt1, Vt2, Vt3, Vt4, Xn, Xnd, Xn, offset, elsz)
 
#define INSTR_CREATE_ld4(dc, Vt1, Vt2, Vt3, Vt4, Xn, index, elsz)   instr_create_4dst_3src(dc, OP_ld4, Vt1, Vt2, Vt3, Vt4, Xn, index, elsz)
 
#define INSTR_CREATE_ld4_2(dc, Vt1, Vt2, Vt3, Vt4, Xn, Xnd, index, offset, elsz)
 
#define INSTR_CREATE_ld4r(dc, Vt1, Vt2, Vt3, Vt4, Xn, elsz)   instr_create_4dst_2src(dc, OP_ld4r, Vt1, Vt2, Vt3, Vt4, Xn, elsz)
 
#define INSTR_CREATE_ld4r_2(dc, Vt1, Vt2, Vt3, Vt4, Xn, Xnd, offset, elsz)   instr_create_5dst_4src(dc, OP_ld4r, Vt1, Vt2, Vt3, Vt4, Xn, Xnd, Xn, offset, elsz)
 
#define INSTR_CREATE_ld1_multi_1(dc, q, r, s)   instr_create_1dst_2src(dc, OP_ld1, q, r, s)
 
#define INSTR_CREATE_st1_multi_1(dc, r, q, s)   instr_create_1dst_2src(dc, OP_st1, r, q, s)
 
#define INSTR_CREATE_orr_sve_pred(dc, Zd, Pg, Zd_, Zm, width)   instr_create_1dst_4src(dc, OP_orr, Zd, Pg, Zd_, Zm, width)
 
#define INSTR_CREATE_eor_sve_pred(dc, Zd, Pg, Zd_, Zm, width)   instr_create_1dst_4src(dc, OP_eor, Zd, Pg, Zd_, Zm, width)
 
#define INSTR_CREATE_and_sve_pred(dc, Zd, Pg, Zd_, Zm, width)   instr_create_1dst_4src(dc, OP_and, Zd, Pg, Zd_, Zm, width)
 
#define INSTR_CREATE_bic_sve_pred(dc, Zd, Pg, Zd_, Zm, width)   instr_create_1dst_4src(dc, OP_bic, Zd, Pg, Zd_, Zm, width)
 
#define INSTR_CREATE_saddl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_saddl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_saddl2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_saddl2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_saddw_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_saddw, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_saddw2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_saddw2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_ssubl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_ssubl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_ssubl2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_ssubl2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_ssubw_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_ssubw, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_ssubw2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_ssubw2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_addhn_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_addhn, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_addhn2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_addhn2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sabal_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sabal, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sabal2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sabal2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_subhn_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_subhn, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_subhn2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_subhn2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sabdl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sabdl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sabdl2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sabdl2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_smlal_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_smlal, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_smlal2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_smlal2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sqdmlal_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sqdmlal, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sqdmlal2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sqdmlal2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_smlsl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_smlsl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_smlsl2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_smlsl2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sqdmlsl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sqdmlsl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sqdmlsl2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sqdmlsl2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_smull_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_smull, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_smull2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_smull2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sqdmull_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sqdmull, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sqdmull2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sqdmull2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_pmull_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_pmull, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_pmull2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_pmull2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uaddl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uaddl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uaddl2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uaddl2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uaddw_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uaddw, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uaddw2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uaddw2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_usubl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_usubl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_usubl2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_usubl2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_usubw_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_usubw, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_usubw2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_usubw2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_raddhn_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_raddhn, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_raddhn2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_raddhn2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uabal_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uabal, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uabal2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uabal2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_rsubhn_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_rsubhn, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_rsubhn2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_rsubhn2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uabdl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uabdl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uabdl2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uabdl2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_umlal_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_4src(dc, OP_umlal, Rd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_umlal2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_4src(dc, OP_umlal2, Rd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_umlsl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_4src(dc, OP_umlsl, Rd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_umlsl2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_4src(dc, OP_umlsl2, Rd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_umull_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_umull, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_umull2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_umull2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_fmov_vector_imm(dc, Rd, f, width)   instr_create_1dst_2src(dc, OP_fmov, Rd, f, width)
 
#define INSTR_CREATE_fmov_scalar_imm(dc, Rd, f)   instr_create_1dst_1src(dc, OP_fmov, Rd, f)
 
#define INSTR_CREATE_ldlar(dc, Rt, Rn)   instr_create_1dst_1src(dc, OP_ldlar, Rt, Rn)
 
#define INSTR_CREATE_ldlarb(dc, Rt, Rn)   instr_create_1dst_1src(dc, OP_ldlarb, Rt, Rn)
 
#define INSTR_CREATE_ldlarh(dc, Rt, Rn)   instr_create_1dst_1src(dc, OP_ldlarh, Rt, Rn)
 
#define INSTR_CREATE_stllr(dc, Rt, Rn)   instr_create_1dst_1src(dc, OP_stllr, Rt, Rn)
 
#define INSTR_CREATE_stllrb(dc, Rt, Rn)   instr_create_1dst_1src(dc, OP_stllrb, Rt, Rn)
 
#define INSTR_CREATE_stllrh(dc, Rt, Rn)   instr_create_1dst_1src(dc, OP_stllrh, Rt, Rn)
 
#define INSTR_CREATE_sm3partw1_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_sm3partw1, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_sm3partw2_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_sm3partw2, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_sm3ss1_vector(dc, Rd, Rn, Rm, Ra, Ra_elsz)   instr_create_1dst_4src(dc, OP_sm3ss1, Rd, Rn, Rm, Ra, Ra_elsz)
 
#define INSTR_CREATE_sm3tt1a_vector_indexed(dc, Rd, Rn, Rm, imm2, Rm_elsz)   instr_create_1dst_4src(dc, OP_sm3tt1a, Rd, Rn, Rm, imm2, Rm_elsz)
 
#define INSTR_CREATE_sm3tt1b_vector_indexed(dc, Rd, Rn, Rm, imm2, Rm_elsz)   instr_create_1dst_4src(dc, OP_sm3tt1b, Rd, Rn, Rm, imm2, Rm_elsz)
 
#define INSTR_CREATE_sm3tt2a_vector_indexed(dc, Rd, Rn, Rm, imm2, Rm_elsz)   instr_create_1dst_4src(dc, OP_sm3tt2a, Rd, Rn, Rm, imm2, Rm_elsz)
 
#define INSTR_CREATE_sm3tt2b_vector_indexed(dc, Rd, Rn, Rm, imm2, Rm_elsz)   instr_create_1dst_4src(dc, OP_sm3tt2b, Rd, Rn, Rm, imm2, Rm_elsz)
 
#define INSTR_CREATE_sm4e_vector(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_2src(dc, OP_sm4e, Rd, Rn, Rn_elsz)
 
#define INSTR_CREATE_sm4ekey_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_sm4ekey, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_bcax(dc, Rd, Rn, Rm, Ra)   instr_create_1dst_4src(dc, OP_bcax, Rd, Rn, Rm, Ra, OPND_CREATE_BYTE())
 
#define INSTR_CREATE_eor3(dc, Rd, Rn, Rm, Ra)   instr_create_1dst_4src(dc, OP_eor3, Rd, Rn, Rm, Ra, OPND_CREATE_BYTE())
 
#define INSTR_CREATE_esb(dc)   instr_create_0dst_0src(dc, OP_esb)
 
#define INSTR_CREATE_psb_csync(dc)   instr_create_0dst_0src(dc, OP_psb)
 
#define INSTR_CREATE_fccmp(dc, Rn, Rm, nzcv, condition_code)   INSTR_PRED(instr_create_0dst_3src(dc, OP_fccmp, Rn, Rm, nzcv), (condition_code))
 
#define INSTR_CREATE_fccmpe(dc, Rn, Rm, nzcv, condition_code)   INSTR_PRED(instr_create_0dst_3src(dc, OP_fccmpe, Rn, Rm, nzcv), (condition_code))
 
#define INSTR_CREATE_fcsel(dc, Rd, Rn, Rm, condition_code)   INSTR_PRED(instr_create_1dst_2src(dc, OP_fcsel, Rd, Rn, Rm), (condition_code))
 
#define INSTR_CREATE_fcmp_zero(dc, Rn)   instr_create_0dst_2src(dc, OP_fcmp, Rn, opnd_create_immed_float(0.0))
 
#define INSTR_CREATE_fcmp(dc, Rn, Rm)   instr_create_0dst_2src(dc, OP_fcmp, Rn, Rm)
 
#define INSTR_CREATE_fcmpe_zero(dc, Rn)   instr_create_0dst_2src(dc, OP_fcmpe, Rn, opnd_create_immed_float(0.0))
 
#define INSTR_CREATE_fcmpe(dc, Rn, Rm)   instr_create_0dst_2src(dc, OP_fcmpe, Rn, Rm)
 
#define INSTR_CREATE_sdot_vector(dc, Rd, Rn, Rm)   instr_create_1dst_4src(dc, OP_sdot, Rd, Rd, Rn, Rm, OPND_CREATE_BYTE())
 
#define INSTR_CREATE_sdot_vector_indexed(dc, Rd, Rn, Rm, index)   instr_create_1dst_5src(dc, OP_sdot, Rd, Rd, Rn, Rm, index, OPND_CREATE_BYTE())
 
#define INSTR_CREATE_udot_vector(dc, Rd, Rn, Rm)   instr_create_1dst_4src(dc, OP_udot, Rd, Rd, Rn, Rm, OPND_CREATE_BYTE())
 
#define INSTR_CREATE_udot_vector_indexed(dc, Rd, Rn, Rm, index)   instr_create_1dst_5src(dc, OP_udot, Rd, Rd, Rn, Rm, index, OPND_CREATE_BYTE())
 
#define INSTR_CREATE_xpaci(dc, Rd)   instr_create_0dst_1src((dc), OP_xpaci, (Rd))
 
Platform-independent macros
#define XINST_CREATE_debug_instr(dc)   INSTR_CREATE_brk((dc), OPND_CREATE_INT16(0))
 
#define XINST_CREATE_load(dc, r, m)
 
#define XINST_CREATE_load_1byte_zext4(dc, r, m)   INSTR_CREATE_ldrb(dc, r, m)
 
#define XINST_CREATE_load_1byte(dc, r, m)   INSTR_CREATE_ldrb(dc, r, m)
 
#define XINST_CREATE_load_2bytes(dc, r, m)   INSTR_CREATE_ldrh(dc, r, m)
 
#define XINST_CREATE_store(dc, m, r)
 
#define XINST_CREATE_store_1byte(dc, m, r)   INSTR_CREATE_strb(dc, m, opnd_create_reg(reg_resize_to_opsz(opnd_get_reg(r), OPSZ_4)))
 
#define XINST_CREATE_store_2bytes(dc, m, r)   INSTR_CREATE_strh(dc, m, opnd_create_reg(reg_resize_to_opsz(opnd_get_reg(r), OPSZ_4)))
 
#define XINST_CREATE_store_pair(dc, m, r1, r2)   INSTR_CREATE_stp(dc, m, r1, r2)
 
#define XINST_CREATE_load_pair(dc, r1, r2, m)   INSTR_CREATE_ldp(dc, r1, r2, m)
 
#define XINST_CREATE_move(dc, d, s)
 
#define XINST_CREATE_load_simd(dc, r, m)   INSTR_CREATE_ldr((dc), (r), (m))
 
#define XINST_CREATE_store_simd(dc, m, r)   INSTR_CREATE_str((dc), (m), (r))
 
#define XINST_CREATE_jump_reg(dc, r)   INSTR_CREATE_br((dc), (r))
 
#define XINST_CREATE_load_int(dc, r, i)
 
#define XINST_CREATE_return(dc)   INSTR_CREATE_ret(dc, opnd_create_reg(DR_REG_X30))
 
#define XINST_CREATE_jump(dc, t)   INSTR_CREATE_b((dc), (t))
 
#define XINST_CREATE_jump_short(dc, t)   INSTR_CREATE_b((dc), (t))
 
#define XINST_CREATE_call(dc, t)   INSTR_CREATE_bl(dc, t)
 
#define XINST_CREATE_jump_cond(dc, pred, t)   (INSTR_PRED(INSTR_CREATE_bcond((dc), (t)), (pred)))
 
#define XINST_CREATE_add(dc, d, s)   INSTR_CREATE_add(dc, d, d, s)
 
#define XINST_CREATE_add_2src(dc, d, s1, s2)   INSTR_CREATE_add(dc, d, s1, s2)
 
#define XINST_CREATE_add_sll(dc, d, s1, s2_toshift, shift_amount)
 
#define XINST_CREATE_add_s(dc, d, s)   INSTR_CREATE_adds(dc, d, d, s)
 
#define XINST_CREATE_sub(dc, d, s)   INSTR_CREATE_sub(dc, d, d, s)
 
#define XINST_CREATE_sub_s(dc, d, s)   INSTR_CREATE_subs(dc, d, d, s)
 
#define XINST_CREATE_and_s(dc, d, s)   INSTR_CREATE_ands(dc, d, d, s)
 
#define XINST_CREATE_cmp(dc, s1, s2)   INSTR_CREATE_cmp(dc, s1, s2)
 
#define XINST_CREATE_interrupt(dc, i)   INSTR_CREATE_svc(dc, (i))
 
#define XINST_CREATE_slr_s(dc, d, rm_or_imm)
 
#define XINST_CREATE_nop(dc)   INSTR_CREATE_nop(dc)
 
#define XINST_CREATE_call_reg(dc, r)   INSTR_CREATE_blr(dc, r)
 

Detailed Description

AArch64-specific instruction creation convenience macros.

Macro Definition Documentation

◆ INSTR_CREATE_add_vector

#define INSTR_CREATE_add_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_add, Rd, Rm, Rn, width)

Creates a ADD vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_addhn2_vector

#define INSTR_CREATE_addhn2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_addhn2, Rd, Rm, Rn, width)

Creates a ADDHN2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_addhn_vector

#define INSTR_CREATE_addhn_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_addhn, Rd, Rm, Rn, width)

Creates a ADDHN vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_addp_vector

#define INSTR_CREATE_addp_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_addp, Rd, Rm, Rn, width)

Creates a ADDP vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_and

#define INSTR_CREATE_and (   dc,
  rd,
  rn,
  rm_or_imm 
)
Value:
(opnd_is_immed(rm_or_imm) \
? instr_create_1dst_2src((dc), OP_and, (rd), (rn), (rm_or_imm)) \
: INSTR_CREATE_and_shift(dc, rd, rn, rm_or_imm, OPND_CREATE_LSL(), \

disabled_until_i4106_is_fixed Creates an AND instruction with one output and two inputs.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
rdThe output register.
rnThe first input register.
rm_or_immThe second input register or immediate.

◆ INSTR_CREATE_and_sve_pred

#define INSTR_CREATE_and_sve_pred (   dc,
  Zd,
  Pg,
  Zd_,
  Zm,
  width 
)    instr_create_1dst_4src(dc, OP_and, Zd, Pg, Zd_, Zm, width)

Creates an AND scalable vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe output SVE vector register.
PgPredicate register for predicated instruction, P0-P7.
Zd_The first input SVE vector register. Must match Zd.
ZmThe second input SVE vector register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_and_vector

#define INSTR_CREATE_and_vector (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_and, Rd, Rm, Rn)

Creates a AND vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_ands

#define INSTR_CREATE_ands (   dc,
  rd,
  rn,
  rm_or_imm 
)
Value:
(opnd_is_immed(rm_or_imm) \
? instr_create_1dst_2src((dc), OP_ands, (rd), (rn), (rm_or_imm)) \
: INSTR_CREATE_ands_shift(dc, rd, rn, rm_or_imm, OPND_CREATE_LSL(), \

disabled_until_i4106_is_fixed Creates an ANDS instruction with one output and two inputs.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
rdThe output register.
rnThe first input register.
rm_or_immThe second input register or immediate.

◆ INSTR_CREATE_bcax

#define INSTR_CREATE_bcax (   dc,
  Rd,
  Rn,
  Rm,
  Ra 
)    instr_create_1dst_4src(dc, OP_bcax, Rd, Rn, Rm, Ra, OPND_CREATE_BYTE())

Creates a BCAX instruction.

This macro is used to encode the forms:

*    BCAX    <Bd>.16B, <Bn>.16B, <Bm>.16B, <Ba>.16B
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register, Q (quadword, 128 bits)
RnThe second source vector register, Q (quadword, 128 bits)
RmThe third source vector register, Q (quadword, 128 bits)
RaThe fourth source vector register, Q (quadword, 128 bits)

◆ INSTR_CREATE_bcond

#define INSTR_CREATE_bcond (   dc,
  pc 
)    instr_create_0dst_1src((dc), OP_bcond, (pc))

disabled_until_i4106_is_fixed This macro creates an instr_t for a conditional branch instruction. The condition can be set using INSTR_PRED macro.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
pcThe opnd_t target operand containing the program counter to jump to.

◆ INSTR_CREATE_bic_sve_pred

#define INSTR_CREATE_bic_sve_pred (   dc,
  Zd,
  Pg,
  Zd_,
  Zm,
  width 
)    instr_create_1dst_4src(dc, OP_bic, Zd, Pg, Zd_, Zm, width)

Creates a BIC scalable vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe output SVE vector register.
PgPredicate register for predicated instruction, P0-P7.
Zd_The first input SVE vector register. Must match Zd.
ZmThe second input SVE vector register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_bic_vector

#define INSTR_CREATE_bic_vector (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_bic, Rd, Rm, Rn)

Creates a BIC vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_bif_vector

#define INSTR_CREATE_bif_vector (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_bif, Rd, Rm, Rn)

Creates a BIF vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_bit_vector

#define INSTR_CREATE_bit_vector (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_bit, Rd, Rm, Rn)

Creates a BIT vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_bl

#define INSTR_CREATE_bl (   dc,
  pc 
)    instr_create_1dst_1src((dc), OP_bl, opnd_create_reg(DR_REG_X30), (pc))

This macro creates an instr_t for a BL (branch and link) instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
pcThe opnd_t target operand containing the program counter to jump to.

◆ INSTR_CREATE_bsl_vector

#define INSTR_CREATE_bsl_vector (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_bsl, Rd, Rm, Rn)

Creates a BSL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_ccmn

#define INSTR_CREATE_ccmn (   dc,
  Rn,
  Op,
  nzcv,
  cond 
)    (INSTR_PRED(instr_create_0dst_3src(dc, OP_ccmn, Rn, Op, nzcv), (cond)))

Creates a CCMN (Conditional Compare Negative) instruction. Sets the NZCV flags to the result of a comparison of its two source values if the named input condition is true, or to an immediate value if the input condition is false. The comparison is based on a negated second source value (Op) if an immediate, inverted if a register.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
condThe comparison condition specified by dr_pred_type_t, e.g. DR_PRED_EQ.
RnThe GPR source register.
OpEither a 5-bit immediate (use opnd_create_immed_uint() to create the operand, e.g. opnd_create_immed_uint(val, OPSZ_5b)) or a GPR source register.
nzcvThe 4 bit NZCV flags value used if the input condition is false. (use opnd_create_immed_uint() to create the operand, e.g. opnd_create_immed_uint(val, OPSZ_4b)).

◆ INSTR_CREATE_ccmp

#define INSTR_CREATE_ccmp (   dc,
  Rn,
  Op,
  nzcv,
  cond 
)    (INSTR_PRED(instr_create_0dst_3src(dc, OP_ccmp, Rn, Op, nzcv), (cond)))

Creates a CCMP (Conditional Compare) instruction. Sets the NZCV flags to the result of a comparison of its two source values if the named input condition is true, or to an immediate value if the input condition is false.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
condThe comparison condition specified by dr_pred_type_t, e.g. DR_PRED_EQ.
RnThe GPR source register.
OpEither a 5-bit immediate (use opnd_create_immed_uint() to create the operand, e.g. opnd_create_immed_uint(val, OPSZ_5b)) or a GPR source register.
nzcvThe 4 bit NZCV flags value used if the input condition is false. (use opnd_create_immed_uint() to create the operand, e.g. opnd_create_immed_uint(val, OPSZ_4b)).

◆ INSTR_CREATE_cmeq_vector

#define INSTR_CREATE_cmeq_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_cmeq, Rd, Rm, Rn, width)

Creates a CMEQ vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_cmge_vector

#define INSTR_CREATE_cmge_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_cmge, Rd, Rm, Rn, width)

Creates a CMGE vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_cmgt_vector

#define INSTR_CREATE_cmgt_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_cmgt, Rd, Rm, Rn, width)

Creates a CMGT vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_cmhi_vector

#define INSTR_CREATE_cmhi_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_cmhi, Rd, Rm, Rn, width)

Creates a CMHI vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_cmhs_vector

#define INSTR_CREATE_cmhs_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_cmhs, Rd, Rm, Rn, width)

Creates a CMHS vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_cmtst_vector

#define INSTR_CREATE_cmtst_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_cmtst, Rd, Rm, Rn, width)

Creates a CMTST vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_eor3

#define INSTR_CREATE_eor3 (   dc,
  Rd,
  Rn,
  Rm,
  Ra 
)    instr_create_1dst_4src(dc, OP_eor3, Rd, Rn, Rm, Ra, OPND_CREATE_BYTE())

Creates a EOR3 instruction.

This macro is used to encode the forms:

*    EOR3    <Bd>.16B, <Bn>.16B, <Bm>.16B, <Ba>.16B
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register, Q (quadword, 128 bits)
RnThe second source vector register, Q (quadword, 128 bits)
RmThe third source vector register, Q (quadword, 128 bits)
RaThe fourth source vector register, Q (quadword, 128 bits)

◆ INSTR_CREATE_eor_sve_pred

#define INSTR_CREATE_eor_sve_pred (   dc,
  Zd,
  Pg,
  Zd_,
  Zm,
  width 
)    instr_create_1dst_4src(dc, OP_eor, Zd, Pg, Zd_, Zm, width)

Creates an EOR scalable vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe output SVE vector register.
PgPredicate register for predicated instruction, P0-P7.
Zd_The first input SVE vector register. Must match Zd.
ZmThe second input SVE vector register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_eor_vector

#define INSTR_CREATE_eor_vector (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_eor, Rd, Rm, Rn)

Creates a EOR vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_esb

#define INSTR_CREATE_esb (   dc)    instr_create_0dst_0src(dc, OP_esb)

Creates a ESB instruction.

This macro is used to encode the forms:

*    ESB
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.

◆ INSTR_CREATE_fabd_vector

#define INSTR_CREATE_fabd_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_fabd, Rd, Rm, Rn, width)

Creates a FABD vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fabs_scalar

#define INSTR_CREATE_fabs_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fabs, Rd, Rm)

Creates a FABS floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.

◆ INSTR_CREATE_facge

#define INSTR_CREATE_facge (   dc,
  Rd,
  Rn,
  Rm 
)    instr_create_1dst_2src(dc, OP_facge, Rd, Rn, Rm)

Creates a FACGE instruction.

This macro is used to encode the forms:

*    FACGE   <Hd>, <Hn>, <Hm>
*    FACGE   <V><d>, <V><n>, <V><m>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RmThe third source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)

◆ INSTR_CREATE_facge_vector

#define INSTR_CREATE_facge_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_3src(dc, OP_facge, Rd, Rn, Rm, Rm_elsz)

Creates a FACGE vector instruction.

This macro is used to encode the forms:

*    FACGE   <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts>
*    FACGE   <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_facgt

#define INSTR_CREATE_facgt (   dc,
  Rd,
  Rn,
  Rm 
)    instr_create_1dst_2src(dc, OP_facgt, Rd, Rn, Rm)

Creates a FACGT instruction.

This macro is used to encode the forms:

*    FACGT   <Hd>, <Hn>, <Hm>
*    FACGT   <V><d>, <V><n>, <V><m>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RmThe third source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)

◆ INSTR_CREATE_facgt_vector

#define INSTR_CREATE_facgt_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_3src(dc, OP_facgt, Rd, Rn, Rm, Rm_elsz)

Creates a FACGT vector instruction.

This macro is used to encode the forms:

*    FACGT   <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts>
*    FACGT   <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fadd_scalar

#define INSTR_CREATE_fadd_scalar (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_fadd, Rd, Rm, Rn)

Creates a FADD floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_fadd_vector

#define INSTR_CREATE_fadd_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_fadd, Rd, Rm, Rn, width)

Creates a FADD vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_faddp_scalar

#define INSTR_CREATE_faddp_scalar (   dc,
  Rd,
  Rn,
  Rn_elsz 
)    instr_create_1dst_2src(dc, OP_faddp, Rd, Rn, Rn_elsz)

Creates a FADDP instruction.

This macro is used to encode the forms:

*    FADDP   <Hd>, <Hn>.2H
*    FADDP   <V><d>, <Sn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rn_elszThe element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_faddp_vector

#define INSTR_CREATE_faddp_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_3src(dc, OP_faddp, Rd, Rn, Rm, Rm_elsz)

Creates a FADDP instruction.

This macro is used to encode the forms:

*    FADDP   <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts>
*    FADDP   <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fccmp

#define INSTR_CREATE_fccmp (   dc,
  Rn,
  Rm,
  nzcv,
  condition_code 
)    INSTR_PRED(instr_create_0dst_3src(dc, OP_fccmp, Rn, Rm, nzcv), (condition_code))

Creates a FCCMP instruction.

This macro is used to encode the forms:

*    FCCMP   <Dn>, <Dm>, #<imm>, <cond>
*    FCCMP   <Hn>, <Hm>, #<imm>, <cond>
*    FCCMP   <Sn>, <Sm>, #<imm>, <cond>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RnThe first source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)
RmThe second source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)
nzcvThe 4 bit NZCV flags value used if the input condition is false. (use opnd_create_immed_uint() to create the operand, e.g. opnd_create_immed_uint(val, OPSZ_4b)).
condition_codeThe comparison condition specified by dr_pred_type_t, e.g. DR_PRED_EQ.

◆ INSTR_CREATE_fccmpe

#define INSTR_CREATE_fccmpe (   dc,
  Rn,
  Rm,
  nzcv,
  condition_code 
)    INSTR_PRED(instr_create_0dst_3src(dc, OP_fccmpe, Rn, Rm, nzcv), (condition_code))

Creates a FCCMPE instruction.

This macro is used to encode the forms:

*    FCCMPE   <Dn>, <Dm>, #<imm>, <cond>
*    FCCMPE   <Hn>, <Hm>, #<imm>, <cond>
*    FCCMPE   <Sn>, <Sm>, #<imm>, <cond>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RnThe first source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)
RmThe second source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)
nzcvThe 4 bit NZCV flags value used if the input condition is false. (use opnd_create_immed_uint() to create the operand, e.g. opnd_create_immed_uint(val, OPSZ_4b)).
condition_codeThe comparison condition specified by dr_pred_type_t, e.g. DR_PRED_EQ.

◆ INSTR_CREATE_fcmeq

#define INSTR_CREATE_fcmeq (   dc,
  Rd,
  Rn,
  Rm 
)    instr_create_1dst_2src(dc, OP_fcmeq, Rd, Rn, Rm)

Creates a FCMEQ instruction.

This macro is used to encode the forms:

*    FCMEQ   <Hd>, <Hn>, <Hm>
*    FCMEQ   <V><d>, <V><n>, <V><m>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RmThe third source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)

◆ INSTR_CREATE_fcmeq_vector

#define INSTR_CREATE_fcmeq_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_3src(dc, OP_fcmeq, Rd, Rn, Rm, Rm_elsz)

Creates a FCMEQ instruction.

This macro is used to encode the forms:

*    FCMEQ   <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts>
*    FCMEQ   <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fcmeq_vector_zero

#define INSTR_CREATE_fcmeq_vector_zero (   dc,
  Rd,
  Rn,
  Rn_elsz 
)    instr_create_1dst_3src(dc, OP_fcmeq, Rd, Rn, opnd_create_immed_float(0), Rn_elsz)

Creates a FCMEQ instruction.

This macro is used to encode the forms:

*    FCMEQ   <Hd>.<Ts>, <Hn>.<Ts>, #0
*    FCMEQ   <Dd>.<Ts>, <Dn>.<Ts>, #0
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rn_elszThe element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fcmeq_zero

#define INSTR_CREATE_fcmeq_zero (   dc,
  Rd,
  Rn 
)    instr_create_1dst_2src(dc, OP_fcmeq, Rd, Rn, opnd_create_immed_float(0))

Creates a FCMEQ instruction.

This macro is used to encode the forms:

*    FCMEQ   <Hd>, <Hn>, #0
*    FCMEQ   <V><d>, <V><n>, #0
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)

◆ INSTR_CREATE_fcmge_vector

#define INSTR_CREATE_fcmge_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_fcmge, Rd, Rm, Rn, width)

Creates a FCMGE vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fcmgt

#define INSTR_CREATE_fcmgt (   dc,
  Rd,
  Rn,
  Rm 
)    instr_create_1dst_2src(dc, OP_fcmgt, Rd, Rn, Rm)

Creates a FCMGT instruction.

This macro is used to encode the forms:

*    FCMGT   <Hd>, <Hn>, <Hm>
*    FCMGT   <V><d>, <V><n>, <V><m>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RmThe third source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)

◆ INSTR_CREATE_fcmgt_vector

#define INSTR_CREATE_fcmgt_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_3src(dc, OP_fcmgt, Rd, Rn, Rm, Rm_elsz)

Creates a FCMGT instruction.

This macro is used to encode the forms:

*    FCMGT   <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts>
*    FCMGT   <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fcmgt_vector_zero

#define INSTR_CREATE_fcmgt_vector_zero (   dc,
  Rd,
  Rn,
  Rn_elsz 
)    instr_create_1dst_3src(dc, OP_fcmgt, Rd, Rn, opnd_create_immed_float(0.0), Rn_elsz)

Creates a FCMGT instruction.

This macro is used to encode the forms:

*    FCMGT   <Hd>.<Ts>, <Hn>.<Ts>, #0
*    FCMGT   <Dd>.<Ts>, <Dn>.<Ts>, #0
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rn_elszThe element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fcmgt_zero

#define INSTR_CREATE_fcmgt_zero (   dc,
  Rd,
  Rn 
)    instr_create_1dst_2src(dc, OP_fcmgt, Rd, Rn, opnd_create_immed_float(0.0))

Creates a FCMGT instruction.

This macro is used to encode the forms:

*    FCMGT   <Hd>, <Hn>, #0
*    FCMGT   <V><d>, <V><n>, #0
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)

◆ INSTR_CREATE_fcmle_vector_zero

#define INSTR_CREATE_fcmle_vector_zero (   dc,
  Rd,
  Rn,
  Rn_elsz 
)    instr_create_1dst_3src(dc, OP_fcmle, Rd, Rn, opnd_create_immed_float(0.0), Rn_elsz)

Creates a FCMLE instruction.

This macro is used to encode the forms:

*    FCMLE   <Hd>.<Ts>, <Hn>.<Ts>, #0
*    FCMLE   <Dd>.<Ts>, <Dn>.<Ts>, #0
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rn_elszThe element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fcmle_zero

#define INSTR_CREATE_fcmle_zero (   dc,
  Rd,
  Rn 
)    instr_create_1dst_2src(dc, OP_fcmle, Rd, Rn, opnd_create_immed_float(0.0))

Creates a FCMLE instruction.

This macro is used to encode the forms:

*    FCMLE   <Hd>, <Hn>, #0
*    FCMLE   <V><d>, <V><n>, #0
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)

◆ INSTR_CREATE_fcmlt_vector_zero

#define INSTR_CREATE_fcmlt_vector_zero (   dc,
  Rd,
  Rn,
  Rn_elsz 
)    instr_create_1dst_3src(dc, OP_fcmlt, Rd, Rn, opnd_create_immed_float(0.0), Rn_elsz)

Creates a FCMLT instruction.

This macro is used to encode the forms:

*    FCMLT   <Hd>.<Ts>, <Hn>.<Ts>, #0
*    FCMLT   <Dd>.<Ts>, <Dn>.<Ts>, #0
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rn_elszThe element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fcmlt_zero

#define INSTR_CREATE_fcmlt_zero (   dc,
  Rd,
  Rn 
)    instr_create_1dst_2src(dc, OP_fcmlt, Rd, Rn, opnd_create_immed_float(0.0))

Creates a FCMLT instruction.

This macro is used to encode the forms:

*    FCMLT   <Hd>, <Hn>, #0
*    FCMLT   <V><d>, <V><n>, #0
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)

◆ INSTR_CREATE_fcmp

#define INSTR_CREATE_fcmp (   dc,
  Rn,
  Rm 
)    instr_create_0dst_2src(dc, OP_fcmp, Rn, Rm)

Creates a FCMP instruction.

This macro is used to encode the forms:

*    FCMP    <Dn>, <Dm>
*    FCMP    <Hn>, <Hm>
*    FCMP    <Sn>, <Sm>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RnThe first source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)
RmThe second source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)

◆ INSTR_CREATE_fcmp_zero

#define INSTR_CREATE_fcmp_zero (   dc,
  Rn 
)    instr_create_0dst_2src(dc, OP_fcmp, Rn, opnd_create_immed_float(0.0))

Creates a FCMP instruction.

This macro is used to encode the forms:

*    FCMP    <Dn>, #0.0
*    FCMP    <Hn>, #0.0
*    FCMP    <Sn>, #0.0
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RnThe first source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)

◆ INSTR_CREATE_fcmpe

#define INSTR_CREATE_fcmpe (   dc,
  Rn,
  Rm 
)    instr_create_0dst_2src(dc, OP_fcmpe, Rn, Rm)

Creates a FCMPE instruction.

This macro is used to encode the forms:

*    FCMPE   <Dn>, <Dm>
*    FCMPE   <Hn>, <Hm>
*    FCMPE   <Sn>, <Sm>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RnThe first source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)
RmThe second source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)

◆ INSTR_CREATE_fcmpe_zero

#define INSTR_CREATE_fcmpe_zero (   dc,
  Rn 
)    instr_create_0dst_2src(dc, OP_fcmpe, Rn, opnd_create_immed_float(0.0))

Creates a FCMPE instruction.

This macro is used to encode the forms:

*    FCMPE   <Dn>, #0.0
*    FCMPE   <Hn>, #0.0
*    FCMPE   <Sn>, #0.0
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RnThe first source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)

◆ INSTR_CREATE_fcsel

#define INSTR_CREATE_fcsel (   dc,
  Rd,
  Rn,
  Rm,
  condition_code 
)    INSTR_PRED(instr_create_1dst_2src(dc, OP_fcsel, Rd, Rn, Rm), (condition_code))

Creates a FCSEL instruction.

This macro is used to encode the forms:

*    FCSEL   <Dd>, <Dn>, <Dm>, <cond>
*    FCSEL   <Hd>, <Hn>, <Hm>, <cond>
*    FCSEL   <Sd>, <Sn>, <Sm>, <cond>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)
RnThe second source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)
RmThe third source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)
condition_codeThe comparison condition specified by dr_pred_type_t, e.g. DR_PRED_EQ.

◆ INSTR_CREATE_fcvt_scalar

#define INSTR_CREATE_fcvt_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fcvt, Rd, Rm)

Creates an FCVT floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point or integer output register.
RmFloating-point input register.

◆ INSTR_CREATE_fcvtas_scalar

#define INSTR_CREATE_fcvtas_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fcvtas, Rd, Rm)

Creates an FCVTAS floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point or integer output register.
RmFloating-point input register.

◆ INSTR_CREATE_fcvtas_vector

#define INSTR_CREATE_fcvtas_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_fcvtas, Rd, Rm, width)

Creates an FCVTAS vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe input vector register.
widthImmediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fcvtau_scalar

#define INSTR_CREATE_fcvtau_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fcvtau, Rd, Rm)

Creates an FCVTAU floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point or integer output register.
RmFloating-point input register.

◆ INSTR_CREATE_fcvtau_vector

#define INSTR_CREATE_fcvtau_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_fcvtau, Rd, Rm, width)

Creates an FCVTAU vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe input vector register.
widthImmediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fcvtms_scalar

#define INSTR_CREATE_fcvtms_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fcvtms, Rd, Rm)

Creates an FCVTMS floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point or integer output register.
RmFloating-point input register.

◆ INSTR_CREATE_fcvtms_vector

#define INSTR_CREATE_fcvtms_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_fcvtms, Rd, Rm, width)

Creates an FCVTMS vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe input vector register.
widthImmediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fcvtmu_scalar

#define INSTR_CREATE_fcvtmu_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fcvtmu, Rd, Rm)

Creates an FCVTMU floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point or integer output register.
RmFloating-point input register.

◆ INSTR_CREATE_fcvtmu_vector

#define INSTR_CREATE_fcvtmu_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_fcvtmu, Rd, Rm, width)

Creates an FCVTMU vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe input vector register.
widthImmediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fcvtns_scalar

#define INSTR_CREATE_fcvtns_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fcvtns, Rd, Rm)

Creates an FCVTNS floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point or integer output register.
RmFloating-point input register.

◆ INSTR_CREATE_fcvtns_vector

#define INSTR_CREATE_fcvtns_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_fcvtns, Rd, Rm, width)

Creates an FCVTNS vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
widthImmediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fcvtnu_scalar

#define INSTR_CREATE_fcvtnu_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fcvtnu, Rd, Rm)

Creates an FCVTNU floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point or integer output register.
RmFloating-point input register.

◆ INSTR_CREATE_fcvtnu_vector

#define INSTR_CREATE_fcvtnu_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_fcvtnu, Rd, Rm, width)

Creates an FCVTNU vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
widthImmediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fcvtps_scalar

#define INSTR_CREATE_fcvtps_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fcvtps, Rd, Rm)

Creates an FCVTPS floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point or integer output register.
RmFloating-point input register.

◆ INSTR_CREATE_fcvtps_vector

#define INSTR_CREATE_fcvtps_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_fcvtps, Rd, Rm, width)

Creates an FCVTPS vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
widthImmediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fcvtpu_scalar

#define INSTR_CREATE_fcvtpu_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fcvtpu, Rd, Rm)

Creates an FCVTPU floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point or integer output register.
RmFloating-point input register.

◆ INSTR_CREATE_fcvtpu_vector

#define INSTR_CREATE_fcvtpu_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_fcvtpu, Rd, Rm, width)

Creates an FCVTPU vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
widthImmediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fcvtzs_scalar

#define INSTR_CREATE_fcvtzs_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fcvtzs, Rd, Rm)

Creates an FCVTZS floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point or integer output register.
RmFloating-point input register.

◆ INSTR_CREATE_fcvtzs_scalar_fixed

#define INSTR_CREATE_fcvtzs_scalar_fixed (   dc,
  Rd,
  Rm,
  fbits 
)    instr_create_1dst_2src(dc, OP_fcvtzs, Rd, Rm, fbits)

Creates an FCVTZS scalar floating-point to fixed-point convert instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point or integer output register.
RmFloating-point input register.
fbitsThe number of bits after the binary point in the fixed-point destination.

◆ INSTR_CREATE_fcvtzs_vector

#define INSTR_CREATE_fcvtzs_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_fcvtzs, Rd, Rm, width)

Creates an FCVTZS vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
widthImmediate int of the vector element width. Must be OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fcvtzu_scalar

#define INSTR_CREATE_fcvtzu_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fcvtzu, Rd, Rm)

Creates an FCVTZU floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point or integer output register.
RmFloating-point input register.

◆ INSTR_CREATE_fcvtzu_scalar_fixed

#define INSTR_CREATE_fcvtzu_scalar_fixed (   dc,
  Rd,
  Rm,
  fbits 
)    instr_create_1dst_2src(dc, OP_fcvtzu, Rd, Rm, fbits)

Creates an FCVTZU scalar floating-point to fixed-point convert instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point or integer output register.
RmFloating-point input register.
fbitsThe number of bits after the binary point in the fixed-point destination.

◆ INSTR_CREATE_fcvtzu_vector

#define INSTR_CREATE_fcvtzu_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_fcvtzu, Rd, Rm, width)

Creates an FCVTZU vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
widthImmediate int of the vector element width. Must be OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fcvtzu_vector_fixed

#define INSTR_CREATE_fcvtzu_vector_fixed (   dc,
  Rd,
  Rm,
  width,
  fbits 
)    instr_create_1dst_3src(dc, OP_fcvtzu, Rd, Rm, width, fbits)

Creates an FCVTZU vector floating-point to fixed-point convert instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe input register.
widthThe vector element width. Use either OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
fbitsThe number of bits after the binary point in the fixed-point destination element.

◆ INSTR_CREATE_fdiv_scalar

#define INSTR_CREATE_fdiv_scalar (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_fdiv, Rd, Rm, Rn)

Creates a FDIV floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_fdiv_vector

#define INSTR_CREATE_fdiv_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_fdiv, Rd, Rm, Rn, width)

Creates a FDIV vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fmadd_scalar

#define INSTR_CREATE_fmadd_scalar (   dc,
  Rd,
  Rm,
  Rn,
  Ra 
)    instr_create_1dst_3src(dc, OP_fmadd, Rd, Rm, Rn, Ra)

Creates a FMADD floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
RaThe third input register.

◆ INSTR_CREATE_fmax_scalar

#define INSTR_CREATE_fmax_scalar (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_fmax, Rd, Rm, Rn)

Creates a FMAX floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_fmax_vector

#define INSTR_CREATE_fmax_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_fmax, Rd, Rm, Rn, width)

Creates a FMAX vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fmaxnm_scalar

#define INSTR_CREATE_fmaxnm_scalar (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_fmaxnm, Rd, Rm, Rn)

Creates a FMAXNM floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_fmaxnm_vector

#define INSTR_CREATE_fmaxnm_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_fmaxnm, Rd, Rm, Rn, width)

Creates a FMAXNM vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fmaxnmp_scalar

#define INSTR_CREATE_fmaxnmp_scalar (   dc,
  Rd,
  Rn,
  Rn_elsz 
)    instr_create_1dst_2src(dc, OP_fmaxnmp, Rd, Rn, Rn_elsz)

Creates a FMAXNMP instruction.

This macro is used to encode the forms:

*    FMAXNMP <Hd>, <Hn>.2H
*    FMAXNMP <V><d>, <Sn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rn_elszThe element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fmaxnmp_vector

#define INSTR_CREATE_fmaxnmp_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_3src(dc, OP_fmaxnmp, Rd, Rn, Rm, Rm_elsz)

Creates a FMAXNMP instruction.

This macro is used to encode the forms:

*    FMAXNMP <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts>
*    FMAXNMP <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fmaxp_scalar

#define INSTR_CREATE_fmaxp_scalar (   dc,
  Rd,
  Rn,
  Rn_elsz 
)    instr_create_1dst_2src(dc, OP_fmaxp, Rd, Rn, Rn_elsz)

Creates a FMAXP instruction.

This macro is used to encode the forms:

*    FMAXP   <Hd>, <Hn>.2H
*    FMAXP   <V><d>, <Sn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rn_elszThe element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fmaxp_vector

#define INSTR_CREATE_fmaxp_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_3src(dc, OP_fmaxp, Rd, Rn, Rm, Rm_elsz)

Creates a FMAXP instruction.

This macro is used to encode the forms:

*    FMAXP   <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts>
*    FMAXP   <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fmin_scalar

#define INSTR_CREATE_fmin_scalar (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_fmin, Rd, Rm, Rn)

Creates a FMIN floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_fmin_vector

#define INSTR_CREATE_fmin_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_fmin, Rd, Rm, Rn, width)

Creates a FMIN vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fminnm_scalar

#define INSTR_CREATE_fminnm_scalar (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_fminnm, Rd, Rm, Rn)

Creates a FMINNM floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_fminnm_vector

#define INSTR_CREATE_fminnm_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_fminnm, Rd, Rm, Rn, width)

Creates a FMINNM vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fminnmp_scalar

#define INSTR_CREATE_fminnmp_scalar (   dc,
  Rd,
  Rn,
  Rn_elsz 
)    instr_create_1dst_2src(dc, OP_fminnmp, Rd, Rn, Rn_elsz)

Creates a FMINNMP instruction.

This macro is used to encode the forms:

*    FMINNMP <Hd>, <Hn>.2H
*    FMINNMP <V><d>, <Sn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rn_elszThe element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fminnmp_vector

#define INSTR_CREATE_fminnmp_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_3src(dc, OP_fminnmp, Rd, Rn, Rm, Rm_elsz)

Creates a FMINNMP instruction.

This macro is used to encode the forms:

*    FMINNMP <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts>
*    FMINNMP <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fminnmv_vector

#define INSTR_CREATE_fminnmv_vector (   dc,
  Rd,
  Rn,
  Rn_elsz 
)    instr_create_1dst_2src(dc, OP_fminnmv, Rd, Rn, Rn_elsz)

Creates a FMINNMV instruction.

This macro is used to encode the forms:

*    FMINNMV <Hd>, <Hn>.<Ts>
*    FMINNMV <Sd>, <Sn>.4S
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits) or S (singleword, 32 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rn_elszThe element size for Rn. Can be OPND_CREATE_HALF() or OPND_CREATE_SINGLE()

◆ INSTR_CREATE_fminp_scalar

#define INSTR_CREATE_fminp_scalar (   dc,
  Rd,
  Rn,
  Rn_elsz 
)    instr_create_1dst_2src(dc, OP_fminp, Rd, Rn, Rn_elsz)

Creates a FMINP instruction.

This macro is used to encode the forms:

*    FMINP   <Hd>, <Hn>.2H
*    FMINP   <V><d>, <Sn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rn_elszThe element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fminp_vector

#define INSTR_CREATE_fminp_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_3src(dc, OP_fminp, Rd, Rn, Rm, Rm_elsz)

Creates a FMINP instruction.

This macro is used to encode the forms:

*    FMINP   <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts>
*    FMINP   <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fmla_vector

#define INSTR_CREATE_fmla_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_4src(dc, OP_fmla, Rd, Rd, Rn, Rm, Rm_elsz)

Creates a FMLA instruction.

This macro is used to encode the forms:

*    FMLA    <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts>
*    FMLA    <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first source and destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fmla_vector_idx

#define INSTR_CREATE_fmla_vector_idx (   dc,
  Rd,
  Rn,
  Rm,
  index,
  Rm_elsz 
)    instr_create_1dst_5src(dc, OP_fmla, Rd, Rd, Rn, Rm, index, Rm_elsz)

Creates a FMLA instruction.

This macro is used to encode the forms:

*    FMLA    <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.H[<index>]
*    FMLA    <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Tb>[<index>]
*    FMLA    <Hd>, <Hn>, <Hm>.H[<index>]
*    FMLA    <V><d>, <V><n>, <Sm>.<Ts>[<index>]
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first source and destination vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be Q (quadword, 128 bits)
indexThe immediate index for Rm
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fmlal2_vector

#define INSTR_CREATE_fmlal2_vector (   dc,
  Rd,
  Rn,
  Rm 
)    instr_create_1dst_4src(dc, OP_fmlal2, Rd, Rd, Rn, Rm, OPND_CREATE_HALF())

Creates a FMLAL2 instruction.

This macro is used to encode the forms:

*    FMLAL2  <Sd>.<Ts>, <Hn>.<Tb>, <Hm>.<Tb>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first source and destination vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register, S (singleword, 32 bits) or D (doubleword, 64 bits)
RmThe third source vector register, S (singleword, 32 bits) or D (doubleword, 64 bits)

◆ INSTR_CREATE_fmlal2_vector_idx

#define INSTR_CREATE_fmlal2_vector_idx (   dc,
  Rd,
  Rn,
  Rm,
  index 
)    instr_create_1dst_5src(dc, OP_fmlal2, Rd, Rd, Rn, Rm, index, OPND_CREATE_HALF())

Creates a FMLAL2 instruction.

This macro is used to encode the forms:

*    FMLAL2  <Sd>.<Ts>, <Hn>.<Tb>, <Hm>.H[<index>]
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first source and destination vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register, S (singleword, 32 bits) or D (doubleword, 64 bits)
RmThe third source vector register, Q (quadword, 128 bits)
indexThe immediate index for Rm

◆ INSTR_CREATE_fmlal_vector

#define INSTR_CREATE_fmlal_vector (   dc,
  Rd,
  Rn,
  Rm 
)    instr_create_1dst_4src(dc, OP_fmlal, Rd, Rd, Rn, Rm, OPND_CREATE_HALF())

Creates a FMLAL instruction.

This macro is used to encode the forms:

*    FMLAL   <Sd>.<Ts>, <Hn>.<Tb>, <Hm>.<Tb>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first source and destination vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register, S (singleword, 32 bits) or D (doubleword, 64 bits)
RmThe third source vector register, S (singleword, 32 bits) or D (doubleword, 64 bits)

◆ INSTR_CREATE_fmlal_vector_idx

#define INSTR_CREATE_fmlal_vector_idx (   dc,
  Rd,
  Rn,
  Rm,
  index 
)    instr_create_1dst_5src(dc, OP_fmlal, Rd, Rd, Rn, Rm, index, OPND_CREATE_HALF())

Creates a FMLAL instruction.

This macro is used to encode the forms:

*    FMLAL   <Sd>.<Ts>, <Hn>.<Tb>, <Hm>.H[<index>]
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first source and destination vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register, S (singleword, 32 bits) or D (doubleword, 64 bits)
RmThe third source vector register, Q (quadword, 128 bits)
indexThe immediate index for Rm

◆ INSTR_CREATE_fmls_vector

#define INSTR_CREATE_fmls_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_4src(dc, OP_fmls, Rd, Rd, Rn, Rm, Rm_elsz)

Creates a FMLS instruction.

This macro is used to encode the forms:

*    FMLS    <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts>
*    FMLS    <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first source and destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fmls_vector_idx

#define INSTR_CREATE_fmls_vector_idx (   dc,
  Rd,
  Rn,
  Rm,
  index,
  Rm_elsz 
)    instr_create_1dst_5src(dc, OP_fmls, Rd, Rd, Rn, Rm, index, Rm_elsz)

Creates a FMLS instruction.

This macro is used to encode the forms:

*    FMLS    <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.H[<index>]
*    FMLS    <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Tb>[<index>]
*    FMLS    <Hd>, <Hn>, <Hm>.H[<index>]
*    FMLS    <V><d>, <V><n>, <Sm>.<Ts>[<index>]
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first source and destination vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be Q (quadword, 128 bits)
indexThe immediate index for Rm
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fmlsl2_vector

#define INSTR_CREATE_fmlsl2_vector (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_4src(dc, OP_fmlsl2, Rd, Rd, Rm, Rn, OPND_CREATE_HALF())

Creates a FMLSL2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register. The instruction also reads this register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_fmlsl2_vector_idx

#define INSTR_CREATE_fmlsl2_vector_idx (   dc,
  Rd,
  Rm,
  Rn,
  index 
)    instr_create_1dst_5src(dc, OP_fmlsl2, Rd, Rd, Rm, Rn, index, OPND_CREATE_HALF())

Creates a FMLSL2 indexed vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register. The instruction also reads this register.
RmThe first input register.
RnThe second input register.
indexThe first input register's vector element index.

◆ INSTR_CREATE_fmlsl_vector

#define INSTR_CREATE_fmlsl_vector (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_4src(dc, OP_fmlsl, Rd, Rd, Rm, Rn, OPND_CREATE_HALF())

Creates a FMLSL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register. The instruction also reads this register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_fmlsl_vector_idx

#define INSTR_CREATE_fmlsl_vector_idx (   dc,
  Rd,
  Rm,
  Rn,
  index 
)    instr_create_1dst_5src(dc, OP_fmlsl, Rd, Rd, Rm, Rn, index, OPND_CREATE_HALF())

Creates a FMLSL indexed vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register. The instruction also reads this register.
RmThe first input register.
RnThe second input register.
indexThe first input register's vector element index.

◆ INSTR_CREATE_fmov_general

#define INSTR_CREATE_fmov_general (   dc,
  Rd,
  Rn 
)    instr_create_1dst_1src(dc, OP_fmov, Rd, Rn)

disabled_until_i4106_is_fixed Creates an FMOV instruction to move between GPRs and floating point registers. This macro is used to encode the forms:

*    FMOV    <Wd>, <Hn>
*    FMOV    <Wd>, <Sn>
*    FMOV    <Xd>, <Dn>
*    FMOV    <Xd>, <Hn>
*    FMOV    <Dd>, <Xn>
*    FMOV    <Hd>, <Wn>
*    FMOV    <Hd>, <Xn>
*    FMOV    <Sd>, <Wn>
*    FMOV    <Dd>, <Dn>
*    FMOV    <Hd>, <Hn>
*    FMOV    <Sd>, <Sn>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RnThe first input register.

◆ INSTR_CREATE_fmov_scalar

#define INSTR_CREATE_fmov_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fmov, Rd, Rm)

Creates an FMOV floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.

◆ INSTR_CREATE_fmov_scalar_imm

#define INSTR_CREATE_fmov_scalar_imm (   dc,
  Rd,
 
)    instr_create_1dst_1src(dc, OP_fmov, Rd, f)

Creates an FMOV immediate to scalar floating point move instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output scalar register.
fThe source immediate floating point opnd.

◆ INSTR_CREATE_fmov_upper_vec

#define INSTR_CREATE_fmov_upper_vec (   dc,
  Rd,
  Rn 
)
Value:

Creates an FMOV instruction to move between GPRs and floating point registers.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RnThe first input vector register.

◆ INSTR_CREATE_fmov_vector_imm

#define INSTR_CREATE_fmov_vector_imm (   dc,
  Rd,
  f,
  width 
)    instr_create_1dst_2src(dc, OP_fmov, Rd, f, width)

Creates an FMOV immediate to vector floating point move instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output vector register.
fThe source immediate floating point opnd.
widthThe output vector element width. Use either OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_fmsub_scalar

#define INSTR_CREATE_fmsub_scalar (   dc,
  Rd,
  Rm,
  Rn,
  Ra 
)    instr_create_1dst_3src(dc, OP_fmsub, Rd, Rm, Rn, Ra)

Creates a FMSUB floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
RaThe third input register.

◆ INSTR_CREATE_fmul_scalar

#define INSTR_CREATE_fmul_scalar (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_fmul, Rd, Rm, Rn)

Creates a FMUL floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_fmul_vector

#define INSTR_CREATE_fmul_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_fmul, Rd, Rm, Rn, width)

Creates a FMUL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fmulx

#define INSTR_CREATE_fmulx (   dc,
  Rd,
  Rn,
  Rm 
)    instr_create_1dst_2src(dc, OP_fmulx, Rd, Rn, Rm)

Creates a FMULX instruction.

This macro is used to encode the forms:

*    FMULX   <Hd>, <Hn>, <Hm>
*    FMULX   <V><d>, <V><n>, <V><m>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RmThe third source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)

◆ INSTR_CREATE_fmulx_vector

#define INSTR_CREATE_fmulx_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_3src(dc, OP_fmulx, Rd, Rn, Rm, Rm_elsz)

Creates a FMULX instruction.

This macro is used to encode the forms:

*    FMULX   <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts>
*    FMULX   <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fmulx_vector_idx

#define INSTR_CREATE_fmulx_vector_idx (   dc,
  Rd,
  Rn,
  Rm,
  index,
  Rm_elsz 
)    instr_create_1dst_4src(dc, OP_fmulx, Rd, Rn, Rm, index, Rm_elsz)

Creates a FMULX instruction.

This macro is used to encode the forms:

*    FMULX   <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.H[<index>]
*    FMULX   <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Tb>[<index>]
*    FMULX   <Hd>, <Hn>, <Hm>.H[<index>]
*    FMULX   <V><d>, <V><n>, <Sm>.<Ts>[<index>]
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register, Q (quadword, 128 bits)
indexThe immediate index for Rm
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fneg_scalar

#define INSTR_CREATE_fneg_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fneg, Rd, Rm)

Creates a FNEG floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.

◆ INSTR_CREATE_fnmadd_scalar

#define INSTR_CREATE_fnmadd_scalar (   dc,
  Rd,
  Rm,
  Rn,
  Ra 
)    instr_create_1dst_3src(dc, OP_fnmadd, Rd, Rm, Rn, Ra)

Creates a FNMADD floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
RaThe third input register.

◆ INSTR_CREATE_fnmsub_scalar

#define INSTR_CREATE_fnmsub_scalar (   dc,
  Rd,
  Rm,
  Rn,
  Ra 
)    instr_create_1dst_3src(dc, OP_fnmsub, Rd, Rm, Rn, Ra)

Creates a FNMSUB floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
RaThe third input register.

◆ INSTR_CREATE_fnmul_scalar

#define INSTR_CREATE_fnmul_scalar (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_fnmul, Rd, Rm, Rn)

Creates a FNMUL floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_frecpe

#define INSTR_CREATE_frecpe (   dc,
  Rd,
  Rn 
)    instr_create_1dst_1src(dc, OP_frecpe, Rd, Rn)

Creates a FRECPE instruction.

This macro is used to encode the forms:

*    FRECPE  <Hd>, <Hn>
*    FRECPE  <V><d>, <V><n>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)

◆ INSTR_CREATE_frecpe_vector

#define INSTR_CREATE_frecpe_vector (   dc,
  Rd,
  Rn,
  Rn_elsz 
)    instr_create_1dst_2src(dc, OP_frecpe, Rd, Rn, Rn_elsz)

Creates a FRECPE instruction.

This macro is used to encode the forms:

*    FRECPE  <Hd>.<Ts>, <Hn>.<Ts>
*    FRECPE  <Dd>.<Ts>, <Dn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rn_elszThe element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_frecps

#define INSTR_CREATE_frecps (   dc,
  Rd,
  Rn,
  Rm 
)    instr_create_1dst_2src(dc, OP_frecps, Rd, Rn, Rm)

Creates a FRECPS instruction.

This macro is used to encode the forms:

*    FRECPS  <Hd>, <Hn>, <Hm>
*    FRECPS  <V><d>, <V><n>, <V><m>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RmThe third source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)

◆ INSTR_CREATE_frecps_vector

#define INSTR_CREATE_frecps_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_3src(dc, OP_frecps, Rd, Rn, Rm, Rm_elsz)

Creates a FRECPS instruction.

This macro is used to encode the forms:

*    FRECPS  <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts>
*    FRECPS  <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_frinta_scalar

#define INSTR_CREATE_frinta_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_frinta, Rd, Rm)

Creates a FRINTA floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.

◆ INSTR_CREATE_frinta_vector

#define INSTR_CREATE_frinta_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_frinta, Rd, Rm, width)

Creates a FRINTA vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe input vector register.
widthImmediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_frinti_scalar

#define INSTR_CREATE_frinti_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_frinti, Rd, Rm)

Creates a FRINTI floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.

◆ INSTR_CREATE_frinti_vector

#define INSTR_CREATE_frinti_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_frinti, Rd, Rm, width)

Creates a FRINTI vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe input vector register.
widthImmediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_frintm_scalar

#define INSTR_CREATE_frintm_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_frintm, Rd, Rm)

Creates a FRINTM floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.

◆ INSTR_CREATE_frintm_vector

#define INSTR_CREATE_frintm_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_frintm, Rd, Rm, width)

Creates a FRINTM vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe input vector register.
widthImmediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_frintn_scalar

#define INSTR_CREATE_frintn_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_frintn, Rd, Rm)

Creates a FRINTN floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.

◆ INSTR_CREATE_frintn_vector

#define INSTR_CREATE_frintn_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_frintn, Rd, Rm, width)

Creates a FRINTN vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe input vector register.
widthImmediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_frintp_scalar

#define INSTR_CREATE_frintp_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_frintp, Rd, Rm)

Creates a FRINTP floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.

◆ INSTR_CREATE_frintp_vector

#define INSTR_CREATE_frintp_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_frintp, Rd, Rm, width)

Creates a FRINTP vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe input vector register.
widthImmediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_frintx_scalar

#define INSTR_CREATE_frintx_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_frintx, Rd, Rm)

Creates a FRINTX floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.

◆ INSTR_CREATE_frintx_vector

#define INSTR_CREATE_frintx_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_frintx, Rd, Rm, width)

Creates a FRINTX vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe input vector register.
widthImmediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_frintz_scalar

#define INSTR_CREATE_frintz_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_frintz, Rd, Rm)

Creates a FRINTZ floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.

◆ INSTR_CREATE_frintz_vector

#define INSTR_CREATE_frintz_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_frintz, Rd, Rm, width)

Creates a FRINTZ vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe input vector register.
widthImmediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_frsqrte

#define INSTR_CREATE_frsqrte (   dc,
  Rd,
  Rn 
)    instr_create_1dst_1src(dc, OP_frsqrte, Rd, Rn)

Creates a FRSQRTE instruction.

This macro is used to encode the forms:

*    FRSQRTE <Hd>, <Hn>
*    FRSQRTE <V><d>, <V><n>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)

◆ INSTR_CREATE_frsqrte_vector

#define INSTR_CREATE_frsqrte_vector (   dc,
  Rd,
  Rn,
  Rn_elsz 
)    instr_create_1dst_2src(dc, OP_frsqrte, Rd, Rn, Rn_elsz)

Creates a FRSQRTE instruction.

This macro is used to encode the forms:

*    FRSQRTE <Hd>.<Ts>, <Hn>.<Ts>
*    FRSQRTE <Dd>.<Ts>, <Dn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rn_elszThe element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_frsqrts

#define INSTR_CREATE_frsqrts (   dc,
  Rd,
  Rn,
  Rm 
)    instr_create_1dst_2src(dc, OP_frsqrts, Rd, Rn, Rm)

Creates a FRSQRTS instruction.

This macro is used to encode the forms:

*    FRSQRTS <Hd>, <Hn>, <Hm>
*    FRSQRTS <V><d>, <V><n>, <V><m>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RmThe third source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)

◆ INSTR_CREATE_frsqrts_vector

#define INSTR_CREATE_frsqrts_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_3src(dc, OP_frsqrts, Rd, Rn, Rm, Rm_elsz)

Creates a FRSQRTS instruction.

This macro is used to encode the forms:

*    FRSQRTS <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts>
*    FRSQRTS <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fsqrt_scalar

#define INSTR_CREATE_fsqrt_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fsqrt, Rd, Rm)

Creates a FSQRT floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.

◆ INSTR_CREATE_fsqrt_vector

#define INSTR_CREATE_fsqrt_vector (   dc,
  Rd,
  Rn,
  Rn_elsz 
)    instr_create_1dst_2src(dc, OP_fsqrt, Rd, Rn, Rn_elsz)

Creates a FSQRT instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rn_elszThe element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fsub_scalar

#define INSTR_CREATE_fsub_scalar (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_fsub, Rd, Rm, Rn)

Creates a FSUB floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_fsub_vector

#define INSTR_CREATE_fsub_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_fsub, Rd, Rm, Rn, width)

Creates a FSUB vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_ld1_multi_1

#define INSTR_CREATE_ld1_multi_1 (   dc,
  q,
  r,
 
)    instr_create_1dst_2src(dc, OP_ld1, q, r, s)

Creates an Advanced SIMD (NEON) LD1 instruction to load multiple single element structures to one vector register, e.g. LD1 {V0.4H},[X0].

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
qThe destination vector register operand.
rThe source memory operand.
sThe size of the vector element.

◆ INSTR_CREATE_ld2

#define INSTR_CREATE_ld2 (   dc,
  Vt1,
  Vt2,
  Xn,
  index,
  elsz 
)    instr_create_2dst_3src(dc, OP_ld2, Vt1, Vt2, Xn, index, elsz)

Creates an Advanced SIMD (NEON) LD2 instruction to load a 2-element structure to the index of two vector registers, e.g. LD2 {V0.4H, V1.4H}[5], [X0].

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
Vt1The first destination vector register operand.
Vt2The second destination vector register operand.
XnThe stack-pointer or GPR to load into Vt1 and Vt2.
indexThe vector element index.
elszThe vector element size

◆ INSTR_CREATE_ld2_2

#define INSTR_CREATE_ld2_2 (   dc,
  Vt1,
  Vt2,
  Xn,
  Xnd,
  index,
  offset,
  elsz 
)    instr_create_3dst_5src(dc, OP_ld2, Vt1, Vt2, Xn, Xnd, index, Xn, offset, elsz)

Creates an Advanced SIMD (NEON) LD2 instruction to load a 2-element structure to the index of two vector registers with post-indexing, e.g. LD2 {V0.4H, V1.4H}[5], [X0], X1.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
Vt1The first destination vector register operand.
Vt2The second destination vector register operand.
XnThe stack-pointer or register to load into Vt and Vt2.
XndThe disposition of Xn.
indexThe index of the destination vectors.
offsetThe post-index offset.
elszThe vector element size

◆ INSTR_CREATE_ld2_multi_2

#define INSTR_CREATE_ld2_multi_2 (   dc,
  Vt1,
  Vt2,
  Xn,
  disp,
  offset,
  elsz 
)    instr_create_3dst_4src(dc, OP_ld2, Vt1, Vt2, Xn, disp, Xn, offset, elsz)

Creates an Advanced SIMD (NEON) LD2 instruction to load multiple 2-element structures to two vector registers with post-indexing, e.g. LD2 {V0.4H, V1.4H}, [X0], #32.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
Vt1The destination vector register operand.
Vt2The second destination vector register operand.
XnThe stack-pointer or GPR to load into Vt1 and Vt2.
dispThe disposition of Xn.
offsetThe post-index offset.
elszThe vector element size

◆ INSTR_CREATE_ld2r

#define INSTR_CREATE_ld2r (   dc,
  Vt1,
  Vt2,
  Xn,
  elsz 
)    instr_create_2dst_2src(dc, OP_ld2r, Vt1, Vt2, Xn, elsz)

Creates an Advanced SIMD (NEON) LD2R instruction to load and replicate a single 2-element structure to all lanes of two vector registers, e.g. LD2R {V0.4H, V1.4H}, [X0].

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
Vt1The first destination vector register operand.
Vt2The second destination vector register operand.
XnThe stack-pointer or GPR to load into Vt1 and Vt2.
elszThe vector element size

◆ INSTR_CREATE_ld2r_2

#define INSTR_CREATE_ld2r_2 (   dc,
  Vt1,
  Vt2,
  Xn,
  Xnd,
  Xm,
  elsz 
)    instr_create_3dst_4src(dc, OP_ld2r, Vt1, Vt2, Xn, Xnd, Xn, Xm, elsz)

Creates an Advanced SIMD (NEON) LD2R instruction to load and replicate a single 2-element structure to all lanes of two vector registers with post-indexing , e.g. LD2R {V0.4H, V1.4H}, [X0], X1.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
Vt1The destination vector register operand.
Vt2The second destination vector register operand.
XnThe stack-pointer or GPR to load into Vt and Vt2.
XndDisposition of Xn.
XmThe post-index offset.
elszThe vector element size

◆ INSTR_CREATE_ld3

#define INSTR_CREATE_ld3 (   dc,
  Vt1,
  Vt2,
  Vt3,
  Xn,
  index,
  elsz 
)    instr_create_3dst_3src(dc, OP_ld3, Vt1, Vt2, Vt3, Xn, index, elsz)

Creates an Advanced SIMD (NEON) LD3 instruction to load a single 3-element structure to the index of three vector registers, e.g. LD3 {V0.4H, V1.4H, V2.4H}[15], [X0].

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
Vt1The first destination vector register operand.
Vt2The second destination vector register operand.
Vt3The third destination vector register operand.
XnThe GPR to load into Vt1, Vt2 and Vt3.
indexThe index of the destination vectors.
elszThe vector element size

◆ INSTR_CREATE_ld3_2

#define INSTR_CREATE_ld3_2 (   dc,
  Vt1,
  Vt2,
  Vt3,
  Xn,
  Xnd,
  index,
  offset,
  elsz 
)    instr_create_4dst_5src(dc, OP_ld3, Vt1, Vt2, Vt3, Xn, Xnd, index, Xn, offset, elsz)

Creates an Advanced SIMD (NEON) LD3 instruction to load a single 3-element structure to the index of three vector registers with post-index offset, e.g. LD3 {V0.4H, V1.4H, V2.4H}[15], [X0], X1.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
Vt1The first destination vector register operand.
Vt2The second destination vector register operand.
Vt3The third destination vector register operand.
XnThe register to load into Vt, Vt2 and Vt3.
indexThe immediate or GPR post-index offset.
XndThe disposition of Xn.
offsetThe immediate or GPR post-index offset.
elszThe vector element size

◆ INSTR_CREATE_ld3_multi

#define INSTR_CREATE_ld3_multi (   dc,
  Vt1,
  Vt2,
  Vt3,
  Xn,
  elsz 
)    instr_create_3dst_2src(dc, OP_ld3, Vt1, Vt2, Vt3, Xn, elsz)

Creates an Advanced SIMD (NEON) LD3 instruction to load multiple 3-element structures from memory to three vector register, e.g. LD3 {V0.4H, V1.4H, V2.4H}, [X0].

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
Vt1The first destination vector register operand.
Vt2The second destination vector register operand.
Vt3The third destination vector register operand.
XnThe stack-pointer or GPR to load into Vt1, Vt2 and Vt3.
elszThe vector element size

◆ INSTR_CREATE_ld3_multi_2

#define INSTR_CREATE_ld3_multi_2 (   dc,
  Vt1,
  Vt2,
  Vt3,
  Xn,
  Xnd,
  Xm,
  elsz 
)    instr_create_4dst_4src(dc, OP_ld3, Vt1, Vt2, Vt3, Xn, Xnd, Xn, Xm, elsz)

Creates an Advanced SIMD (NEON) LD3 instruction to load multiple 3-element structures from memory to the index of three vector registers with post-index offset, e.g. LD3 {V0.4H, V1.4H, V2.4H}, [X0], X1.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
Vt1The first destination vector register operand.
Vt2The second destination vector register operand.
Vt3The third destination vector register operand.
XnThe stack-pointer or GPR to load into Vt1, Vt2 and Vt3.
XndThe disposition of Xn.
XmThe post-index offset.
elszThe vector element size

◆ INSTR_CREATE_ld3r

#define INSTR_CREATE_ld3r (   dc,
  Vt1,
  Vt2,
  Vt3,
  Xn,
  elsz 
)    instr_create_3dst_2src(dc, OP_ld3r, Vt1, Vt2, Vt3, Xn, elsz)

Creates an Advanced SIMD (NEON) LD3 instruction to load and replicate a single 3-element structure to the index of three vector registers, e.g. LD3 {V0.4H, V1.4H, V2.4H}[15], [X0].

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
Vt1The first destination vector register operand.
Vt2The second destination vector register operand.
Vt3The third destination vector register operand.
XnThe stack-pointer or GPR to load into Vt1, Vt2 and Vt3.
elszThe vector element size

◆ INSTR_CREATE_ld3r_2

#define INSTR_CREATE_ld3r_2 (   dc,
  Vt1,
  Vt2,
  Vt3,
  Xn,
  Xnd,
  offset,
  elsz 
)    instr_create_4dst_4src(dc, OP_ld3r, Vt1, Vt2, Vt3, Xn, Xnd, Xn, offset, elsz)

Creates an Advanced SIMD (NEON) LD3 instruction to load and replicate a single 3-element structure to the index of three vector registers with post-index offset, e.g. LD3 {V0.4H, V1.4H, V2.4H}[15], [X0], X1.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
Vt1The first destination vector register operand.
Vt2The second destination vector register operand.
Vt3The third destination vector register operand.
XnThe stack-pointer or GPR to load into Vt1, Vt2 and Vt3.
XndThe disposition of Xn.
offsetThe immediate or GPR post-index offset
elszThe vector element size

◆ INSTR_CREATE_ld4

#define INSTR_CREATE_ld4 (   dc,
  Vt1,
  Vt2,
  Vt3,
  Vt4,
  Xn,
  index,
  elsz 
)    instr_create_4dst_3src(dc, OP_ld4, Vt1, Vt2, Vt3, Vt4, Xn, index, elsz)

Creates an Advanced SIMD (NEON) LD4 instruction to load single or multiple 4-element structures to four vector registers, e.g. LD4 {V0.4H, V1.4H, V2.4H, V3.4H}, [X0].

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
Vt1The first destination vector register operand.
Vt2The second destination vector register operand.
Vt3The third destination vector register operand.
Vt4The fourth destination vector register operand.
XnThe stack-pointer or register to load into the destination vectors.
indexThe immediate or GPR post-index offset.
elszThe vector element size

◆ INSTR_CREATE_ld4_2

#define INSTR_CREATE_ld4_2 (   dc,
  Vt1,
  Vt2,
  Vt3,
  Vt4,
  Xn,
  Xnd,
  index,
  offset,
  elsz 
)
Value:
instr_create_5dst_5src(dc, OP_ld4, Vt1, Vt2, Vt3, Vt4, Xn, Xnd, index, Xn, offset, \
elsz)

Creates an Advanced SIMD (NEON) LD4 instruction to load a single 4-element structures to four vector registers with post-index, e.g. LD4 {V0.4H, V1.4H, V2.4H, V3.4H}, [X0], X1.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
Vt1The first destination vector register operand.
Vt2The second destination vector register operand.
Vt3The third destination vector register operand.
Vt4The fourth destination vector register operand.
XnThe stack-pointer or GPR to load into the destination vectors.
XndThe disposition of Xn.
indexThe index of the destination vectors.
offsetThe post-index offset.
elszThe vector element size

◆ INSTR_CREATE_ld4_multi

#define INSTR_CREATE_ld4_multi (   dc,
  Vt1,
  Vt2,
  Vt3,
  Vt4,
  Xn,
  elsz 
)    instr_create_4dst_2src(dc, OP_ld4, Vt1, Vt2, Vt3, Vt4, Xn, elsz)

Creates an Advanced SIMD (NEON) LD4 instruction to load single or multiple 4-element structures to four vector registers, e.g. LD4 {V0.4H, V1.4H, V2.4H, V3.4H}, [X0].

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
Vt1The first destination vector register operand.
Vt2The second destination vector register operand.
Vt3The third destination vector register operand.
Vt4The fourth destination vector register operand.
XnThe stack-pointer or register to load into the destination vectors.
elszThe vector element size

◆ INSTR_CREATE_ld4_multi_2

#define INSTR_CREATE_ld4_multi_2 (   dc,
  Vt1,
  Vt2,
  Vt3,
  Vt4,
  Xn,
  Xnd,
  offset,
  elsz 
)    instr_create_5dst_4src(dc, OP_ld4, Vt1, Vt2, Vt3, Vt4, Xn, Xnd, Xn, offset, elsz)

Creates an Advanced SIMD (NEON) LD4 instruction to load multiple 4-element structures to four vector registers with post-index, e.g. LD4 {V0.4H, V1.4H, V2.4H, V3.4H}, [X0], X1.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
Vt1The first destination vector register operand.
Vt2The second destination vector register operand.
Vt3The third destination vector register operand.
Vt4The fourth destination vector register operand.
XnThe stack-pointer or GPR to load into the destination vectors
XndThe disposition of Xn
offsetThe post-index offset.
elszThe vector element size

◆ INSTR_CREATE_ld4r

#define INSTR_CREATE_ld4r (   dc,
  Vt1,
  Vt2,
  Vt3,
  Vt4,
  Xn,
  elsz 
)    instr_create_4dst_2src(dc, OP_ld4r, Vt1, Vt2, Vt3, Vt4, Xn, elsz)

Creates an Advanced SIMD (NEON) LD4R instruction to load and replicate a single 4-element structure to four vector registers, e.g. LD4R {V0.4H, V1.4H, V2.4H, V3.4H}, [X0].

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
Vt1The first destination vector register operand.
Vt2The second destination vector register operand.
Vt3The third destination vector register operand.
Vt4The fourth destination vector register operand.
XnThe stack-pointer or GPR to load into the destination vectors.
elszThe vector element size

◆ INSTR_CREATE_ld4r_2

#define INSTR_CREATE_ld4r_2 (   dc,
  Vt1,
  Vt2,
  Vt3,
  Vt4,
  Xn,
  Xnd,
  offset,
  elsz 
)    instr_create_5dst_4src(dc, OP_ld4r, Vt1, Vt2, Vt3, Vt4, Xn, Xnd, Xn, offset, elsz)

Creates an Advanced SIMD (NEON) LD4R instruction to load and replicate a single 4-element structure to four vector registers with post-indexing, e.g. LD4 {V0.4H, V1.4H, V2.4H, V3.4H}, [X0], X1.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
Vt1The first destination vector register operand.
Vt2The second destination vector register operand.
Vt3The third destination vector register operand.
Vt4The fourth destination vector register operand.
XnThe stack-pointer or register to load into the destination vectors.
XndThe disposition of Xn.
offsetThe post-index offset.
elszThe vector element size

◆ INSTR_CREATE_ldlar

#define INSTR_CREATE_ldlar (   dc,
  Rt,
  Rn 
)    instr_create_1dst_1src(dc, OP_ldlar, Rt, Rn)

Creates a LDLAR instruction.

This macro is used to encode the forms:

*    LDLAR   <Wt>, [<Xn|SP>]
*    LDLAR   <Xt>, [<Xn|SP>]
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RtThe first destination register. Can be W (Word, 32 bits) or X (Extended, 64 bits)
RnThe second source register. Can be X (Extended, 64 bits)

◆ INSTR_CREATE_ldlarb

#define INSTR_CREATE_ldlarb (   dc,
  Rt,
  Rn 
)    instr_create_1dst_1src(dc, OP_ldlarb, Rt, Rn)

Creates a LDLARB instruction.

This macro is used to encode the forms:

*    LDLARB  <Wt>, [<Xn|SP>]
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RtThe first destination register, W (Word, 32 bits)
RnThe second source register, X (Extended, 64 bits)

◆ INSTR_CREATE_ldlarh

#define INSTR_CREATE_ldlarh (   dc,
  Rt,
  Rn 
)    instr_create_1dst_1src(dc, OP_ldlarh, Rt, Rn)

Creates a LDLARH instruction.

This macro is used to encode the forms:

*    LDLARH  <Wt>, [<Xn|SP>]
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RtThe first destination register, W (Word, 32 bits)
RnThe second source register, X (Extended, 64 bits)

◆ INSTR_CREATE_ldpsw

#define INSTR_CREATE_ldpsw (   dc,
  Xt1,
  Xt2,
  Xn,
  Xr,
  imm 
)    instr_create_3dst_3src(dc, OP_ldpsw, Xt1, Xt2, Xn, Xr, Xn, imm)

Creates a LDPSW floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
Xt1The first GPR output register.
Xt2The second GPR output register.
XnThe input Stack-pointer or GPR register.
XrThe disposition of the input Stack-pointer or GPR register.
immThe immediate integer offset.

◆ INSTR_CREATE_ldpsw_2

#define INSTR_CREATE_ldpsw_2 (   dc,
  Xt1,
  Xt2,
  Xn 
)    instr_create_2dst_1src(dc, OP_ldpsw, Xt1, Xt2, Xn)

Creates a LDPSW floating point instruction.

Parameters
dcdc
Xt1The first GPR output register.
Xt2The second GPR output register.
XnThe disposition of the input register.

◆ INSTR_CREATE_ldr_imm

#define INSTR_CREATE_ldr_imm (   dc,
  Rt,
  Xn,
  Rn,
  imm 
)    instr_create_2dst_3src(dc, OP_ldr, Rt, Xn, Rn, Xn, imm)

Creates an LDR immediate instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RtThe output register.
XnThe input register or stack pointer
RnThe input memory disposition.
immImmediate int of the input register offset

◆ INSTR_CREATE_mla_vector

#define INSTR_CREATE_mla_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_4src(dc, OP_mla, Rd, Rd, Rm, Rn, width)

Creates a MLA vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register. The instruction also reads this register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_mls_vector

#define INSTR_CREATE_mls_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_4src(dc, OP_mls, Rd, Rd, Rm, Rn, width)

Creates a MLS vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register. The instruction also reads this register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_mul_vector

#define INSTR_CREATE_mul_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_mul, Rd, Rm, Rn, width)

Creates a MUL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_orn_vector

#define INSTR_CREATE_orn_vector (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_orn, Rd, Rm, Rn)

Creates a ORN vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_orr_sve_pred

#define INSTR_CREATE_orr_sve_pred (   dc,
  Zd,
  Pg,
  Zd_,
  Zm,
  width 
)    instr_create_1dst_4src(dc, OP_orr, Zd, Pg, Zd_, Zm, width)

Creates an ORR scalable vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe output SVE vector register.
PgPredicate register for predicated instruction, P0-P7.
Zd_The first input SVE vector register. Must match Zd.
ZmThe second input SVE vector register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_orr_vector

#define INSTR_CREATE_orr_vector (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_orr, Rd, Rm, Rn)

Creates a ORR vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_pmul_vector

#define INSTR_CREATE_pmul_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_pmul, Rd, Rm, Rn, width)

Creates a PMUL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use OPND_CREATE_BYTE().

◆ INSTR_CREATE_pmull2_vector

#define INSTR_CREATE_pmull2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_pmull2, Rd, Rm, Rn, width)

Creates a PMULL2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_pmull_vector

#define INSTR_CREATE_pmull_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_pmull, Rd, Rm, Rn, width)

Creates a PMULL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_psb_csync

#define INSTR_CREATE_psb_csync (   dc)    instr_create_0dst_0src(dc, OP_psb)

Creates a PSB instruction.

This macro is used to encode the forms:

*    PSB CSYNC
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.

◆ INSTR_CREATE_raddhn2_vector

#define INSTR_CREATE_raddhn2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_raddhn2, Rd, Rm, Rn, width)

Creates a RADDHN2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_raddhn_vector

#define INSTR_CREATE_raddhn_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_raddhn, Rd, Rm, Rn, width)

Creates a RADDHN vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_rax1

#define INSTR_CREATE_rax1 (   dc,
  Rd,
  Rn,
  Rm 
)    instr_create_1dst_3src(dc, OP_rax1, Rd, Rn, Rm, OPND_CREATE_DOUBLE())

Creates a RAX1 instruction.

This macro is used to encode the forms:

*    RAX1    <Dd>.2D, <Dn>.2D, <Dm>.2D
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register, Q (quadword, 128 bits)
RnThe second source vector register, Q (quadword, 128 bits)
RmThe third source vector register, Q (quadword, 128 bits)

◆ INSTR_CREATE_rsubhn2_vector

#define INSTR_CREATE_rsubhn2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_rsubhn2, Rd, Rm, Rn, width)

Creates a RSUBHN2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_rsubhn_vector

#define INSTR_CREATE_rsubhn_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_rsubhn, Rd, Rm, Rn, width)

Creates a RSUBHN vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_saba_vector

#define INSTR_CREATE_saba_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_saba, Rd, Rm, Rn, width)

Creates a SABA vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_sabal2_vector

#define INSTR_CREATE_sabal2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_sabal2, Rd, Rm, Rn, width)

Creates a SABAL2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_sabal_vector

#define INSTR_CREATE_sabal_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_sabal, Rd, Rm, Rn, width)

Creates a SABAL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_sabd_vector

#define INSTR_CREATE_sabd_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_sabd, Rd, Rm, Rn, width)

Creates a SABD vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_sabdl2_vector

#define INSTR_CREATE_sabdl2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_sabdl2, Rd, Rm, Rn, width)

Creates a SABDL2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_sabdl_vector

#define INSTR_CREATE_sabdl_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_sabdl, Rd, Rm, Rn, width)

Creates a SABDL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_saddl2_vector

#define INSTR_CREATE_saddl2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_saddl2, Rd, Rm, Rn, width)

Creates a SADDL2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_saddl_vector

#define INSTR_CREATE_saddl_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_saddl, Rd, Rm, Rn, width)

Creates a SADDL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_saddw2_vector

#define INSTR_CREATE_saddw2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_saddw2, Rd, Rm, Rn, width)

Creates a SADDW2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_saddw_vector

#define INSTR_CREATE_saddw_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_saddw, Rd, Rm, Rn, width)

Creates a SADDW vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_scvtf_scalar

#define INSTR_CREATE_scvtf_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_scvtf, Rd, Rm)

Creates an SCVTF floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point output register.
RmInteger input register.

◆ INSTR_CREATE_scvtf_scalar_fixed

#define INSTR_CREATE_scvtf_scalar_fixed (   dc,
  Rd,
  Rm,
  fbits 
)    instr_create_1dst_2src(dc, OP_scvtf, Rd, Rm, fbits)

Creates an SCVTF scalar floating-point to fixed-point convert instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point output register.
RmInteger input register.
fbitsThe number of bits after the binary point in the fixed-point input.

◆ INSTR_CREATE_scvtf_vector

#define INSTR_CREATE_scvtf_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_scvtf, Rd, Rm, width)

Creates an SCVTF vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
widthImmediate int of the vector element width. Must be OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE() or OPND_CREATE_HALF().

◆ INSTR_CREATE_scvtf_vector_fixed

#define INSTR_CREATE_scvtf_vector_fixed (   dc,
  Rd,
  Rm,
  width,
  fbits 
)    instr_create_1dst_3src(dc, OP_scvtf, Rd, Rm, width, fbits)

Creates an SCVTF vector floating-point to fixed-point convert instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe input register.
widthThe vector element width. Must be OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE() or OPND_CREATE_HALF().
fbitsThe number of bits after the binary point in the fixed-point destination element.

◆ INSTR_CREATE_sdot_vector

#define INSTR_CREATE_sdot_vector (   dc,
  Rd,
  Rn,
  Rm 
)    instr_create_1dst_4src(dc, OP_sdot, Rd, Rd, Rn, Rm, OPND_CREATE_BYTE())

Creates a SDOT instruction.

This macro is used to encode the forms:

*    SDOT    <Sd>.<Ts>, <Bn>.<Tb>, <Bm>.<Tb>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first source and destination vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits)

◆ INSTR_CREATE_sdot_vector_indexed

#define INSTR_CREATE_sdot_vector_indexed (   dc,
  Rd,
  Rn,
  Rm,
  index 
)    instr_create_1dst_5src(dc, OP_sdot, Rd, Rd, Rn, Rm, index, OPND_CREATE_BYTE())

Creates a SDOT instruction.

This macro is used to encode the forms:

*    SDOT    <Sd>.<Ts>, <Bn>.<Tb>, <Bm>.4B[<index>]
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first source and destination vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register, Q (quadword, 128 bits)
indexThe immediate index for Rm

◆ INSTR_CREATE_sha512h

#define INSTR_CREATE_sha512h (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_4src(dc, OP_sha512h, Rd, Rd, Rn, Rm, Rm_elsz)

Creates a SHA512H instruction.

This macro is used to encode the forms:

*    SHA512H <Qd>, <Qn>, <Dm>.2D
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first source and destination register, Q (quadword, 128 bits)
RnThe second source register, Q (quadword, 128 bits)
RmThe third source vector register, Q (quadword, 128 bits)
Rm_elszThe element size for Rm, OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_sha512h2

#define INSTR_CREATE_sha512h2 (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_4src(dc, OP_sha512h2, Rd, Rd, Rn, Rm, Rm_elsz)

Creates a SHA512H2 instruction.

This macro is used to encode the forms:

*    SHA512H2 <Qd>, <Qn>, <Dm>.2D
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first source and destination register, Q (quadword, 128 bits)
RnThe second source register, Q (quadword, 128 bits)
RmThe third source vector register, Q (quadword, 128 bits)
Rm_elszThe element size for Rm, OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_sha512su0

#define INSTR_CREATE_sha512su0 (   dc,
  Rd,
  Rn,
  Rn_elsz 
)    instr_create_1dst_3src(dc, OP_sha512su0, Rd, Rd, Rn, Rn_elsz)

Creates a SHA512SU0 instruction.

This macro is used to encode the forms:

*    SHA512SU0 <Dd>.2D, <Dn>.2D
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first source and destination vector register, Q (quadword, 128 bits)
RnThe second source vector register, Q (quadword, 128 bits)
Rn_elszThe element size for Rn, OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_sha512su1

#define INSTR_CREATE_sha512su1 (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_4src(dc, OP_sha512su1, Rd, Rd, Rn, Rm, Rm_elsz)

Creates a SHA512SU1 instruction.

This macro is used to encode the forms:

*    SHA512SU1 <Dd>.2D, <Dn>.2D, <Dm>.2D
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first source and destination vector register, Q (quadword, 128 bits)
RnThe second source vector register, Q (quadword, 128 bits)
RmThe third source vector register, Q (quadword, 128 bits)
Rm_elszThe element size for Rm, OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_shadd_vector

#define INSTR_CREATE_shadd_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_shadd, Rd, Rm, Rn, width)

Creates a SHADD vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_shsub_vector

#define INSTR_CREATE_shsub_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_shsub, Rd, Rm, Rn, width)

Creates a SHSUB vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_sli_vector

#define INSTR_CREATE_sli_vector (   dc,
  Rd,
  Rn,
  width,
  shift 
)    instr_create_1dst_3src(dc, OP_sli, Rd, Rn, width, shift)

Creates an SLI shift left and insert instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RnThe input register.
widthThe output vector element width. Use OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
shiftThe number of bits to shift the result by.

◆ INSTR_CREATE_sm3partw1_vector

#define INSTR_CREATE_sm3partw1_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_3src(dc, OP_sm3partw1, Rd, Rn, Rm, Rm_elsz)

Creates a SM3PARTW1 instruction.

This macro is used to encode the forms:

*    SM3PARTW1 <Sd>.4S, <Sn>.4S, <Sm>.4S
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register, Q (quadword, 128 bits)
RnThe second source vector register, Q (quadword, 128 bits)
RmThe third source vector register, Q (quadword, 128 bits)
Rm_elszThe element size for Rm, OPND_CREATE_SINGLE()

◆ INSTR_CREATE_sm3partw2_vector

#define INSTR_CREATE_sm3partw2_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_3src(dc, OP_sm3partw2, Rd, Rn, Rm, Rm_elsz)

Creates a SM3PARTW2 instruction.

This macro is used to encode the forms:

*    SM3PARTW2 <Sd>.4S, <Sn>.4S, <Sm>.4S
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register, Q (quadword, 128 bits)
RnThe second source vector register, Q (quadword, 128 bits)
RmThe third source vector register, Q (quadword, 128 bits)
Rm_elszThe element size for Rm, OPND_CREATE_SINGLE()

◆ INSTR_CREATE_sm3ss1_vector

#define INSTR_CREATE_sm3ss1_vector (   dc,
  Rd,
  Rn,
  Rm,
  Ra,
  Ra_elsz 
)    instr_create_1dst_4src(dc, OP_sm3ss1, Rd, Rn, Rm, Ra, Ra_elsz)

Creates a SM3SS1 instruction.

This macro is used to encode the forms:

*    SM3SS1  <Sd>.4S, <Sn>.4S, <Sm>.4S, <Sa>.4S
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register, Q (quadword, 128 bits)
RnThe second source vector register, Q (quadword, 128 bits)
RmThe third source vector register, Q (quadword, 128 bits)
RaThe fourth source vector register, Q (quadword, 128 bits)
Ra_elszThe element size for Ra, OPND_CREATE_SINGLE()

◆ INSTR_CREATE_sm3tt1a_vector_indexed

#define INSTR_CREATE_sm3tt1a_vector_indexed (   dc,
  Rd,
  Rn,
  Rm,
  imm2,
  Rm_elsz 
)    instr_create_1dst_4src(dc, OP_sm3tt1a, Rd, Rn, Rm, imm2, Rm_elsz)

Creates a SM3TT1A instruction.

This macro is used to encode the forms:

*    SM3TT1A <Sd>.4S, <Sn>.4S, <Sm>.S[<index>]
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register, Q (quadword, 128 bits)
RnThe second source vector register, Q (quadword, 128 bits)
RmThe third source vector register, Q (quadword, 128 bits)
imm2The immediate index for Rm
Rm_elszThe element size for Rm, OPND_CREATE_SINGLE()

◆ INSTR_CREATE_sm3tt1b_vector_indexed

#define INSTR_CREATE_sm3tt1b_vector_indexed (   dc,
  Rd,
  Rn,
  Rm,
  imm2,
  Rm_elsz 
)    instr_create_1dst_4src(dc, OP_sm3tt1b, Rd, Rn, Rm, imm2, Rm_elsz)

Creates a SM3TT1B instruction.

This macro is used to encode the forms:

*    SM3TT1B <Sd>.4S, <Sn>.4S, <Sm>.S[<index>]
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register, Q (quadword, 128 bits)
RnThe second source vector register, Q (quadword, 128 bits)
RmThe third source vector register, Q (quadword, 128 bits)
imm2The immediate index for Rm
Rm_elszThe element size for Rm, OPND_CREATE_SINGLE()

◆ INSTR_CREATE_sm3tt2a_vector_indexed

#define INSTR_CREATE_sm3tt2a_vector_indexed (   dc,
  Rd,
  Rn,
  Rm,
  imm2,
  Rm_elsz 
)    instr_create_1dst_4src(dc, OP_sm3tt2a, Rd, Rn, Rm, imm2, Rm_elsz)

Creates a SM3TT2A instruction.

This macro is used to encode the forms:

*    SM3TT2A <Sd>.4S, <Sn>.4S, <Sm>.S[<index>]
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register, Q (quadword, 128 bits)
RnThe second source vector register, Q (quadword, 128 bits)
RmThe third source vector register, Q (quadword, 128 bits)
imm2The immediate index for Rm
Rm_elszThe element size for Rm, OPND_CREATE_SINGLE()

◆ INSTR_CREATE_sm3tt2b_vector_indexed

#define INSTR_CREATE_sm3tt2b_vector_indexed (   dc,
  Rd,
  Rn,
  Rm,
  imm2,
  Rm_elsz 
)    instr_create_1dst_4src(dc, OP_sm3tt2b, Rd, Rn, Rm, imm2, Rm_elsz)

Creates a SM3TT2B instruction.

This macro is used to encode the forms:

*    SM3TT2B <Sd>.4S, <Sn>.4S, <Sm>.S[<index>]
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register, Q (quadword, 128 bits)
RnThe second source vector register, Q (quadword, 128 bits)
RmThe third source vector register, Q (quadword, 128 bits)
imm2The immediate index for Rm
Rm_elszThe element size for Rm, OPND_CREATE_SINGLE()

◆ INSTR_CREATE_sm4e_vector

#define INSTR_CREATE_sm4e_vector (   dc,
  Rd,
  Rn,
  Rn_elsz 
)    instr_create_1dst_2src(dc, OP_sm4e, Rd, Rn, Rn_elsz)

Creates a SM4E instruction.

This macro is used to encode the forms:

*    SM4E    <Sd>.4S, <Sn>.4S
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register, Q (quadword, 128 bits)
RnThe second source vector register, Q (quadword, 128 bits)
Rn_elszThe element size for Rn, OPND_CREATE_SINGLE()

◆ INSTR_CREATE_sm4ekey_vector

#define INSTR_CREATE_sm4ekey_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_3src(dc, OP_sm4ekey, Rd, Rn, Rm, Rm_elsz)

Creates a SM4EKEY instruction.

This macro is used to encode the forms:

*    SM4EKEY <Sd>.4S, <Sn>.4S, <Sm>.4S
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register, Q (quadword, 128 bits)
RnThe second source vector register, Q (quadword, 128 bits)
RmThe third source vector register, Q (quadword, 128 bits)
Rm_elszThe element size for Rm, OPND_CREATE_SINGLE()

◆ INSTR_CREATE_smax_vector

#define INSTR_CREATE_smax_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_smax, Rd, Rm, Rn, width)

Creates a SMAX vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_smaxp_vector

#define INSTR_CREATE_smaxp_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_smaxp, Rd, Rm, Rn, width)

Creates a SMAXP vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_smin_vector

#define INSTR_CREATE_smin_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_smin, Rd, Rm, Rn, width)

Creates a SMIN vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_sminp_vector

#define INSTR_CREATE_sminp_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_sminp, Rd, Rm, Rn, width)

Creates a SMINP vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_smlal2_vector

#define INSTR_CREATE_smlal2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_smlal2, Rd, Rm, Rn, width)

Creates a SMLAL2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_smlal_vector

#define INSTR_CREATE_smlal_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_smlal, Rd, Rm, Rn, width)

Creates a SMLAL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_smlsl2_vector

#define INSTR_CREATE_smlsl2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_smlsl2, Rd, Rm, Rn, width)

Creates a SMLSL2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_smlsl_vector

#define INSTR_CREATE_smlsl_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_smlsl, Rd, Rm, Rn, width)

Creates a SMLSL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_smull2_vector

#define INSTR_CREATE_smull2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_smull2, Rd, Rm, Rn, width)

Creates a SMULL2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_smull_vector

#define INSTR_CREATE_smull_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_smull, Rd, Rm, Rn, width)

Creates a SMULL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_sqadd_vector

#define INSTR_CREATE_sqadd_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_sqadd, Rd, Rm, Rn, width)

Creates a SQADD vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_sqdmlal2_vector

#define INSTR_CREATE_sqdmlal2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_sqdmlal2, Rd, Rm, Rn, width)

Creates a SQDMLAL2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_sqdmlal_vector

#define INSTR_CREATE_sqdmlal_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_sqdmlal, Rd, Rm, Rn, width)

Creates a SQDMLAL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_sqdmlsl2_vector

#define INSTR_CREATE_sqdmlsl2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_sqdmlsl2, Rd, Rm, Rn, width)

Creates a SQDMLSL2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_sqdmlsl_vector

#define INSTR_CREATE_sqdmlsl_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_sqdmlsl, Rd, Rm, Rn, width)

Creates a SQDMLSL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_sqdmulh_vector

#define INSTR_CREATE_sqdmulh_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_sqdmulh, Rd, Rm, Rn, width)

Creates a SQDMULH vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_sqdmull2_vector

#define INSTR_CREATE_sqdmull2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_sqdmull2, Rd, Rm, Rn, width)

Creates a SQDMULL2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_sqdmull_vector

#define INSTR_CREATE_sqdmull_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_sqdmull, Rd, Rm, Rn, width)

Creates a SQDMULL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_sqrdmlsh_scalar

#define INSTR_CREATE_sqrdmlsh_scalar (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_3src(dc, OP_sqrdmlsh, Rd, Rd, Rm, Rn)

Creates a SQRDMLSH scalar instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_sqrdmlsh_scalar_idx

#define INSTR_CREATE_sqrdmlsh_scalar_idx (   dc,
  Rd,
  Rm,
  Rn,
  index,
  elsz 
)    instr_create_1dst_5src(dc, OP_sqrdmlsh, Rd, Rd, Rm, Rn, index, elsz)

Creates a SQRDMLSH scalar indexed instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
indexThe first input register's vector element index.
elszThe vector element size. Use either OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_sqrdmlsh_vector

#define INSTR_CREATE_sqrdmlsh_vector (   dc,
  Rd,
  Rm,
  Rn,
  elsz 
)    instr_create_1dst_4src(dc, OP_sqrdmlsh, Rd, Rd, Rm, Rn, elsz)

Creates a SQRDMLSH vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
elszThe vector element size. Use either OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_sqrdmlsh_vector_idx

#define INSTR_CREATE_sqrdmlsh_vector_idx (   dc,
  Rd,
  Rm,
  Rn,
  index,
  elsz 
)    instr_create_1dst_5src(dc, OP_sqrdmlsh, Rd, Rd, Rm, Rn, index, elsz)

Creates a SQRDMLSH vector indexed instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
indexThe first input register's vector element index.
elszThe vector element size. Use either OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_sqrdmulh_vector

#define INSTR_CREATE_sqrdmulh_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_sqrdmulh, Rd, Rm, Rn, width)

Creates a SQRDMULH vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_sqrshl_vector

#define INSTR_CREATE_sqrshl_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_sqrshl, Rd, Rm, Rn, width)

Creates a SQRSHL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_sqshl_vector

#define INSTR_CREATE_sqshl_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_sqshl, Rd, Rm, Rn, width)

Creates a SQSHL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_sqsub_vector

#define INSTR_CREATE_sqsub_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_sqsub, Rd, Rm, Rn, width)

Creates a SQSUB vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_srhadd_vector

#define INSTR_CREATE_srhadd_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_srhadd, Rd, Rm, Rn, width)

Creates a SRHADD vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_srshl_vector

#define INSTR_CREATE_srshl_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_srshl, Rd, Rm, Rn, width)

Creates a SRSHL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_sshl_vector

#define INSTR_CREATE_sshl_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_sshl, Rd, Rm, Rn, width)

Creates a SSHL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_ssubl2_vector

#define INSTR_CREATE_ssubl2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_ssubl2, Rd, Rm, Rn, width)

Creates a SSUBL2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_ssubl_vector

#define INSTR_CREATE_ssubl_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_ssubl, Rd, Rm, Rn, width)

Creates a SSUBL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_ssubw2_vector

#define INSTR_CREATE_ssubw2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_ssubw2, Rd, Rm, Rn, width)

Creates a SSUBW2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_ssubw_vector

#define INSTR_CREATE_ssubw_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_ssubw, Rd, Rm, Rn, width)

Creates a SSUBW vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_st1_multi_1

#define INSTR_CREATE_st1_multi_1 (   dc,
  r,
  q,
 
)    instr_create_1dst_2src(dc, OP_st1, r, q, s)

Creates an Advanced SIMD (NEON) ST1 instruction to store multiple single element structures from one vector register, e.g. ST1 {V1.2S},[X1].

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
rThe destination memory operand.
qThe source vector register operand.
sThe size of the vector element.

◆ INSTR_CREATE_stllr

#define INSTR_CREATE_stllr (   dc,
  Rt,
  Rn 
)    instr_create_1dst_1src(dc, OP_stllr, Rt, Rn)

Creates a STLLR instruction.

This macro is used to encode the forms:

*    STLLR   <Wt>, [<Xn|SP>]
*    STLLR   <Xt>, [<Xn|SP>]
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RtThe first destination register. Can be W (Word, 32 bits) or X (Extended, 64 bits)
RnThe second source register. Can be X (Extended, 64 bits)

◆ INSTR_CREATE_stllrb

#define INSTR_CREATE_stllrb (   dc,
  Rt,
  Rn 
)    instr_create_1dst_1src(dc, OP_stllrb, Rt, Rn)

Creates a STLLRB instruction.

This macro is used to encode the forms:

*    STLLRB  <Wt>, [<Xn|SP>]
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RtThe first destination register, W (Word, 32 bits)
RnThe second source register, X (Extended, 64 bits)

◆ INSTR_CREATE_stllrh

#define INSTR_CREATE_stllrh (   dc,
  Rt,
  Rn 
)    instr_create_1dst_1src(dc, OP_stllrh, Rt, Rn)

Creates a STLLRH instruction.

This macro is used to encode the forms:

*    STLLRH  <Wt>, [<Xn|SP>]
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RtThe first destination register, W (Word, 32 bits)
RnThe second source register, X (Extended, 64 bits)

◆ INSTR_CREATE_str_imm

#define INSTR_CREATE_str_imm (   dc,
  Rt,
  Xt,
  Xn,
  imm 
)    instr_create_2dst_3src(dc, OP_str, Rt, Xn, Xt, Xn, imm)

Creates a STR immediate instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RtThe output memory disposition.
XtThe input register or stack pointer.
XnThe output register
immImmediate int of the output register offset

◆ INSTR_CREATE_sub_vector

#define INSTR_CREATE_sub_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_sub, Rd, Rm, Rn, width)

Creates a SUB vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_subhn2_vector

#define INSTR_CREATE_subhn2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_subhn2, Rd, Rm, Rn, width)

Creates a SUBHN2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_subhn_vector

#define INSTR_CREATE_subhn_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_subhn, Rd, Rm, Rn, width)

Creates a SUBHN vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_uaba_vector

#define INSTR_CREATE_uaba_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_uaba, Rd, Rm, Rn, width)

Creates a UABA vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_uabal2_vector

#define INSTR_CREATE_uabal2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_uabal2, Rd, Rm, Rn, width)

Creates a UABAL2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_uabal_vector

#define INSTR_CREATE_uabal_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_uabal, Rd, Rm, Rn, width)

Creates a UABAL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_uabd_vector

#define INSTR_CREATE_uabd_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_uabd, Rd, Rm, Rn, width)

Creates a UABD vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_uabdl2_vector

#define INSTR_CREATE_uabdl2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_uabdl2, Rd, Rm, Rn, width)

Creates a UABDL2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_uabdl_vector

#define INSTR_CREATE_uabdl_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_uabdl, Rd, Rm, Rn, width)

Creates a UABDL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_uaddl2_vector

#define INSTR_CREATE_uaddl2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_uaddl2, Rd, Rm, Rn, width)

Creates a UADDL2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_uaddl_vector

#define INSTR_CREATE_uaddl_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_uaddl, Rd, Rm, Rn, width)

Creates a UADDL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_uaddw2_vector

#define INSTR_CREATE_uaddw2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_uaddw2, Rd, Rm, Rn, width)

Creates a UADDW2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_uaddw_vector

#define INSTR_CREATE_uaddw_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_uaddw, Rd, Rm, Rn, width)

Creates a UADDW vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_ucvtf_scalar

#define INSTR_CREATE_ucvtf_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_ucvtf, Rd, Rm)

Creates a UCVTF floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point output register.
RmInteger input register.

◆ INSTR_CREATE_ucvtf_scalar_fixed

#define INSTR_CREATE_ucvtf_scalar_fixed (   dc,
  Rd,
  Rm,
  fbits 
)    instr_create_1dst_2src(dc, OP_ucvtf, Rd, Rm, fbits)

Creates a UCVTF scalar floating-point to fixed-point convert instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point output register.
RmInteger input register.
fbitsThe number of bits after the binary point in the fixed-point input.

◆ INSTR_CREATE_ucvtf_vector

#define INSTR_CREATE_ucvtf_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_ucvtf, Rd, Rm, width)

Creates a UCVTF vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
widthImmediate int of the vector element width. Must be OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE() or OPND_CREATE_HALF().

◆ INSTR_CREATE_ucvtf_vector_fixed

#define INSTR_CREATE_ucvtf_vector_fixed (   dc,
  Rd,
  Rm,
  width,
  fbits 
)    instr_create_1dst_3src(dc, OP_ucvtf, Rd, Rm, width, fbits)

Creates a UCVTF vector floating-point to fixed-point convert instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe input register.
widthThe vector element width. Must be OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE() or OPND_CREATE_HALF().
fbitsThe number of bits after the binary point in the fixed-point destination element.

◆ INSTR_CREATE_udot_vector

#define INSTR_CREATE_udot_vector (   dc,
  Rd,
  Rn,
  Rm 
)    instr_create_1dst_4src(dc, OP_udot, Rd, Rd, Rn, Rm, OPND_CREATE_BYTE())

Creates a UDOT instruction.

This macro is used to encode the forms:

*    UDOT    <Sd>.<Ts>, <Bn>.<Tb>, <Bm>.<Tb>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first source and destination vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits)

◆ INSTR_CREATE_udot_vector_indexed

#define INSTR_CREATE_udot_vector_indexed (   dc,
  Rd,
  Rn,
  Rm,
  index 
)    instr_create_1dst_5src(dc, OP_udot, Rd, Rd, Rn, Rm, index, OPND_CREATE_BYTE())

Creates a UDOT instruction.

This macro is used to encode the forms:

*    UDOT    <Sd>.<Ts>, <Bn>.<Tb>, <Bm>.4B[<index>]
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first source and destination vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register, Q (quadword, 128 bits)
indexThe immediate index for Rm

◆ INSTR_CREATE_uhadd_vector

#define INSTR_CREATE_uhadd_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_uhadd, Rd, Rm, Rn, width)

Creates a UHADD vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_uhsub_vector

#define INSTR_CREATE_uhsub_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_uhsub, Rd, Rm, Rn, width)

Creates a UHSUB vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_umax_vector

#define INSTR_CREATE_umax_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_umax, Rd, Rm, Rn, width)

Creates a UMAX vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_umaxp_vector

#define INSTR_CREATE_umaxp_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_umaxp, Rd, Rm, Rn, width)

Creates a UMAXP vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_umin_vector

#define INSTR_CREATE_umin_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_umin, Rd, Rm, Rn, width)

Creates a UMIN vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_uminp_vector

#define INSTR_CREATE_uminp_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_uminp, Rd, Rm, Rn, width)

Creates a UMINP vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_umlal2_vector

#define INSTR_CREATE_umlal2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_4src(dc, OP_umlal2, Rd, Rd, Rm, Rn, width)

Creates a UMLAL2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_umlal_vector

#define INSTR_CREATE_umlal_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_4src(dc, OP_umlal, Rd, Rd, Rm, Rn, width)

Creates a UMLAL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_umlsl2_vector

#define INSTR_CREATE_umlsl2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_4src(dc, OP_umlsl2, Rd, Rd, Rm, Rn, width)

Creates a UMLSL2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_umlsl_vector

#define INSTR_CREATE_umlsl_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_4src(dc, OP_umlsl, Rd, Rd, Rm, Rn, width)

Creates a UMLSL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_umull2_vector

#define INSTR_CREATE_umull2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_umull2, Rd, Rm, Rn, width)

Creates a UMULL2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_umull_vector

#define INSTR_CREATE_umull_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_umull, Rd, Rm, Rn, width)

Creates a UMULL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_uqadd_vector

#define INSTR_CREATE_uqadd_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_uqadd, Rd, Rm, Rn, width)

Creates a UQADD vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_uqrshl_vector

#define INSTR_CREATE_uqrshl_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_uqrshl, Rd, Rm, Rn, width)

Creates a UQRSHL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_uqshl_vector

#define INSTR_CREATE_uqshl_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_uqshl, Rd, Rm, Rn, width)

Creates a UQSHL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_uqshrn_vector

#define INSTR_CREATE_uqshrn_vector (   dc,
  Rd,
  Rn,
  width,
  shift 
)    instr_create_1dst_3src(dc, OP_uqshrn, Rd, Rn, width, shift)

Creates an UQSHRN vector unsigned saturating shift right narrow (immediate) instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RnThe input register.
widthThe output vector element width. Use OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
shiftThe number of bits to shift the result by.

◆ INSTR_CREATE_uqsub_vector

#define INSTR_CREATE_uqsub_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_uqsub, Rd, Rm, Rn, width)

Creates a UQSUB vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_urhadd_vector

#define INSTR_CREATE_urhadd_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_urhadd, Rd, Rm, Rn, width)

Creates a URHADD vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_urshl_vector

#define INSTR_CREATE_urshl_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_urshl, Rd, Rm, Rn, width)

Creates a URSHL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_ushl_vector

#define INSTR_CREATE_ushl_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_ushl, Rd, Rm, Rn, width)

Creates a USHL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_usubl2_vector

#define INSTR_CREATE_usubl2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_usubl2, Rd, Rm, Rn, width)

Creates a USUBL2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_usubl_vector

#define INSTR_CREATE_usubl_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_usubl, Rd, Rm, Rn, width)

Creates a USUBL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_usubw2_vector

#define INSTR_CREATE_usubw2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_usubw2, Rd, Rm, Rn, width)

Creates a USUBW2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_usubw_vector

#define INSTR_CREATE_usubw_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_usubw, Rd, Rm, Rn, width)

Creates a USUBW vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_xar

#define INSTR_CREATE_xar (   dc,
  Rd,
  Rn,
  Rm,
  imm6 
)    instr_create_1dst_4src(dc, OP_xar, Rd, Rn, Rm, imm6, OPND_CREATE_DOUBLE())

Creates a XAR instruction.

This macro is used to encode the forms:

*    XAR     <Dd>.2D, <Dn>.2D, <Dm>.2D, #<imm>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register, Q (quadword, 128 bits)
RnThe second source vector register, Q (quadword, 128 bits)
RmThe third source vector register, Q (quadword, 128 bits)
imm6The immediate imm

◆ INSTR_CREATE_xpaci

#define INSTR_CREATE_xpaci (   dc,
  Rd 
)    instr_create_0dst_1src((dc), OP_xpaci, (Rd))

Creates an XPACI instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdRegister with PAC bits to remove.

◆ OPND_CREATE_ABSMEM

#define OPND_CREATE_ABSMEM (   addr,
  size 
)    opnd_create_rel_addr(addr, size)

Create an absolute address operand encoded as pc-relative. Encoding will fail if addr is out of the maximum signed displacement reach for the architecture.

◆ OPND_CREATE_BYTE

#define OPND_CREATE_BYTE ( )    OPND_CREATE_INT8(VECTOR_ELEM_WIDTH_BYTE)

Operand denoting 8 bit vector element width for the other operands of the containing instruction.

◆ OPND_CREATE_DOUBLE

#define OPND_CREATE_DOUBLE ( )    OPND_CREATE_INT8(VECTOR_ELEM_WIDTH_DOUBLE)

Operand denoting 64 bit vector element width for the other operands of the containing instruction.

◆ OPND_CREATE_HALF

#define OPND_CREATE_HALF ( )    OPND_CREATE_INT8(VECTOR_ELEM_WIDTH_HALF)

Operand denoting 16 bit vector element width for the other operands of the containing instruction.

◆ OPND_CREATE_INT

#define OPND_CREATE_INT (   val)    OPND_CREATE_INTPTR(val)

Create an immediate integer operand. For AArch64 the size of an immediate is ignored when encoding, so there is no need to specify the final size.

◆ OPND_CREATE_LSL

#define OPND_CREATE_LSL ( )    opnd_add_flags(OPND_CREATE_INT(DR_SHIFT_LSL), DR_OPND_IS_SHIFT)

Create an operand specifying LSL, the default shift type when there is no shift.

◆ OPND_CREATE_SINGLE

#define OPND_CREATE_SINGLE ( )    OPND_CREATE_INT8(VECTOR_ELEM_WIDTH_SINGLE)

Operand denoting 32 bit vector element width for the other operands of the containing instruction.

◆ OPND_CREATE_ZR

#define OPND_CREATE_ZR (   reg)    opnd_create_reg(opnd_get_size(reg) == OPSZ_4 ? DR_REG_WZR : DR_REG_XZR)

Create a zero register operand of the same size as reg.

◆ VECTOR_ELEM_WIDTH_BYTE

#define VECTOR_ELEM_WIDTH_BYTE   0

Used in an additional immediate source operand to a vector operation, denotes 8 bit vector element width. See AArch64 IR Variations.

◆ VECTOR_ELEM_WIDTH_DOUBLE

#define VECTOR_ELEM_WIDTH_DOUBLE   3

Used in an additional immediate source operand to a vector operation, denotes 64 bit vector element width. See AArch64 IR Variations.

◆ VECTOR_ELEM_WIDTH_HALF

#define VECTOR_ELEM_WIDTH_HALF   1

Used in an additional immediate source operand to a vector operation, denotes 16 bit vector element width. See AArch64 IR Variations.

◆ VECTOR_ELEM_WIDTH_QUAD

#define VECTOR_ELEM_WIDTH_QUAD   4

Used in an additional immediate source operand to a vector operation, denotes full size 128 bit vector width. See AArch64 IR Variations.

◆ VECTOR_ELEM_WIDTH_SINGLE

#define VECTOR_ELEM_WIDTH_SINGLE   2

Used in an additional immediate source operand to a vector operation, denotes 32 bit vector element width. See AArch64 IR Variations.

◆ XINST_CREATE_add

#define XINST_CREATE_add (   dc,
  d,
 
)    INSTR_CREATE_add(dc, d, d, s)

This platform-independent macro creates an instr_t for an addition instruction that does not affect the status flags.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
dThe opnd_t explicit destination operand for the instruction.
sThe opnd_t explicit source operand for the instruction.

◆ XINST_CREATE_add_2src

#define XINST_CREATE_add_2src (   dc,
  d,
  s1,
  s2 
)    INSTR_CREATE_add(dc, d, s1, s2)

This platform-independent macro creates an instr_t for an addition instruction that does not affect the status flags and takes two sources plus a destination.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
dThe opnd_t explicit destination operand for the instruction.
s1The opnd_t explicit first source operand for the instruction. This must be a register.
s2The opnd_t explicit source operand for the instruction. This can be either a register or an immediate integer.

◆ XINST_CREATE_add_s

#define XINST_CREATE_add_s (   dc,
  d,
 
)    INSTR_CREATE_adds(dc, d, d, s)

This platform-independent macro creates an instr_t for an addition instruction that does affect the status flags.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
dThe opnd_t explicit destination operand for the instruction.
sThe opnd_t explicit source operand for the instruction.

◆ XINST_CREATE_add_sll

#define XINST_CREATE_add_sll (   dc,
  d,
  s1,
  s2_toshift,
  shift_amount 
)
Value:
INSTR_CREATE_add_shift((dc), (d), (s1), (s2_toshift), OPND_CREATE_LSL(), \
OPND_CREATE_INT8(shift_amount))

This platform-independent macro creates an instr_t for an addition instruction that does not affect the status flags and takes two register sources plus a destination, with one source being shifted logically left by an immediate amount that is limited to either 0, 1, 2, or 3.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
dThe opnd_t explicit destination operand for the instruction.
s1The opnd_t explicit first source operand for the instruction. This must be a register.
s2_toshiftThe opnd_t explicit source operand for the instruction. This must be a register.
shift_amountAn integer value that must be either 0, 1, 2, or 3.

◆ XINST_CREATE_and_s

#define XINST_CREATE_and_s (   dc,
  d,
 
)    INSTR_CREATE_ands(dc, d, d, s)

This platform-independent macro creates an instr_t for a bitwise and instruction that does affect the status flags.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
dThe opnd_t explicit destination operand for the instruction.
sThe opnd_t explicit source operand for the instruction.

◆ XINST_CREATE_call

#define XINST_CREATE_call (   dc,
 
)    INSTR_CREATE_bl(dc, t)

This platform-independent macro creates an instr_t for an unconditional branch instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
tThe opnd_t target operand for the instruction, which can be either a pc (opnd_create_pc)()) or an instr_t (opnd_create_instr()). Be sure to ensure that the limited reach of this short branch will reach the target (a pc operand is not suitable for most uses unless you know precisely where this instruction will be encoded).

◆ XINST_CREATE_call_reg

#define XINST_CREATE_call_reg (   dc,
 
)    INSTR_CREATE_blr(dc, r)

This platform-independent macro creates an instr_t for an indirect call instr through a register.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
rThe opnd_t explicit source operand for the instruction. This should be a reg_id_t operand with the address of the subroutine.

◆ XINST_CREATE_cmp

#define XINST_CREATE_cmp (   dc,
  s1,
  s2 
)    INSTR_CREATE_cmp(dc, s1, s2)

This platform-independent macro creates an instr_t for a comparison instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
s1The opnd_t explicit source operand for the instruction.
s2The opnd_t explicit source operand for the instruction.

◆ XINST_CREATE_debug_instr

#define XINST_CREATE_debug_instr (   dc)    INSTR_CREATE_brk((dc), OPND_CREATE_INT16(0))

This platform-independent macro creates an instr_t for a debug trap instruction, automatically supplying any implicit operands.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.

◆ XINST_CREATE_interrupt

#define XINST_CREATE_interrupt (   dc,
 
)    INSTR_CREATE_svc(dc, (i))

This platform-independent macro creates an instr_t for a software interrupt instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
iThe source integer constant opnd_t operand.

◆ XINST_CREATE_jump

#define XINST_CREATE_jump (   dc,
 
)    INSTR_CREATE_b((dc), (t))

This platform-independent macro creates an instr_t for an unconditional branch instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
tThe opnd_t target operand for the instruction, which can be either a pc (opnd_create_pc)()) or an instr_t (opnd_create_instr()). Be sure to ensure that the limited reach of this short branch will reach the target (a pc operand is not suitable for most uses unless you know precisely where this instruction will be encoded).

◆ XINST_CREATE_jump_cond

#define XINST_CREATE_jump_cond (   dc,
  pred,
 
)    (INSTR_PRED(INSTR_CREATE_bcond((dc), (t)), (pred)))

This platform-independent macro creates an instr_t for a conditional branch instruction that branches if the previously-set condition codes indicate the condition indicated by pred.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
predThe dr_pred_type_t condition to match.
tThe opnd_t target operand for the instruction, which can be either a pc (opnd_create_pc)()) or an instr_t (opnd_create_instr()). Be sure to ensure that the limited reach of this short branch will reach the target (a pc operand is not suitable for most uses unless you know precisely where this instruction will be encoded).

◆ XINST_CREATE_jump_reg

#define XINST_CREATE_jump_reg (   dc,
 
)    INSTR_CREATE_br((dc), (r))

This platform-independent macro creates an instr_t for an indirect jump instruction through a register.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
rThe register opnd holding the target.

◆ XINST_CREATE_jump_short

#define XINST_CREATE_jump_short (   dc,
 
)    INSTR_CREATE_b((dc), (t))

This platform-independent macro creates an instr_t for an unconditional branch instruction with the smallest available reach.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
tThe opnd_t target operand for the instruction, which can be either a pc (opnd_create_pc)()) or an instr_t (opnd_create_instr()). Be sure to ensure that the limited reach of this short branch will reach the target (a pc operand is not suitable for most uses unless you know precisely where this instruction will be encoded).

◆ XINST_CREATE_load

#define XINST_CREATE_load (   dc,
  r,
 
)
Value:
(opnd_get_disp(m) < 0 || \
opnd_get_disp(m) % opnd_size_in_bytes(opnd_get_size(m)) != 0)) \
? INSTR_CREATE_ldur( \
dc, \
m) \
dc, \
m))

This platform-independent macro creates an instr_t for a 4-byte or 8-byte memory load instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
rThe destination register opnd.
mThe source memory opnd.

◆ XINST_CREATE_load_1byte

#define XINST_CREATE_load_1byte (   dc,
  r,
 
)    INSTR_CREATE_ldrb(dc, r, m)

This platform-independent macro creates an instr_t for a 1-byte memory load instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
rThe destination register opnd.
mThe source memory opnd.

◆ XINST_CREATE_load_1byte_zext4

#define XINST_CREATE_load_1byte_zext4 (   dc,
  r,
 
)    INSTR_CREATE_ldrb(dc, r, m)

This platform-independent macro creates an instr_t which loads 1 byte from memory, zero-extends it to 4 bytes, and writes it to a 4 byte destination register.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
rThe destination register opnd.
mThe source memory opnd.

◆ XINST_CREATE_load_2bytes

#define XINST_CREATE_load_2bytes (   dc,
  r,
 
)    INSTR_CREATE_ldrh(dc, r, m)

This platform-independent macro creates an instr_t for a 2-byte memory load instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
rThe destination register opnd.
mThe source memory opnd.

◆ XINST_CREATE_load_int

#define XINST_CREATE_load_int (   dc,
  r,
 
)
Value:
? INSTR_CREATE_movn((dc), (r), OPND_CREATE_INT32(~opnd_get_immed_int(i)), \
: INSTR_CREATE_movz((dc), (r), (i), OPND_CREATE_INT(0)))

This platform-independent macro creates an instr_t for an immediate integer load instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
rThe destination register opnd.
iThe source immediate integer opnd.

◆ XINST_CREATE_load_pair

#define XINST_CREATE_load_pair (   dc,
  r1,
  r2,
 
)    INSTR_CREATE_ldp(dc, r1, r2, m)

This AArchXX-platform-independent macro creates an instr_t for a 2-register memory load instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
r1The first register opnd.
r2The second register opnd.
mThe source memory opnd.

◆ XINST_CREATE_load_simd

#define XINST_CREATE_load_simd (   dc,
  r,
 
)    INSTR_CREATE_ldr((dc), (r), (m))

This platform-independent macro creates an instr_t for a multimedia register load instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
rThe destination register opnd.
mThe source memory opnd.

◆ XINST_CREATE_move

#define XINST_CREATE_move (   dc,
  d,
 
)
Value:
opnd_get_reg(d) == DR_REG_WSP || opnd_get_reg(s) == DR_REG_WSP) \
OPND_CREATE_LSL(), OPND_CREATE_INT(0)) \
OPND_CREATE_LSL(), OPND_CREATE_INT(0)))

This platform-independent macro creates an instr_t for a register to register move instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
dThe destination register opnd.
sThe source register opnd.

◆ XINST_CREATE_nop

#define XINST_CREATE_nop (   dc)    INSTR_CREATE_nop(dc)

This platform-independent macro creates an instr_t for a nop instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.

◆ XINST_CREATE_return

#define XINST_CREATE_return (   dc)    INSTR_CREATE_ret(dc, opnd_create_reg(DR_REG_X30))

This platform-independent macro creates an instr_t for a return instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.

◆ XINST_CREATE_slr_s

#define XINST_CREATE_slr_s (   dc,
  d,
  rm_or_imm 
)
Value:
(opnd_is_reg(rm_or_imm) \
? instr_create_1dst_2src(dc, OP_lsrv, d, d, rm_or_imm) \
: instr_create_1dst_3src(dc, OP_ubfm, d, d, rm_or_imm, \

This platform-independent macro creates an instr_t for a logical right shift instruction that does affect the status flags.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
dThe opnd_t explicit destination operand for the instruction.
rm_or_immThe opnd_t explicit source operand for the instruction.

◆ XINST_CREATE_store

#define XINST_CREATE_store (   dc,
  m,
 
)
Value:
(opnd_get_disp(m) < 0 || \
opnd_get_disp(m) % opnd_size_in_bytes(opnd_get_size(m)) != 0)) \
? INSTR_CREATE_stur( \
dc, m, \
dc, m, \

This platform-independent macro creates an instr_t for a 4-byte or 8-byte memory store instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
mThe destination memory opnd.
rThe source register opnd.

◆ XINST_CREATE_store_1byte

#define XINST_CREATE_store_1byte (   dc,
  m,
 
)    INSTR_CREATE_strb(dc, m, opnd_create_reg(reg_resize_to_opsz(opnd_get_reg(r), OPSZ_4)))

This platform-independent macro creates an instr_t for a 1-byte memory store instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
mThe destination memory opnd.
rThe source register opnd.

◆ XINST_CREATE_store_2bytes

#define XINST_CREATE_store_2bytes (   dc,
  m,
 
)    INSTR_CREATE_strh(dc, m, opnd_create_reg(reg_resize_to_opsz(opnd_get_reg(r), OPSZ_4)))

This platform-independent macro creates an instr_t for a 2-byte memory store instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
mThe destination memory opnd.
rThe source register opnd.

◆ XINST_CREATE_store_pair

#define XINST_CREATE_store_pair (   dc,
  m,
  r1,
  r2 
)    INSTR_CREATE_stp(dc, m, r1, r2)

This AArchXX-platform-independent macro creates an instr_t for a 2-register memory store instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
mThe destination memory opnd.
r1The first register opnd.
r2The second register opnd.

◆ XINST_CREATE_store_simd

#define XINST_CREATE_store_simd (   dc,
  m,
 
)    INSTR_CREATE_str((dc), (m), (r))

This platform-independent macro creates an instr_t for a multimedia register store instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
mThe destination memory opnd.
rThe source register opnd.

◆ XINST_CREATE_sub

#define XINST_CREATE_sub (   dc,
  d,
 
)    INSTR_CREATE_sub(dc, d, d, s)

This platform-independent macro creates an instr_t for a subtraction instruction that does not affect the status flags.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
dThe opnd_t explicit destination operand for the instruction.
sThe opnd_t explicit source operand for the instruction.

◆ XINST_CREATE_sub_s

#define XINST_CREATE_sub_s (   dc,
  d,
 
)    INSTR_CREATE_subs(dc, d, d, s)

This platform-independent macro creates an instr_t for a subtraction instruction that does affect the status flags.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
dThe opnd_t explicit destination operand for the instruction.
sThe opnd_t explicit source operand for the instruction.
#define INSTR_CREATE_ldr(dc, Rd, mem)
Definition: dr_ir_macros_arm.h:1821
DR_API instr_t * instr_create_2dst_2src(void *drcontext, int opcode, opnd_t dst1, opnd_t dst2, opnd_t src1, opnd_t src2)
#define INSTR_CREATE_str(dc, mem, Rt)
Definition: dr_ir_macros_arm.h:1874
@ OPSZ_2b
Definition: dr_ir_opnd.h:169
DR_API opnd_size_t opnd_get_size(opnd_t opnd)
#define DR_REG_XSP
Definition: dr_ir_opnd.h:1308
DR_API instr_t * instr_create_1dst_4src(void *drcontext, int opcode, opnd_t dst, opnd_t src1, opnd_t src2, opnd_t src3, opnd_t src4)
DR_API bool opnd_is_base_disp(opnd_t opnd)
#define OPND_CREATE_INT8(val)
Definition: dr_ir_macros.h:136
#define OPND_CREATE_INT32(val)
Definition: dr_ir_macros.h:124
#define OPND_CREATE_DOUBLE()
Definition: dr_ir_macros_aarch64.h:90
#define OPND_CREATE_INT(val)
Definition: dr_ir_macros_aarch64.h:108
DR_API reg_id_t reg_resize_to_opsz(reg_id_t reg, opnd_size_t sz)
DR_API INSTR_INLINE opnd_t opnd_create_reg(reg_id_t r)
@ OP_ands
Definition: dr_ir_opcodes_arm.h:77
DR_API instr_t * instr_create_5dst_5src(void *drcontext, int opcode, opnd_t dst1, opnd_t dst2, opnd_t dst3, opnd_t dst4, opnd_t dst5, opnd_t src1, opnd_t src2, opnd_t src3, opnd_t src4, opnd_t src5)
DR_API instr_t * instr_create_1dst_2src(void *drcontext, int opcode, opnd_t dst, opnd_t src1, opnd_t src2)
DR_API uint opnd_size_in_bytes(opnd_size_t size)
DR_API bool opnd_is_reg(opnd_t opnd)
#define OPND_CREATE_ZR(reg)
Definition: dr_ir_macros_aarch64.h:111
DR_API ptr_int_t opnd_get_immed_int(opnd_t opnd)
@ OP_orr
Definition: dr_ir_opcodes_arm.h:188
DR_API int opnd_get_disp(opnd_t opnd)
@ OP_and
Definition: dr_ir_opcodes_arm.h:76
DR_API bool reg_is_32bit(reg_id_t reg)
@ OP_add
Definition: dr_ir_opcodes_arm.h:69
DR_API instr_t * instr_create_1dst_3src(void *drcontext, int opcode, opnd_t dst, opnd_t src1, opnd_t src2, opnd_t src3)
DR_API INSTR_INLINE bool opnd_is_immed(opnd_t opnd)
DR_API reg_id_t opnd_get_reg(opnd_t opnd)
#define OPND_CREATE_LSL()
Definition: dr_ir_macros_aarch64.h:115
DR_API opnd_t opnd_create_immed_int(ptr_int_t i, opnd_size_t data_size)