|
DynamoRIO
|
dr_ir_macros_aarch64.h File Reference
AArch64-specific instruction creation convenience macros. More...
Macros | |
| #define | VECTOR_ELEM_WIDTH_BYTE 0 |
| #define | VECTOR_ELEM_WIDTH_HALF 1 |
| #define | VECTOR_ELEM_WIDTH_SINGLE 2 |
| #define | VECTOR_ELEM_WIDTH_DOUBLE 3 |
| #define | VECTOR_ELEM_WIDTH_QUAD 4 |
| #define | OPND_CREATE_BYTE() OPND_CREATE_INT8(VECTOR_ELEM_WIDTH_BYTE) |
| #define | OPND_CREATE_HALF() OPND_CREATE_INT8(VECTOR_ELEM_WIDTH_HALF) |
| #define | OPND_CREATE_SINGLE() OPND_CREATE_INT8(VECTOR_ELEM_WIDTH_SINGLE) |
| #define | OPND_CREATE_DOUBLE() OPND_CREATE_INT8(VECTOR_ELEM_WIDTH_DOUBLE) |
| #define | OPND_CREATE_ABSMEM(addr, size) opnd_create_rel_addr(addr, size) |
| #define | OPND_CREATE_INT(val) OPND_CREATE_INTPTR(val) |
| #define | OPND_CREATE_ZR(reg) opnd_create_reg(opnd_get_size(reg) == OPSZ_4 ? DR_REG_WZR : DR_REG_XZR) |
| #define | OPND_CREATE_LSL() opnd_add_flags(OPND_CREATE_INT(DR_SHIFT_LSL), DR_OPND_IS_SHIFT) |
| #define | OPND_CREATE_LSR() opnd_add_flags(OPND_CREATE_INT(DR_SHIFT_LSR), DR_OPND_IS_SHIFT) |
| #define | OPND_CREATE_ASR() opnd_add_flags(OPND_CREATE_INT(DR_SHIFT_ASR), DR_OPND_IS_SHIFT) |
| #define | OPND_CREATE_ROR() opnd_add_flags(OPND_CREATE_INT(DR_SHIFT_ROR), DR_OPND_IS_SHIFT) |
| #define | OPND_CREATE_MUL() opnd_add_flags(OPND_CREATE_INT(DR_SHIFT_MUL), DR_OPND_IS_SHIFT) |
| #define | INSTR_CREATE_and(dc, rd, rn, rm_or_imm) |
| #define | INSTR_CREATE_orr(dc, rd, rn, rm_or_imm) |
| #define | INSTR_CREATE_ands(dc, rd, rn, rm_or_imm) |
| #define | INSTR_CREATE_bcond(dc, pc) instr_create_0dst_1src((dc), OP_bcond, (pc)) |
| #define | INSTR_CREATE_bl(dc, pc) instr_create_1dst_1src((dc), OP_bl, opnd_create_reg(DR_REG_X30), (pc)) |
| #define | INSTR_CREATE_ccmp(dc, Rn, Op, nzcv, cond) instr_create_0dst_4src(dc, OP_ccmp, Rn, Op, nzcv, cond) |
| #define | INSTR_CREATE_ccmn(dc, Rn, Op, nzcv, cond) instr_create_0dst_4src(dc, OP_ccmn, Rn, Op, nzcv, cond) |
| #define | INSTR_CREATE_fmov_general(dc, Rd, Rn) instr_create_1dst_1src(dc, OP_fmov, Rd, Rn) |
| #define | INSTR_CREATE_fmov_upper_vec(dc, Rd, Rn) |
| #define | INSTR_CREATE_shadd_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_shadd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sqadd_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sqadd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_srhadd_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_srhadd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_shsub_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_shsub, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sqsub_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sqsub, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_cmgt_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_cmgt, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_cmge_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_cmge, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sshl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sshl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sqshl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sqshl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_srshl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_srshl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sqrshl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sqrshl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_smax_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_smax, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_smin_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_smin, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sabd_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sabd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_saba_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_saba, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_add_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_add, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sve_add_vector(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_add, Rd, Rm, Rn) |
| #define | INSTR_CREATE_cmtst_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_cmtst, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_mla_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_4src(dc, OP_mla, Rd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_mul_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_mul, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_smaxp_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_smaxp, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sminp_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sminp, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sqdmulh_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sqdmulh, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_addp_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_addp, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_fmaxnm_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_fmaxnm, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_fmla_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_4src(dc, OP_fmla, Rd, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_fmla_vector_idx(dc, Rd, Rn, Rm, index, Rm_elsz) instr_create_1dst_5src(dc, OP_fmla, Rd, Rd, Rn, Rm, index, Rm_elsz) |
| #define | INSTR_CREATE_fadd_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_fadd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_fmulx_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_fmulx, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_fmulx_vector_idx(dc, Rd, Rn, Rm, index, Rm_elsz) instr_create_1dst_4src(dc, OP_fmulx, Rd, Rn, Rm, index, Rm_elsz) |
| #define | INSTR_CREATE_fmulx(dc, Rd, Rn, Rm) instr_create_1dst_2src(dc, OP_fmulx, Rd, Rn, Rm) |
| #define | INSTR_CREATE_fcmeq_vector_zero(dc, Rd, Rn, Rn_elsz) instr_create_1dst_3src(dc, OP_fcmeq, Rd, Rn, opnd_create_immed_float(0), Rn_elsz) |
| #define | INSTR_CREATE_fcmeq_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_fcmeq, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_fcmeq_zero(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_fcmeq, Rd, Rn, opnd_create_immed_float(0)) |
| #define | INSTR_CREATE_fcmeq(dc, Rd, Rn, Rm) instr_create_1dst_2src(dc, OP_fcmeq, Rd, Rn, Rm) |
| #define | INSTR_CREATE_fmlal_vector(dc, Rd, Rn, Rm) instr_create_1dst_4src(dc, OP_fmlal, Rd, Rd, Rn, Rm, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_fmlal_vector_idx(dc, Rd, Rn, Rm, index) instr_create_1dst_5src(dc, OP_fmlal, Rd, Rd, Rn, Rm, index, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_fmax_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_fmax, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_frecpe_vector(dc, Rd, Rn, Rn_elsz) instr_create_1dst_2src(dc, OP_frecpe, Rd, Rn, Rn_elsz) |
| #define | INSTR_CREATE_frecpe(dc, Rd, Rn) instr_create_1dst_1src(dc, OP_frecpe, Rd, Rn) |
| #define | INSTR_CREATE_frecps_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_frecps, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_frecps(dc, Rd, Rn, Rm) instr_create_1dst_2src(dc, OP_frecps, Rd, Rn, Rm) |
| #define | INSTR_CREATE_frsqrte_vector(dc, Rd, Rn, Rn_elsz) instr_create_1dst_2src(dc, OP_frsqrte, Rd, Rn, Rn_elsz) |
| #define | INSTR_CREATE_frsqrte(dc, Rd, Rn) instr_create_1dst_1src(dc, OP_frsqrte, Rd, Rn) |
| #define | INSTR_CREATE_and_vector(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_and, Rd, Rm, Rn) |
| #define | INSTR_CREATE_bic_vector(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_bic, Rd, Rm, Rn) |
| #define | INSTR_CREATE_fminnm_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_fminnm, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_fmls_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_4src(dc, OP_fmls, Rd, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_fmls_vector_idx(dc, Rd, Rn, Rm, index, Rm_elsz) instr_create_1dst_5src(dc, OP_fmls, Rd, Rd, Rn, Rm, index, Rm_elsz) |
| #define | INSTR_CREATE_fsub_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_fsub, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_fmlsl_vector(dc, Rd, Rm, Rn) instr_create_1dst_4src(dc, OP_fmlsl, Rd, Rd, Rm, Rn, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_fmlsl_vector_idx(dc, Rd, Rm, Rn, index) instr_create_1dst_5src(dc, OP_fmlsl, Rd, Rd, Rm, Rn, index, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_fmin_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_fmin, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_frsqrts_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_frsqrts, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_frsqrts(dc, Rd, Rn, Rm) instr_create_1dst_2src(dc, OP_frsqrts, Rd, Rn, Rm) |
| #define | INSTR_CREATE_orr_vector(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_orr, Rd, Rm, Rn) |
| #define | INSTR_CREATE_orn_vector(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_orn, Rd, Rm, Rn) |
| #define | INSTR_CREATE_uhadd_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uhadd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uqadd_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uqadd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_urhadd_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_urhadd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uhsub_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uhsub, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uqsub_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uqsub, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_cmhi_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_cmhi, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_cmhs_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_cmhs, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_ushl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_ushl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uqshl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uqshl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_urshl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_urshl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uqrshl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uqrshl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_umax_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_umax, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_umin_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_umin, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uabd_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uabd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uaba_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uaba, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sub_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sub, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_cmeq_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_cmeq, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_mls_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_4src(dc, OP_mls, Rd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_pmul_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_pmul, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_umaxp_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_umaxp, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uminp_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uminp, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sqrdmulh_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sqrdmulh, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sqrdmlsh_scalar(dc, Rd, Rm, Rn) instr_create_1dst_3src(dc, OP_sqrdmlsh, Rd, Rd, Rm, Rn) |
| #define | INSTR_CREATE_sqrdmlsh_scalar_idx(dc, Rd, Rm, Rn, index, elsz) instr_create_1dst_5src(dc, OP_sqrdmlsh, Rd, Rd, Rm, Rn, index, elsz) |
| #define | INSTR_CREATE_sqrdmlsh_vector(dc, Rd, Rm, Rn, elsz) instr_create_1dst_4src(dc, OP_sqrdmlsh, Rd, Rd, Rm, Rn, elsz) |
| #define | INSTR_CREATE_sqrdmlsh_vector_idx(dc, Rd, Rm, Rn, index, elsz) instr_create_1dst_5src(dc, OP_sqrdmlsh, Rd, Rd, Rm, Rn, index, elsz) |
| #define | INSTR_CREATE_fmlal2_vector(dc, Rd, Rn, Rm) instr_create_1dst_4src(dc, OP_fmlal2, Rd, Rd, Rn, Rm, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_fmlal2_vector_idx(dc, Rd, Rn, Rm, index) instr_create_1dst_5src(dc, OP_fmlal2, Rd, Rd, Rn, Rm, index, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_faddp_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_faddp, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_faddp_scalar(dc, Rd, Rn, Rn_elsz) instr_create_1dst_2src(dc, OP_faddp, Rd, Rn, Rn_elsz) |
| #define | INSTR_CREATE_fmul_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_fmul, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_fcmge_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_fcmge, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_fmaxnmp_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_fmaxnmp, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_fmaxnmp_scalar(dc, Rd, Rn, Rn_elsz) instr_create_1dst_2src(dc, OP_fmaxnmp, Rd, Rn, Rn_elsz) |
| #define | INSTR_CREATE_fmaxp_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_fmaxp, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_fmaxp_scalar(dc, Rd, Rn, Rn_elsz) instr_create_1dst_2src(dc, OP_fmaxp, Rd, Rn, Rn_elsz) |
| #define | INSTR_CREATE_facge_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_facge, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_facge(dc, Rd, Rn, Rm) instr_create_1dst_2src(dc, OP_facge, Rd, Rn, Rm) |
| #define | INSTR_CREATE_fcmle_vector_zero(dc, Rd, Rn, Rn_elsz) instr_create_1dst_3src(dc, OP_fcmle, Rd, Rn, opnd_create_immed_float(0.0), Rn_elsz) |
| #define | INSTR_CREATE_fcmle_zero(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_fcmle, Rd, Rn, opnd_create_immed_float(0.0)) |
| #define | INSTR_CREATE_fcmlt_vector_zero(dc, Rd, Rn, Rn_elsz) instr_create_1dst_3src(dc, OP_fcmlt, Rd, Rn, opnd_create_immed_float(0.0), Rn_elsz) |
| #define | INSTR_CREATE_fcmlt_zero(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_fcmlt, Rd, Rn, opnd_create_immed_float(0.0)) |
| #define | INSTR_CREATE_fdiv_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_fdiv, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_eor_vector(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_eor, Rd, Rm, Rn) |
| #define | INSTR_CREATE_bsl_vector(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_bsl, Rd, Rm, Rn) |
| #define | INSTR_CREATE_fminnmp_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_fminnmp, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_fminnmp_scalar(dc, Rd, Rn, Rn_elsz) instr_create_1dst_2src(dc, OP_fminnmp, Rd, Rn, Rn_elsz) |
| #define | INSTR_CREATE_fminnmv_vector(dc, Rd, Rn, Rn_elsz) instr_create_1dst_2src(dc, OP_fminnmv, Rd, Rn, Rn_elsz) |
| #define | INSTR_CREATE_fmlsl2_vector(dc, Rd, Rm, Rn) instr_create_1dst_4src(dc, OP_fmlsl2, Rd, Rd, Rm, Rn, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_fmlsl2_vector_idx(dc, Rd, Rm, Rn, index) instr_create_1dst_5src(dc, OP_fmlsl2, Rd, Rd, Rm, Rn, index, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_fabd_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_fabd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_facgt_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_facgt, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_facgt(dc, Rd, Rn, Rm) instr_create_1dst_2src(dc, OP_facgt, Rd, Rn, Rm) |
| #define | INSTR_CREATE_fcmgt_vector_zero(dc, Rd, Rn, Rn_elsz) instr_create_1dst_3src(dc, OP_fcmgt, Rd, Rn, opnd_create_immed_float(0.0), Rn_elsz) |
| #define | INSTR_CREATE_fcmgt_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_fcmgt, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_fcmgt_zero(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_fcmgt, Rd, Rn, opnd_create_immed_float(0.0)) |
| #define | INSTR_CREATE_fcmgt(dc, Rd, Rn, Rm) instr_create_1dst_2src(dc, OP_fcmgt, Rd, Rn, Rm) |
| #define | INSTR_CREATE_fminp_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_fminp, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_fminp_scalar(dc, Rd, Rn, Rn_elsz) instr_create_1dst_2src(dc, OP_fminp, Rd, Rn, Rn_elsz) |
| #define | INSTR_CREATE_bit_vector(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_bit, Rd, Rm, Rn) |
| #define | INSTR_CREATE_bif_vector(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_bif, Rd, Rm, Rn) |
| #define | INSTR_CREATE_fcvtas_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_fcvtas, Rd, Rm, width) |
| #define | INSTR_CREATE_fcvtau_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_fcvtau, Rd, Rm, width) |
| #define | INSTR_CREATE_fcvtms_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_fcvtms, Rd, Rm, width) |
| #define | INSTR_CREATE_fcvtmu_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_fcvtmu, Rd, Rm, width) |
| #define | INSTR_CREATE_fcvtns_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_fcvtns, Rd, Rm, width) |
| #define | INSTR_CREATE_fcvtnu_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_fcvtnu, Rd, Rm, width) |
| #define | INSTR_CREATE_fcvtps_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_fcvtps, Rd, Rm, width) |
| #define | INSTR_CREATE_fcvtpu_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_fcvtpu, Rd, Rm, width) |
| #define | INSTR_CREATE_fcvtzs_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_fcvtzs, Rd, Rm, width) |
| #define | INSTR_CREATE_fcvtzu_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_fcvtzu, Rd, Rm, width) |
| #define | INSTR_CREATE_fcvtzu_vector_fixed(dc, Rd, Rm, width, fbits) instr_create_1dst_3src(dc, OP_fcvtzu, Rd, Rm, width, fbits) |
| #define | INSTR_CREATE_sli_vector(dc, Rd, Rn, width, shift) instr_create_1dst_3src(dc, OP_sli, Rd, Rn, width, shift) |
| #define | INSTR_CREATE_uqshrn_vector(dc, Rd, Rn, width, shift) instr_create_1dst_3src(dc, OP_uqshrn, Rd, Rn, width, shift) |
| #define | INSTR_CREATE_ucvtf_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_ucvtf, Rd, Rm, width) |
| #define | INSTR_CREATE_ucvtf_vector_fixed(dc, Rd, Rm, width, fbits) instr_create_1dst_3src(dc, OP_ucvtf, Rd, Rm, width, fbits) |
| #define | INSTR_CREATE_scvtf_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_scvtf, Rd, Rm, width) |
| #define | INSTR_CREATE_scvtf_vector_fixed(dc, Rd, Rm, width, fbits) instr_create_1dst_3src(dc, OP_scvtf, Rd, Rm, width, fbits) |
| #define | INSTR_CREATE_sha512h(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_4src(dc, OP_sha512h, Rd, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_sha512h2(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_4src(dc, OP_sha512h2, Rd, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_sha512su0(dc, Rd, Rn, Rn_elsz) instr_create_1dst_3src(dc, OP_sha512su0, Rd, Rd, Rn, Rn_elsz) |
| #define | INSTR_CREATE_sha512su1(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_4src(dc, OP_sha512su1, Rd, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_rax1(dc, Rd, Rn, Rm) instr_create_1dst_3src(dc, OP_rax1, Rd, Rn, Rm, OPND_CREATE_DOUBLE()) |
| #define | INSTR_CREATE_xar(dc, Rd, Rn, Rm, imm6) instr_create_1dst_4src(dc, OP_xar, Rd, Rn, Rm, imm6, OPND_CREATE_DOUBLE()) |
| #define | INSTR_CREATE_ldr_imm(dc, Rt, Xn, Rn, imm) instr_create_2dst_3src(dc, OP_ldr, Rt, Xn, Rn, Xn, imm) |
| #define | INSTR_CREATE_str_imm(dc, Rt, Xt, Xn, imm) instr_create_2dst_3src(dc, OP_str, Rt, Xn, Xt, Xn, imm) |
| #define | INSTR_CREATE_fmov_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fmov, Rd, Rm) |
| #define | INSTR_CREATE_fabs_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fabs, Rd, Rm) |
| #define | INSTR_CREATE_fneg_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fneg, Rd, Rm) |
| #define | INSTR_CREATE_fsqrt_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fsqrt, Rd, Rm) |
| #define | INSTR_CREATE_fsqrt_vector(dc, Rd, Rn, Rn_elsz) instr_create_1dst_2src(dc, OP_fsqrt, Rd, Rn, Rn_elsz) |
| #define | INSTR_CREATE_fcvt_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fcvt, Rd, Rm) |
| #define | INSTR_CREATE_fcvtas_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fcvtas, Rd, Rm) |
| #define | INSTR_CREATE_fcvtau_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fcvtau, Rd, Rm) |
| #define | INSTR_CREATE_fcvtms_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fcvtms, Rd, Rm) |
| #define | INSTR_CREATE_fcvtmu_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fcvtmu, Rd, Rm) |
| #define | INSTR_CREATE_fcvtns_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fcvtns, Rd, Rm) |
| #define | INSTR_CREATE_fcvtnu_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fcvtnu, Rd, Rm) |
| #define | INSTR_CREATE_fcvtps_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fcvtps, Rd, Rm) |
| #define | INSTR_CREATE_fcvtpu_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fcvtpu, Rd, Rm) |
| #define | INSTR_CREATE_fcvtzs_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fcvtzs, Rd, Rm) |
| #define | INSTR_CREATE_fcvtzs_scalar_fixed(dc, Rd, Rm, fbits) instr_create_1dst_2src(dc, OP_fcvtzs, Rd, Rm, fbits) |
| #define | INSTR_CREATE_fcvtzu_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fcvtzu, Rd, Rm) |
| #define | INSTR_CREATE_fcvtzu_scalar_fixed(dc, Rd, Rm, fbits) instr_create_1dst_2src(dc, OP_fcvtzu, Rd, Rm, fbits) |
| #define | INSTR_CREATE_ucvtf_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_ucvtf, Rd, Rm) |
| #define | INSTR_CREATE_ucvtf_scalar_fixed(dc, Rd, Rm, fbits) instr_create_1dst_2src(dc, OP_ucvtf, Rd, Rm, fbits) |
| #define | INSTR_CREATE_scvtf_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_scvtf, Rd, Rm) |
| #define | INSTR_CREATE_scvtf_scalar_fixed(dc, Rd, Rm, fbits) instr_create_1dst_2src(dc, OP_scvtf, Rd, Rm, fbits) |
| #define | INSTR_CREATE_frintn_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_frintn, Rd, Rm) |
| #define | INSTR_CREATE_frintn_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_frintn, Rd, Rm, width) |
| #define | INSTR_CREATE_frintp_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_frintp, Rd, Rm) |
| #define | INSTR_CREATE_frintp_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_frintp, Rd, Rm, width) |
| #define | INSTR_CREATE_frintm_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_frintm, Rd, Rm) |
| #define | INSTR_CREATE_frintm_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_frintm, Rd, Rm, width) |
| #define | INSTR_CREATE_frintz_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_frintz, Rd, Rm) |
| #define | INSTR_CREATE_frintz_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_frintz, Rd, Rm, width) |
| #define | INSTR_CREATE_frinta_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_frinta, Rd, Rm) |
| #define | INSTR_CREATE_frinta_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_frinta, Rd, Rm, width) |
| #define | INSTR_CREATE_frintx_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_frintx, Rd, Rm) |
| #define | INSTR_CREATE_frintx_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_frintx, Rd, Rm, width) |
| #define | INSTR_CREATE_frinti_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_frinti, Rd, Rm) |
| #define | INSTR_CREATE_frinti_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_frinti, Rd, Rm, width) |
| #define | INSTR_CREATE_ldpsw(dc, Xt1, Xt2, Xn, Xr, imm) instr_create_3dst_3src(dc, OP_ldpsw, Xt1, Xt2, Xn, Xr, Xn, imm) |
| #define | INSTR_CREATE_ldpsw_2(dc, Xt1, Xt2, Xn) instr_create_2dst_1src(dc, OP_ldpsw, Xt1, Xt2, Xn) |
| #define | INSTR_CREATE_fmul_scalar(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_fmul, Rd, Rm, Rn) |
| #define | INSTR_CREATE_fdiv_scalar(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_fdiv, Rd, Rm, Rn) |
| #define | INSTR_CREATE_fadd_scalar(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_fadd, Rd, Rm, Rn) |
| #define | INSTR_CREATE_fsub_scalar(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_fsub, Rd, Rm, Rn) |
| #define | INSTR_CREATE_fmax_scalar(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_fmax, Rd, Rm, Rn) |
| #define | INSTR_CREATE_fmin_scalar(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_fmin, Rd, Rm, Rn) |
| #define | INSTR_CREATE_fmaxnm_scalar(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_fmaxnm, Rd, Rm, Rn) |
| #define | INSTR_CREATE_fminnm_scalar(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_fminnm, Rd, Rm, Rn) |
| #define | INSTR_CREATE_fnmul_scalar(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_fnmul, Rd, Rm, Rn) |
| #define | INSTR_CREATE_fmadd_scalar(dc, Rd, Rm, Rn, Ra) instr_create_1dst_3src(dc, OP_fmadd, Rd, Rm, Rn, Ra) |
| #define | INSTR_CREATE_fmsub_scalar(dc, Rd, Rm, Rn, Ra) instr_create_1dst_3src(dc, OP_fmsub, Rd, Rm, Rn, Ra) |
| #define | INSTR_CREATE_fnmadd_scalar(dc, Rd, Rm, Rn, Ra) instr_create_1dst_3src(dc, OP_fnmadd, Rd, Rm, Rn, Ra) |
| #define | INSTR_CREATE_fnmsub_scalar(dc, Rd, Rm, Rn, Ra) instr_create_1dst_3src(dc, OP_fnmsub, Rd, Rm, Rn, Ra) |
| #define | INSTR_CREATE_ld2_multi_2(dc, Vt1, Vt2, Xn, disp, offset, elsz) instr_create_3dst_4src(dc, OP_ld2, Vt1, Vt2, Xn, disp, Xn, offset, elsz) |
| #define | INSTR_CREATE_ld2(dc, Vt1, Vt2, Xn, index, elsz) instr_create_2dst_3src(dc, OP_ld2, Vt1, Vt2, Xn, index, elsz) |
| #define | INSTR_CREATE_ld2_2(dc, Vt1, Vt2, Xn, Xnd, index, offset, elsz) instr_create_3dst_5src(dc, OP_ld2, Vt1, Vt2, Xn, Xnd, index, Xn, offset, elsz) |
| #define | INSTR_CREATE_ld2r(dc, Vt1, Vt2, Xn, elsz) instr_create_2dst_2src(dc, OP_ld2r, Vt1, Vt2, Xn, elsz) |
| #define | INSTR_CREATE_ld2r_2(dc, Vt1, Vt2, Xn, Xnd, Xm, elsz) instr_create_3dst_4src(dc, OP_ld2r, Vt1, Vt2, Xn, Xnd, Xn, Xm, elsz) |
| #define | INSTR_CREATE_ld3_multi(dc, Vt1, Vt2, Vt3, Xn, elsz) instr_create_3dst_2src(dc, OP_ld3, Vt1, Vt2, Vt3, Xn, elsz) |
| #define | INSTR_CREATE_ld3_multi_2(dc, Vt1, Vt2, Vt3, Xn, Xnd, Xm, elsz) instr_create_4dst_4src(dc, OP_ld3, Vt1, Vt2, Vt3, Xn, Xnd, Xn, Xm, elsz) |
| #define | INSTR_CREATE_ld3(dc, Vt1, Vt2, Vt3, Xn, index, elsz) instr_create_3dst_3src(dc, OP_ld3, Vt1, Vt2, Vt3, Xn, index, elsz) |
| #define | INSTR_CREATE_ld3_2(dc, Vt1, Vt2, Vt3, Xn, Xnd, index, offset, elsz) instr_create_4dst_5src(dc, OP_ld3, Vt1, Vt2, Vt3, Xn, Xnd, index, Xn, offset, elsz) |
| #define | INSTR_CREATE_ld3r(dc, Vt1, Vt2, Vt3, Xn, elsz) instr_create_3dst_2src(dc, OP_ld3r, Vt1, Vt2, Vt3, Xn, elsz) |
| #define | INSTR_CREATE_ld3r_2(dc, Vt1, Vt2, Vt3, Xn, Xnd, offset, elsz) instr_create_4dst_4src(dc, OP_ld3r, Vt1, Vt2, Vt3, Xn, Xnd, Xn, offset, elsz) |
| #define | INSTR_CREATE_ld4_multi(dc, Vt1, Vt2, Vt3, Vt4, Xn, elsz) instr_create_4dst_2src(dc, OP_ld4, Vt1, Vt2, Vt3, Vt4, Xn, elsz) |
| #define | INSTR_CREATE_ld4_multi_2(dc, Vt1, Vt2, Vt3, Vt4, Xn, Xnd, offset, elsz) instr_create_5dst_4src(dc, OP_ld4, Vt1, Vt2, Vt3, Vt4, Xn, Xnd, Xn, offset, elsz) |
| #define | INSTR_CREATE_ld4(dc, Vt1, Vt2, Vt3, Vt4, Xn, index, elsz) instr_create_4dst_3src(dc, OP_ld4, Vt1, Vt2, Vt3, Vt4, Xn, index, elsz) |
| #define | INSTR_CREATE_ld4_2(dc, Vt1, Vt2, Vt3, Vt4, Xn, Xnd, index, offset, elsz) |
| #define | INSTR_CREATE_ld4r(dc, Vt1, Vt2, Vt3, Vt4, Xn, elsz) instr_create_4dst_2src(dc, OP_ld4r, Vt1, Vt2, Vt3, Vt4, Xn, elsz) |
| #define | INSTR_CREATE_ld4r_2(dc, Vt1, Vt2, Vt3, Vt4, Xn, Xnd, offset, elsz) instr_create_5dst_4src(dc, OP_ld4r, Vt1, Vt2, Vt3, Vt4, Xn, Xnd, Xn, offset, elsz) |
| #define | INSTR_CREATE_ld1_multi_1(dc, q, r, s) instr_create_1dst_2src(dc, OP_ld1, q, r, s) |
| #define | INSTR_CREATE_st1_multi_1(dc, r, q, s) instr_create_1dst_2src(dc, OP_st1, r, q, s) |
| #define | INSTR_CREATE_saddl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_saddl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_saddl2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_saddl2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_saddw_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_saddw, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_saddw2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_saddw2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_ssubl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_ssubl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_ssubl2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_ssubl2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_ssubw_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_ssubw, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_ssubw2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_ssubw2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_addhn_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_addhn, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_addhn2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_addhn2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sabal_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sabal, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sabal2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sabal2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_subhn_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_subhn, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_subhn2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_subhn2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sabdl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sabdl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sabdl2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sabdl2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_smlal_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_smlal, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_smlal2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_smlal2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sqdmlal_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sqdmlal, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sqdmlal2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sqdmlal2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_smlsl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_smlsl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_smlsl2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_smlsl2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sqdmlsl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sqdmlsl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sqdmlsl2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sqdmlsl2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_smull_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_smull, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_smull2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_smull2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sqdmull_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sqdmull, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sqdmull2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sqdmull2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_pmull_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_pmull, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_pmull2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_pmull2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uaddl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uaddl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uaddl2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uaddl2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uaddw_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uaddw, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uaddw2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uaddw2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_usubl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_usubl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_usubl2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_usubl2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_usubw_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_usubw, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_usubw2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_usubw2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_raddhn_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_raddhn, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_raddhn2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_raddhn2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uabal_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uabal, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uabal2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uabal2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_rsubhn_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_rsubhn, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_rsubhn2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_rsubhn2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uabdl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uabdl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uabdl2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uabdl2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_umlal_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_4src(dc, OP_umlal, Rd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_umlal2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_4src(dc, OP_umlal2, Rd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_umlsl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_4src(dc, OP_umlsl, Rd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_umlsl2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_4src(dc, OP_umlsl2, Rd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_umull_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_umull, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_umull2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_umull2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_fmov_vector_imm(dc, Rd, f, width) instr_create_1dst_2src(dc, OP_fmov, Rd, f, width) |
| #define | INSTR_CREATE_fmov_scalar_imm(dc, Rd, f) instr_create_1dst_1src(dc, OP_fmov, Rd, f) |
| #define | INSTR_CREATE_ldlar(dc, Rt, Rn) instr_create_1dst_1src(dc, OP_ldlar, Rt, Rn) |
| #define | INSTR_CREATE_ldlarb(dc, Rt, Rn) instr_create_1dst_1src(dc, OP_ldlarb, Rt, Rn) |
| #define | INSTR_CREATE_ldlarh(dc, Rt, Rn) instr_create_1dst_1src(dc, OP_ldlarh, Rt, Rn) |
| #define | INSTR_CREATE_stllr(dc, Rt, Rn) instr_create_1dst_1src(dc, OP_stllr, Rt, Rn) |
| #define | INSTR_CREATE_stllrb(dc, Rt, Rn) instr_create_1dst_1src(dc, OP_stllrb, Rt, Rn) |
| #define | INSTR_CREATE_stllrh(dc, Rt, Rn) instr_create_1dst_1src(dc, OP_stllrh, Rt, Rn) |
| #define | INSTR_CREATE_ldapr(dc, Rt, mem) instr_create_1dst_1src((dc), OP_ldapr, (Rt), (mem)) |
| #define | INSTR_CREATE_ldaprb(dc, Rt, mem) instr_create_1dst_1src((dc), OP_ldaprb, (Rt), (mem)) |
| #define | INSTR_CREATE_ldaprh(dc, Rt, mem) instr_create_1dst_1src((dc), OP_ldaprh, (Rt), (mem)) |
| #define | INSTR_CREATE_sm3partw1_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_sm3partw1, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_sm3partw2_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_sm3partw2, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_sm3ss1_vector(dc, Rd, Rn, Rm, Ra, Ra_elsz) instr_create_1dst_4src(dc, OP_sm3ss1, Rd, Rn, Rm, Ra, Ra_elsz) |
| #define | INSTR_CREATE_sm3tt1a_vector_indexed(dc, Rd, Rn, Rm, imm2, Rm_elsz) instr_create_1dst_4src(dc, OP_sm3tt1a, Rd, Rn, Rm, imm2, Rm_elsz) |
| #define | INSTR_CREATE_sm3tt1b_vector_indexed(dc, Rd, Rn, Rm, imm2, Rm_elsz) instr_create_1dst_4src(dc, OP_sm3tt1b, Rd, Rn, Rm, imm2, Rm_elsz) |
| #define | INSTR_CREATE_sm3tt2a_vector_indexed(dc, Rd, Rn, Rm, imm2, Rm_elsz) instr_create_1dst_4src(dc, OP_sm3tt2a, Rd, Rn, Rm, imm2, Rm_elsz) |
| #define | INSTR_CREATE_sm3tt2b_vector_indexed(dc, Rd, Rn, Rm, imm2, Rm_elsz) instr_create_1dst_4src(dc, OP_sm3tt2b, Rd, Rn, Rm, imm2, Rm_elsz) |
| #define | INSTR_CREATE_sm4e_vector(dc, Rd, Rn, Rn_elsz) instr_create_1dst_2src(dc, OP_sm4e, Rd, Rn, Rn_elsz) |
| #define | INSTR_CREATE_sm4ekey_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_sm4ekey, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_bcax(dc, Rd, Rn, Rm, Ra) instr_create_1dst_4src(dc, OP_bcax, Rd, Rn, Rm, Ra, OPND_CREATE_BYTE()) |
| #define | INSTR_CREATE_eor3(dc, Rd, Rn, Rm, Ra) instr_create_1dst_4src(dc, OP_eor3, Rd, Rn, Rm, Ra, OPND_CREATE_BYTE()) |
| #define | INSTR_CREATE_esb(dc) instr_create_0dst_0src(dc, OP_esb) |
| #define | INSTR_CREATE_psb_csync(dc) instr_create_0dst_0src(dc, OP_psb) |
| #define | INSTR_CREATE_fccmp(dc, Rn, Rm, nzcv, cond) instr_create_0dst_4src(dc, OP_fccmp, Rn, Rm, nzcv, cond) |
| #define | INSTR_CREATE_fccmpe(dc, Rn, Rm, nzcv, cond) instr_create_0dst_4src(dc, OP_fccmpe, Rn, Rm, nzcv, cond) |
| #define | INSTR_CREATE_fcsel(dc, Rd, Rn, Rm, cond) instr_create_1dst_3src(dc, OP_fcsel, Rd, Rn, Rm, cond) |
| #define | INSTR_CREATE_fcmp_zero(dc, Rn) instr_create_0dst_2src(dc, OP_fcmp, Rn, opnd_create_immed_float(0.0)) |
| #define | INSTR_CREATE_fcmp(dc, Rn, Rm) instr_create_0dst_2src(dc, OP_fcmp, Rn, Rm) |
| #define | INSTR_CREATE_fcmpe_zero(dc, Rn) instr_create_0dst_2src(dc, OP_fcmpe, Rn, opnd_create_immed_float(0.0)) |
| #define | INSTR_CREATE_fcmpe(dc, Rn, Rm) instr_create_0dst_2src(dc, OP_fcmpe, Rn, Rm) |
| #define | INSTR_CREATE_sdot_vector(dc, Rd, Rn, Rm) instr_create_1dst_4src(dc, OP_sdot, Rd, Rd, Rn, Rm, OPND_CREATE_BYTE()) |
| #define | INSTR_CREATE_sdot_vector_indexed(dc, Rd, Rn, Rm, index) instr_create_1dst_5src(dc, OP_sdot, Rd, Rd, Rn, Rm, index, OPND_CREATE_BYTE()) |
| #define | INSTR_CREATE_udot_vector(dc, Rd, Rn, Rm) instr_create_1dst_4src(dc, OP_udot, Rd, Rd, Rn, Rm, OPND_CREATE_BYTE()) |
| #define | INSTR_CREATE_udot_vector_indexed(dc, Rd, Rn, Rm, index) instr_create_1dst_5src(dc, OP_udot, Rd, Rd, Rn, Rm, index, OPND_CREATE_BYTE()) |
| #define | INSTR_CREATE_bfcvt(dc, Rd, Rn) instr_create_1dst_1src(dc, OP_bfcvt, Rd, Rn) |
| #define | INSTR_CREATE_bfcvtn2_vector(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_bfcvtn2, Rd, Rn, OPND_CREATE_SINGLE()) |
| #define | INSTR_CREATE_bfcvtn_vector(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_bfcvtn, Rd, Rn, OPND_CREATE_SINGLE()) |
| #define | INSTR_CREATE_bfdot_vector(dc, Rd, Rn, Rm) instr_create_1dst_4src(dc, OP_bfdot, Rd, Rd, Rn, Rm, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_bfdot_vector_idx(dc, Rd, Rn, Rm, index) instr_create_1dst_5src(dc, OP_bfdot, Rd, Rd, Rn, Rm, index, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_bfmlalb_vector(dc, Rd, Rn, Rm) instr_create_1dst_4src(dc, OP_bfmlalb, Rd, Rd, Rn, Rm, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_bfmlalb_vector_idx(dc, Rd, Rn, Rm, index) instr_create_1dst_5src(dc, OP_bfmlalb, Rd, Rd, Rn, Rm, index, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_bfmlalt_vector(dc, Rd, Rn, Rm) instr_create_1dst_4src(dc, OP_bfmlalt, Rd, Rd, Rn, Rm, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_bfmlalt_vector_idx(dc, Rd, Rn, Rm, index) instr_create_1dst_5src(dc, OP_bfmlalt, Rd, Rd, Rn, Rm, index, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_bfmmla_vector(dc, Rd, Rn, Rm) instr_create_1dst_4src(dc, OP_bfmmla, Rd, Rd, Rn, Rm, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_smmla_vector(dc, Rd, Rn, Rm) instr_create_1dst_4src(dc, OP_smmla, Rd, Rd, Rn, Rm, OPND_CREATE_BYTE()) |
| #define | INSTR_CREATE_sudot_vector_idx(dc, Rd, Rn, Rm, index) instr_create_1dst_5src(dc, OP_sudot, Rd, Rd, Rn, Rm, index, OPND_CREATE_BYTE()) |
| #define | INSTR_CREATE_ummla_vector(dc, Rd, Rn, Rm) instr_create_1dst_4src(dc, OP_ummla, Rd, Rd, Rn, Rm, OPND_CREATE_BYTE()) |
| #define | INSTR_CREATE_usmmla_vector(dc, Rd, Rn, Rm) instr_create_1dst_4src(dc, OP_usmmla, Rd, Rd, Rn, Rm, OPND_CREATE_BYTE()) |
| #define | INSTR_CREATE_usdot_vector(dc, Rd, Rn, Rm) instr_create_1dst_4src(dc, OP_usdot, Rd, Rd, Rn, Rm, OPND_CREATE_BYTE()) |
| #define | INSTR_CREATE_usdot_vector_idx(dc, Rd, Rn, Rm, index) instr_create_1dst_5src(dc, OP_usdot, Rd, Rd, Rn, Rm, index, OPND_CREATE_BYTE()) |
| #define | INSTR_CREATE_fcadd_vector(dc, Rd, Rn, Rm, rot, Rm_elsz) instr_create_1dst_5src(dc, OP_fcadd, Rd, Rd, Rn, Rm, rot, Rm_elsz) |
| #define | INSTR_CREATE_fcmla_vector(dc, Rd, Rn, Rm, rot, Rm_elsz) instr_create_1dst_5src(dc, OP_fcmla, Rd, Rd, Rn, Rm, rot, Rm_elsz) |
| #define | INSTR_CREATE_fcmla_vector_idx(dc, Rd, Rn, Rm, index, rot, Rm_elsz) instr_create_1dst_6src(dc, OP_fcmla, Rd, Rd, Rn, Rm, index, rot, Rm_elsz) |
| #define | INSTR_CREATE_orr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_orr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_eor_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_eor, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_and_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_and, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_bic_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_bic, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_movprfx_vector(dc, Zd, Zn) instr_create_1dst_1src(dc, OP_movprfx, Zd, Zn) |
| #define | INSTR_CREATE_movprfx_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_movprfx, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sqadd_sve_shift(dc, Zdn, imm, shift) instr_create_1dst_4src(dc, OP_sqadd, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift) |
| #define | INSTR_CREATE_sqadd_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_sqadd, Zd, Zn, Zm) |
| #define | INSTR_CREATE_sqsub_sve_shift(dc, Zdn, imm, shift) instr_create_1dst_4src(dc, OP_sqsub, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift) |
| #define | INSTR_CREATE_sqsub_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_sqsub, Zd, Zn, Zm) |
| #define | INSTR_CREATE_sub_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_sub, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sub_sve_shift(dc, Zdn, imm, shift) instr_create_1dst_4src(dc, OP_sub, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift) |
| #define | INSTR_CREATE_sub_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_sub, Zd, Zn, Zm) |
| #define | INSTR_CREATE_subr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_subr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_subr_sve_shift(dc, Zdn, imm, shift) instr_create_1dst_4src(dc, OP_subr, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift) |
| #define | INSTR_CREATE_uqadd_sve_shift(dc, Zdn, imm, shift) instr_create_1dst_4src(dc, OP_uqadd, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift) |
| #define | INSTR_CREATE_uqadd_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_uqadd, Zd, Zn, Zm) |
| #define | INSTR_CREATE_uqsub_sve_shift(dc, Zdn, imm, shift) instr_create_1dst_4src(dc, OP_uqsub, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift) |
| #define | INSTR_CREATE_uqsub_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_uqsub, Zd, Zn, Zm) |
| #define | INSTR_CREATE_add_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_add, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_add_sve_shift(dc, Zdn, imm, shift) instr_create_1dst_4src(dc, OP_add, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift) |
| #define | INSTR_CREATE_add_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_add, Zd, Zn, Zm) |
| #define | INSTR_CREATE_cpy_sve_shift_pred(dc, Zd, Pg, simm, shift) |
| #define | INSTR_CREATE_cpy_sve_pred(dc, Zd, Pg, Rn_or_Vn) INSTR_PRED(instr_create_1dst_2src(dc, OP_cpy, Zd, Pg, Rn_or_Vn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ptest_sve_pred(dc, Pg, Pn) INSTR_PRED(instr_create_0dst_2src(dc, OP_ptest, Pg, Pn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_mad_sve_pred(dc, Zdn, Pg, Zm, Za) INSTR_PRED(instr_create_1dst_4src(dc, OP_mad, Zdn, Zdn, Pg, Zm, Za), DR_PRED_MASKED) |
| #define | INSTR_CREATE_mla_sve_pred(dc, Zda, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_4src(dc, OP_mla, Zda, Zda, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_mls_sve_pred(dc, Zda, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_4src(dc, OP_mls, Zda, Zda, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_msb_sve_pred(dc, Zdn, Pg, Zm, Za) INSTR_PRED(instr_create_1dst_4src(dc, OP_msb, Zdn, Zdn, Pg, Zm, Za), DR_PRED_MASKED) |
| #define | INSTR_CREATE_mul_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_mul, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_mul_sve_imm(dc, Zdn, simm) instr_create_1dst_2src(dc, OP_mul, Zdn, Zdn, simm) |
| #define | INSTR_CREATE_smulh_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_smulh, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_umulh_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_umulh, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fexpa_sve(dc, Zd, Zn) instr_create_1dst_1src(dc, OP_fexpa, Zd, Zn) |
| #define | INSTR_CREATE_ftmad_sve(dc, Zdn, Zm, imm) instr_create_1dst_3src(dc, OP_ftmad, Zdn, Zdn, Zm, imm) |
| #define | INSTR_CREATE_ftsmul_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_ftsmul, Zd, Zn, Zm) |
| #define | INSTR_CREATE_ftssel_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_ftssel, Zd, Zn, Zm) |
| #define | INSTR_CREATE_abs_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_abs, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cnot_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_cnot, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_neg_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_neg, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sabd_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_sabd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_smax_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_smax, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_smax_sve(dc, Zdn, simm) instr_create_1dst_2src(dc, OP_smax, Zdn, Zdn, simm) |
| #define | INSTR_CREATE_smin_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_smin, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_smin_sve(dc, Zdn, simm) instr_create_1dst_2src(dc, OP_smin, Zdn, Zdn, simm) |
| #define | INSTR_CREATE_uabd_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_uabd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_facge_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_facge, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_facgt_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_facgt, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sdiv_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_sdiv, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sdivr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_sdivr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_udiv_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_udiv, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_udivr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_udivr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_umax_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_umax, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_umax_sve(dc, Zdn, imm) instr_create_1dst_2src(dc, OP_umax, Zdn, Zdn, imm) |
| #define | INSTR_CREATE_umin_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_umin, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_umin_sve(dc, Zdn, imm) instr_create_1dst_2src(dc, OP_umin, Zdn, Zdn, imm) |
| #define | INSTR_CREATE_sxtb_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_sxtb, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sxth_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_sxth, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sxtw_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_sxtw, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uxtb_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_uxtb, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uxth_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_uxth, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uxtw_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_uxtw, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcmeq_sve_zero_pred(dc, Pd, Pg, Zn) |
| #define | INSTR_CREATE_fcmeq_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmeq, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcmge_sve_zero_pred(dc, Pd, Pg, Zn) |
| #define | INSTR_CREATE_fcmge_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmge, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcmgt_sve_zero_pred(dc, Pd, Pg, Zn) |
| #define | INSTR_CREATE_fcmgt_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmgt, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcmle_sve_zero_pred(dc, Pd, Pg, Zn) |
| #define | INSTR_CREATE_fcmlt_sve_zero_pred(dc, Pd, Pg, Zn) |
| #define | INSTR_CREATE_fcmne_sve_zero_pred(dc, Pd, Pg, Zn) |
| #define | INSTR_CREATE_fcmne_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmne, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcmuo_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmuo, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcmle_sve_pred(dc, Pd, Pg, Zm, Zn) INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmle, Pd, Pg, Zm, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcmlt_sve_pred(dc, Pd, Pg, Zm, Zn) INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmlt, Pd, Pg, Zm, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmpeq_sve_pred_simm(dc, Pd, Pg, Zn, simm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpeq, Pd, Pg, Zn, simm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmpeq_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpeq, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmpge_sve_pred_simm(dc, Pd, Pg, Zn, simm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpge, Pd, Pg, Zn, simm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmpge_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpge, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmpgt_sve_pred_simm(dc, Pd, Pg, Zn, simm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpgt, Pd, Pg, Zn, simm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmpgt_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpgt, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmphi_sve_pred_imm(dc, Pd, Pg, Zn, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphi, Pd, Pg, Zn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmphi_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphi, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmphs_sve_pred_imm(dc, Pd, Pg, Zn, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphs, Pd, Pg, Zn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmphs_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphs, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmple_sve_pred_simm(dc, Pd, Pg, Zn, simm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmple, Pd, Pg, Zn, simm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmple_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmple, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmplo_sve_pred_imm(dc, Pd, Pg, Zn, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplo, Pd, Pg, Zn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmplo_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplo, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmpls_sve_pred_imm(dc, Pd, Pg, Zn, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpls, Pd, Pg, Zn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmpls_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpls, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmplt_sve_pred_simm(dc, Pd, Pg, Zn, simm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplt, Pd, Pg, Zn, simm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmplt_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplt, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmpne_sve_pred_simm(dc, Pd, Pg, Zn, simm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpne, Pd, Pg, Zn, simm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmpne_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpne, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_setffr_sve(dc) instr_create_0dst_0src(dc, OP_setffr) |
| #define | INSTR_CREATE_rdffr_sve(dc, Pd) instr_create_1dst_0src(dc, OP_rdffr, Pd) |
| #define | INSTR_CREATE_rdffr_sve_pred(dc, Pd, Pg) INSTR_PRED(instr_create_1dst_1src(dc, OP_rdffr, Pd, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_rdffrs_sve_pred(dc, Pd, Pg) INSTR_PRED(instr_create_1dst_1src(dc, OP_rdffrs, Pd, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_wrffr_sve(dc, Pn) instr_create_0dst_1src(dc, OP_wrffr, Pn) |
| #define | INSTR_CREATE_cntp_sve_pred(dc, Rd, Pg, Pn) INSTR_PRED(instr_create_1dst_2src(dc, OP_cntp, Rd, Pg, Pn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_decp_sve(dc, Rdn, Pm) instr_create_1dst_2src(dc, OP_decp, Rdn, Rdn, Pm) |
| #define | INSTR_CREATE_decp_sve_vector(dc, Zdn, Pm) instr_create_1dst_2src(dc, OP_decp, Zdn, Zdn, Pm) |
| #define | INSTR_CREATE_incp_sve(dc, Rdn, Pm) instr_create_1dst_2src(dc, OP_incp, Rdn, Rdn, Pm) |
| #define | INSTR_CREATE_incp_sve_vector(dc, Zdn, Pm) instr_create_1dst_2src(dc, OP_incp, Zdn, Zdn, Pm) |
| #define | INSTR_CREATE_sqdecp_sve(dc, Rdn, Pm) instr_create_1dst_2src(dc, OP_sqdecp, Rdn, Rdn, Pm) |
| #define | INSTR_CREATE_sqdecp_sve_wide(dc, Rdn, Pm) |
| #define | INSTR_CREATE_sqdecp_sve_vector(dc, Zdn, Pm) instr_create_1dst_2src(dc, OP_sqdecp, Zdn, Zdn, Pm) |
| #define | INSTR_CREATE_sqincp_sve(dc, Rdn, Pm) instr_create_1dst_2src(dc, OP_sqincp, Rdn, Rdn, Pm) |
| #define | INSTR_CREATE_sqincp_sve_wide(dc, Rdn, Pm) |
| #define | INSTR_CREATE_sqincp_sve_vector(dc, Zdn, Pm) instr_create_1dst_2src(dc, OP_sqincp, Zdn, Zdn, Pm) |
| #define | INSTR_CREATE_uqdecp_sve(dc, Rdn, Pm) instr_create_1dst_2src(dc, OP_uqdecp, Rdn, Rdn, Pm) |
| #define | INSTR_CREATE_uqdecp_sve_vector(dc, Zdn, Pm) instr_create_1dst_2src(dc, OP_uqdecp, Zdn, Zdn, Pm) |
| #define | INSTR_CREATE_uqincp_sve(dc, Rdn, Pm) instr_create_1dst_2src(dc, OP_uqincp, Rdn, Rdn, Pm) |
| #define | INSTR_CREATE_uqincp_sve_vector(dc, Zdn, Pm) instr_create_1dst_2src(dc, OP_uqincp, Zdn, Zdn, Pm) |
| #define | INSTR_CREATE_and_sve_imm(dc, Zdn, imm) instr_create_1dst_2src(dc, OP_and, Zdn, Zdn, imm) |
| #define | INSTR_CREATE_bic_sve_imm(dc, Zdn, imm) instr_create_1dst_2src(dc, OP_and, Zdn, Zdn, opnd_invert_immed_int(imm)) |
| #define | INSTR_CREATE_eor_sve_imm(dc, Zdn, imm) instr_create_1dst_2src(dc, OP_eor, Zdn, Zdn, imm) |
| #define | INSTR_CREATE_orr_sve_imm(dc, Zdn, imm) instr_create_1dst_2src(dc, OP_orr, Zdn, Zdn, imm) |
| #define | INSTR_CREATE_orn_sve_imm(dc, Zdn, imm) instr_create_1dst_2src(dc, OP_orr, Zdn, Zdn, opnd_invert_immed_int(imm)) |
| #define | INSTR_CREATE_and_sve_pred_b(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_and, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_and_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_and, Zd, Zn, Zm) |
| #define | INSTR_CREATE_ands_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_ands, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_bic_sve_pred_b(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_bic, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_bic_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_bic, Zd, Zn, Zm) |
| #define | INSTR_CREATE_bics_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_bics, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_eor_sve_pred_b(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_eor, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_not_sve_pred_b(dc, Pd, Pg, Pn) |
| #define | INSTR_CREATE_eor_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_eor, Zd, Zn, Zm) |
| #define | INSTR_CREATE_eors_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_eors, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_nand_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_nand, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_nands_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_nands, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_nor_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_nor, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_nors_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_nors, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_not_sve_pred_vec(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_not, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_orn_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_orn, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_orns_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_orns, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_orr_sve_pred_b(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_orr, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_orr_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_orr, Zd, Zn, Zm) |
| #define | INSTR_CREATE_orrs_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_orrs, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_clasta_sve_scalar(dc, Rdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_clasta, Rdn, Pg, Rdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_clasta_sve_simd_fp(dc, Vdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_clasta, Vdn, Pg, Vdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_clasta_sve_vector(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_clasta, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_clastb_sve_scalar(dc, Rdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_clastb, Rdn, Pg, Rdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_clastb_sve_simd_fp(dc, Vdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_clastb, Vdn, Pg, Vdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_clastb_sve_vector(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_clastb, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_lasta_sve_scalar(dc, Rd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_lasta, Rd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_lasta_sve_simd_fp(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_lasta, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_lastb_sve_scalar(dc, Rd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_lastb, Rd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_lastb_sve_simd_fp(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_lastb, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cnt_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_cnt, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cntb(dc, Rd, pattern, imm) instr_create_1dst_3src(dc, OP_cntb, Rd, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_cntd(dc, Rd, pattern, imm) instr_create_1dst_3src(dc, OP_cntd, Rd, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_cnth(dc, Rd, pattern, imm) instr_create_1dst_3src(dc, OP_cnth, Rd, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_cntw(dc, Rd, pattern, imm) instr_create_1dst_3src(dc, OP_cntw, Rd, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_decb(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_decb, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_decd(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_decd, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_decd_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_decd, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_dech(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_dech, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_dech_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_dech, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_decw(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_decw, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_decw_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_decw, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_incb(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_incb, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_incd(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_incd, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_incd_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_incd, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_inch(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_inch, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_inch_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_inch, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_incw(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_incw, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_incw_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_incw, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqdecb_wide(dc, Rdn, pattern, imm) |
| #define | INSTR_CREATE_sqdecb(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqdecb, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqdecd_wide(dc, Rdn, pattern, imm) |
| #define | INSTR_CREATE_sqdecd(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqdecd, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqdecd_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqdecd, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqdech_wide(dc, Rdn, pattern, imm) |
| #define | INSTR_CREATE_sqdech(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqdech, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqdech_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqdech, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqdecw_wide(dc, Rdn, pattern, imm) |
| #define | INSTR_CREATE_sqdecw(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqdecw, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqdecw_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqdecw, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqincb_wide(dc, Rdn, pattern, imm) |
| #define | INSTR_CREATE_sqincb(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqincb, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqincd_wide(dc, Rdn, pattern, imm) |
| #define | INSTR_CREATE_sqincd(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqincd, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqincd_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqincd, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqinch_wide(dc, Rdn, pattern, imm) |
| #define | INSTR_CREATE_sqinch(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqinch, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqinch_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqinch, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqincw_wide(dc, Rdn, pattern, imm) |
| #define | INSTR_CREATE_sqincw(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqincw, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqincw_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqincw, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqdecb(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqdecb, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqdecd(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqdecd, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqdecd_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqdecd, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqdech(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqdech, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqdech_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqdech, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqdecw(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqdecw, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqdecw_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqdecw, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqincb(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqincb, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqincd(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqincd, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqincd_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqincd, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqinch(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqinch, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqinch_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqinch, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqincw(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqincw, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqincw_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqincw, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_brka_sve_pred(dc, Pd, Pg, Pn) INSTR_PRED(instr_create_1dst_2src(dc, OP_brka, Pd, Pg, Pn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_brkas_sve_pred(dc, Pd, Pg, Pn) INSTR_PRED(instr_create_1dst_2src(dc, OP_brkas, Pd, Pg, Pn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_brkb_sve_pred(dc, Pd, Pg, Pn) INSTR_PRED(instr_create_1dst_2src(dc, OP_brkb, Pd, Pg, Pn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_brkbs_sve_pred(dc, Pd, Pg, Pn) INSTR_PRED(instr_create_1dst_2src(dc, OP_brkbs, Pd, Pg, Pn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_brkn_sve_pred(dc, Pdm, Pg, Pn) INSTR_PRED(instr_create_1dst_3src(dc, OP_brkn, Pdm, Pg, Pn, Pdm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_brkns_sve_pred(dc, Pdm, Pg, Pn) INSTR_PRED(instr_create_1dst_3src(dc, OP_brkns, Pdm, Pg, Pn, Pdm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_brkpa_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpa, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_brkpas_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpas, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_brkpb_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpb, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_brkpbs_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpbs, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_whilele_sve(dc, Pd, Rn, Rm) instr_create_1dst_2src(dc, OP_whilele, Pd, Rn, Rm) |
| #define | INSTR_CREATE_whilelo_sve(dc, Pd, Rn, Rm) instr_create_1dst_2src(dc, OP_whilelo, Pd, Rn, Rm) |
| #define | INSTR_CREATE_whilels_sve(dc, Pd, Rn, Rm) instr_create_1dst_2src(dc, OP_whilels, Pd, Rn, Rm) |
| #define | INSTR_CREATE_whilelt_sve(dc, Pd, Rn, Rm) instr_create_1dst_2src(dc, OP_whilelt, Pd, Rn, Rm) |
| #define | INSTR_CREATE_tbl_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_tbl, Zd, Zn, Zm) |
| #define | INSTR_CREATE_tbl_sve_mulvec(dc, Zd, Zn, Zm) instr_create_1dst_3src(dc, OP_tbl, Zd, Zn, opnd_create_increment_reg(Zn, 1), Zm) |
| #define | INSTR_CREATE_dup_sve_shift(dc, Zd, simm, shift) instr_create_1dst_3src(dc, OP_dup, Zd, simm, OPND_CREATE_LSL(), shift) |
| #define | INSTR_CREATE_dup_sve_idx(dc, Zd, Zn, index) instr_create_1dst_2src(dc, OP_dup, Zd, Zn, index) |
| #define | INSTR_CREATE_dup_sve_scalar(dc, Zd, Rn) instr_create_1dst_1src(dc, OP_dup, Zd, Rn) |
| #define | INSTR_CREATE_insr_sve_scalar(dc, Zd, Rm) instr_create_1dst_2src(dc, OP_insr, Zd, Zd, Rm) |
| #define | INSTR_CREATE_insr_sve_simd_fp(dc, Zdn, Vm) instr_create_1dst_2src(dc, OP_insr, Zdn, Zdn, Vm) |
| #define | INSTR_CREATE_ext_sve(dc, Zdn, Zm, imm) instr_create_1dst_3src(dc, OP_ext, Zdn, Zdn, Zm, imm) |
| #define | INSTR_CREATE_splice_sve_des(dc, Zdn, Pv, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_splice, Zdn, Pv, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_splice_sve_con(dc, Zd, Pv, Zn) |
| #define | INSTR_CREATE_rev_sve_pred(dc, Pd, Pn) instr_create_1dst_1src(dc, OP_rev, Pd, Pn) |
| #define | INSTR_CREATE_rev_sve(dc, Zd, Zn) instr_create_1dst_1src(dc, OP_rev, Zd, Zn) |
| #define | INSTR_CREATE_revb_sve(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_revb, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_revh_sve(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_revh, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_revw_sve(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_revw, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_compact_sve(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_compact, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_punpkhi_sve(dc, Pd, Pn) instr_create_1dst_1src(dc, OP_punpkhi, Pd, Pn) |
| #define | INSTR_CREATE_punpklo_sve(dc, Pd, Pn) instr_create_1dst_1src(dc, OP_punpklo, Pd, Pn) |
| #define | INSTR_CREATE_sunpkhi_sve(dc, Zd, Zn) instr_create_1dst_1src(dc, OP_sunpkhi, Zd, Zn) |
| #define | INSTR_CREATE_sunpklo_sve(dc, Zd, Zn) instr_create_1dst_1src(dc, OP_sunpklo, Zd, Zn) |
| #define | INSTR_CREATE_uunpkhi_sve(dc, Zd, Zn) instr_create_1dst_1src(dc, OP_uunpkhi, Zd, Zn) |
| #define | INSTR_CREATE_uunpklo_sve(dc, Zd, Zn) instr_create_1dst_1src(dc, OP_uunpklo, Zd, Zn) |
| #define | INSTR_CREATE_uzp1_sve_pred(dc, Pd, Pn, Pm) instr_create_1dst_2src(dc, OP_uzp1, Pd, Pn, Pm) |
| #define | INSTR_CREATE_uzp2_sve_pred(dc, Pd, Pn, Pm) instr_create_1dst_2src(dc, OP_uzp2, Pd, Pn, Pm) |
| #define | INSTR_CREATE_uzp2_sve_vector(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_uzp2, Zd, Zn, Zm) |
| #define | INSTR_CREATE_zip1_sve_pred(dc, Pd, Pn, Pm) instr_create_1dst_2src(dc, OP_zip1, Pd, Pn, Pm) |
| #define | INSTR_CREATE_zip1_sve_vector(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_zip1, Zd, Zn, Zm) |
| #define | INSTR_CREATE_zip2_sve_pred(dc, Pd, Pn, Pm) instr_create_1dst_2src(dc, OP_zip2, Pd, Pn, Pm) |
| #define | INSTR_CREATE_zip2_sve_vector(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_zip2, Zd, Zn, Zm) |
| #define | INSTR_CREATE_trn1_sve_pred(dc, Pd, Pn, Pm) instr_create_1dst_2src(dc, OP_trn1, Pd, Pn, Pm) |
| #define | INSTR_CREATE_trn1_sve_vector(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_trn1, Zd, Zn, Zm) |
| #define | INSTR_CREATE_trn2_sve_pred(dc, Pd, Pn, Pm) instr_create_1dst_2src(dc, OP_trn2, Pd, Pn, Pm) |
| #define | INSTR_CREATE_trn2_sve_vector(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_trn2, Zd, Zn, Zm) |
| #define | INSTR_CREATE_dupm_sve(dc, Zd, imm) instr_create_1dst_1src(dc, OP_dupm, Zd, imm) |
| #define | INSTR_CREATE_eon_sve_imm(dc, Zdn, imm) instr_create_1dst_2src(dc, OP_eor, Zdn, Zdn, opnd_invert_immed_int(imm)) |
| #define | INSTR_CREATE_pfalse_sve(dc, Pd) instr_create_1dst_0src(dc, OP_pfalse, Pd) |
| #define | INSTR_CREATE_pfirst_sve(dc, Pdn, Pg) INSTR_PRED(instr_create_1dst_2src(dc, OP_pfirst, Pdn, Pg, Pdn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sel_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_sel, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sel_sve_vector(dc, Zd, Pv, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_sel, Zd, Pv, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_mov_sve_pred(dc, Pd, Pn) |
| #define | INSTR_CREATE_movs_sve_pred(dc, Pd, Pg, Pn) INSTR_PRED(instr_create_1dst_3src(dc, OP_ands, Pd, Pg, Pn, Pn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ptrue_sve(dc, Pd, pattern) instr_create_1dst_1src(dc, OP_ptrue, Pd, pattern) |
| #define | INSTR_CREATE_ptrues_sve(dc, Pd, pattern) instr_create_1dst_1src(dc, OP_ptrues, Pd, pattern) |
| #define | INSTR_CREATE_asr_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_asr, Zd, Zn, imm) |
| #define | INSTR_CREATE_asr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_asr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_asr_sve_pred_wide(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_asr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_asr_sve_wide(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_asr, Zd, Zn, Zm) |
| #define | INSTR_CREATE_asrd_sve_pred(dc, Zdn, Pg, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_asrd, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_asrr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_asrr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cls_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_cls, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_clz_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_clz, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cnt_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_cnt, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_lsl_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_lsl, Zd, Zn, imm) |
| #define | INSTR_CREATE_lsl_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_lsl, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_lsl_sve_pred_wide(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_lsl, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_lsl_sve_wide(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_lsl, Zd, Zn, Zm) |
| #define | INSTR_CREATE_lslr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_lslr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_lsr_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_lsr, Zd, Zn, imm) |
| #define | INSTR_CREATE_lsr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_lsr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_lsr_sve_pred_wide(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_lsr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_lsr_sve_wide(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_lsr, Zd, Zn, Zm) |
| #define | INSTR_CREATE_lsrr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_lsrr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_rbit_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_rbit, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_andv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_andv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_eorv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_eorv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fadda_sve_pred(dc, Vdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fadda, Vdn, Pg, Vdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_faddv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_faddv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmaxnmv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_fmaxnmv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmaxv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_fmaxv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fminnmv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_fminnmv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fminv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_fminv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_orv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_orv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_saddv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_saddv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_smaxv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_smaxv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sminv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_sminv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uaddv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_uaddv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_umaxv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_umaxv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uminv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_uminv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fdup_sve(dc, Zd, imm) instr_create_1dst_1src(dc, OP_fdup, Zd, imm) |
| #define | INSTR_CREATE_ld1rb_sve(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rb, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1rh_sve(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rh, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1rw_sve(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rw, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1rd_sve(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rd, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1rsb_sve(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rsb, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1rsh_sve(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rsh, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1rsw_sve(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rsw, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_index_sve(dc, Zd, Rn_or_imm, Rm_or_imm) instr_create_1dst_2src(dc, OP_index, Zd, Rn_or_imm, Rm_or_imm) |
| #define | INSTR_CREATE_fcvt_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvt, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcvtzs_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvtzs, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcvtzu_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvtzu, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_frinta_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_frinta, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_frinti_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_frinti, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_frintm_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_frintm, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_frintn_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_frintn, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_frintp_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_frintp, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_frintx_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_frintx, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_frintz_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_frintz, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_scvtf_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_scvtf, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ucvtf_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ucvtf, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ctermeq(dc, Rn, Rm) instr_create_0dst_2src(dc, OP_ctermeq, Rn, Rm) |
| #define | INSTR_CREATE_ctermne(dc, Rn, Rm) instr_create_0dst_2src(dc, OP_ctermne, Rn, Rm) |
| #define | INSTR_CREATE_pnext_sve(dc, Pdn, Pv) INSTR_PRED(instr_create_1dst_2src(dc, OP_pnext, Pdn, Pv, Pdn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fabd_sve(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fabd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fabs_sve(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_fabs, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fdiv_sve(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fdiv, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fdivr_sve(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fdivr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmad_sve(dc, Zdn, Pg, Zm, Za) INSTR_PRED(instr_create_1dst_4src(dc, OP_fmad, Zdn, Zdn, Pg, Zm, Za), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmulx_sve(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fmulx, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fneg_sve(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_fneg, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fnmad_sve(dc, Zdn, Pg, Zm, Za) INSTR_PRED(instr_create_1dst_4src(dc, OP_fnmad, Zdn, Zdn, Pg, Zm, Za), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fnmla_sve(dc, Zda, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_4src(dc, OP_fnmla, Zda, Zda, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fnmls_sve(dc, Zda, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_4src(dc, OP_fnmls, Zda, Zda, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fnmsb_sve_pred(dc, Zdn, Pg, Zm, Za) INSTR_PRED(instr_create_1dst_4src(dc, OP_fnmsb, Zdn, Zdn, Pg, Zm, Za), DR_PRED_MASKED) |
| #define | INSTR_CREATE_frecpe_sve(dc, Zd, Zn) instr_create_1dst_1src(dc, OP_frecpe, Zd, Zn) |
| #define | INSTR_CREATE_frecps_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_frecps, Zd, Zn, Zm) |
| #define | INSTR_CREATE_frecpx_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_frecpx, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_frsqrte_sve(dc, Zd, Zn) instr_create_1dst_1src(dc, OP_frsqrte, Zd, Zn) |
| #define | INSTR_CREATE_frsqrts_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_frsqrts, Zd, Zn, Zm) |
| #define | INSTR_CREATE_fscale_sve(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fscale, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fsqrt_sve(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_fsqrt, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fadd_sve(dc, Zdn, Pg, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fadd, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fadd_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fadd_sve_vector(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_fadd, Zd, Zn, Zm) |
| #define | INSTR_CREATE_fsub_sve(dc, Zdn, Pg, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fsub, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fsub_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fsub, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fsub_sve_vector(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_fsub, Zd, Zn, Zm) |
| #define | INSTR_CREATE_fsubr_sve(dc, Zdn, Pg, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fsubr, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fsubr_sve_vector(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fsubr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmax_sve(dc, Zdn, Pg, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fmax, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmax_sve_vector(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fmax, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmaxnm_sve(dc, Zdn, Pg, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fmaxnm, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmaxnm_sve_vector(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fmaxnm, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmin_sve(dc, Zdn, Pg, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fmin, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmin_sve_vector(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fmin, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fminnm_sve(dc, Zdn, Pg, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fminnm, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fminnm_sve_vector(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fminnm, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmla_sve_vector(dc, Zda, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_4src(dc, OP_fmla, Zda, Zda, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmla_sve_idx(dc, Zda, Zn, Zm, index) instr_create_1dst_4src(dc, OP_fmla, Zda, Zda, Zn, Zm, index) |
| #define | INSTR_CREATE_fmls_sve_vector(dc, Zda, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_4src(dc, OP_fmls, Zda, Zda, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmls_sve_idx(dc, Zda, Zn, Zm, index) instr_create_1dst_4src(dc, OP_fmls, Zda, Zda, Zn, Zm, index) |
| #define | INSTR_CREATE_fmsb_sve(dc, Zdn, Pg, Zm, Za) INSTR_PRED(instr_create_1dst_4src(dc, OP_fmsb, Zdn, Zdn, Pg, Zm, Za), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmul_sve(dc, Zdn, Pg, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fmul, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmul_sve_pred_vector(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fmul, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmul_sve_vector(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_fmul, Zd, Zn, Zm) |
| #define | INSTR_CREATE_fmul_sve_idx(dc, Zd, Zn, Zm, index) instr_create_1dst_3src(dc, OP_fmul, Zd, Zn, Zm, index) |
| #define | INSTR_CREATE_addpl(dc, Rd, Rn, simm) instr_create_1dst_2src(dc, OP_addpl, Rd, Rn, simm) |
| #define | INSTR_CREATE_addvl(dc, Rd, Rn, simm) instr_create_1dst_2src(dc, OP_addvl, Rd, Rn, simm) |
| #define | INSTR_CREATE_rdvl(dc, Rd, simm) instr_create_1dst_1src(dc, OP_rdvl, Rd, simm) |
| #define | INSTR_CREATE_ldff1b_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1b, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldff1d_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1d, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldff1h_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1h, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldff1sb_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1sb, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldff1sh_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1sh, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldff1sw_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1sw, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldff1w_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1w, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcadd_sve_pred(dc, Zdn, Pg, Zm, rot) |
| #define | INSTR_CREATE_fcmla_sve_vector(dc, Zda, Pg, Zn, Zm, rot) |
| #define | INSTR_CREATE_fcmla_sve_idx(dc, Zda, Zn, Zm, imm, rot) instr_create_1dst_5src(dc, OP_fcmla, Zda, Zda, Zn, Zm, imm, rot) |
| #define | INSTR_CREATE_ld1b_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1b, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1rob_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rob, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1rqb_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rqb, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1rqh_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rqh, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1rqw_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rqw, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1rqd_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rqd, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1sb_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1sb, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldnt1b_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1b, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_st1b_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_st1b, Rn, Zt, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_stnt1b_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_stnt1b, Rn, Zt, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_bfcvt_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_bfcvt, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_bfdot_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_bfdot, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_bfdot_sve_idx(dc, Zda, Zn, Zm, index) instr_create_1dst_4src(dc, OP_bfdot, Zda, Zda, Zn, Zm, index) |
| #define | INSTR_CREATE_bfmlalb_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_bfmlalb, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_bfmlalb_sve_idx(dc, Zda, Zn, Zm, index) instr_create_1dst_4src(dc, OP_bfmlalb, Zda, Zda, Zn, Zm, index) |
| #define | INSTR_CREATE_bfmlalt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_bfmlalt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_bfmlalt_sve_idx(dc, Zda, Zn, Zm, index) instr_create_1dst_4src(dc, OP_bfmlalt, Zda, Zda, Zn, Zm, index) |
| #define | INSTR_CREATE_bfmmla_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_bfmmla, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_smmla_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_smmla, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sudot_sve_idx(dc, Zda, Zn, Zm, index) instr_create_1dst_4src(dc, OP_sudot, Zda, Zda, Zn, Zm, index) |
| #define | INSTR_CREATE_ummla_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_ummla, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_usdot_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_usdot, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_usdot_sve_idx(dc, Zda, Zn, Zm, index) instr_create_1dst_4src(dc, OP_usdot, Zda, Zda, Zn, Zm, index) |
| #define | INSTR_CREATE_usmmla_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_usmmla, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_prfb_sve_pred(dc, prfop, Pg, Rn) INSTR_PRED(instr_create_0dst_3src(dc, OP_prfb, prfop, Pg, Rn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_prfd_sve_pred(dc, prfop, Pg, Rn) INSTR_PRED(instr_create_0dst_3src(dc, OP_prfd, prfop, Pg, Rn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_prfh_sve_pred(dc, prfop, Pg, Rn) INSTR_PRED(instr_create_0dst_3src(dc, OP_prfh, prfop, Pg, Rn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_prfw_sve_pred(dc, prfop, Pg, Rn) INSTR_PRED(instr_create_0dst_3src(dc, OP_prfw, prfop, Pg, Rn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_adr_sve(dc, Zd, Zn) instr_create_1dst_1src(dc, OP_adr, Zd, Zn) |
| #define | INSTR_CREATE_ld2b_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_ld3b_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_ld4b_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_st2b_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_st3b_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_st4b_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_ld1h_sve_pred(dc, Zt, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1h, Zt, Zn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1sh_sve_pred(dc, Zt, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1sh, Zt, Zn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1w_sve_pred(dc, Zt, Pg, Zn) |
| #define | INSTR_CREATE_ld1d_sve_pred(dc, Zt, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1d, Zt, Zn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1sw_sve_pred(dc, Zt, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1sw, Zt, Zn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_st1h_sve_pred(dc, Zt, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_st1h, Zn, Zt, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_st1w_sve_pred(dc, Zt, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_st1w, Zn, Zt, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_st1d_sve_pred(dc, Zt, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_st1d, Zn, Zt, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld2d_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_ld2h_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_ld2w_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_ld3d_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_ld3h_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_ld3w_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_ld4d_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_ld4h_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_ld4w_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_ldnt1d_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1d, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldnt1h_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1h, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldnt1w_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1w, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_st2d_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_st2h_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_st2w_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_st3d_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_st3h_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_st3w_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_st4d_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_st4h_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_st4w_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_stnt1d_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_stnt1d, Rn, Zt, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_stnt1h_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_stnt1h, Rn, Zt, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_stnt1w_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_stnt1w, Rn, Zt, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldnf1b_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1b, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldnf1d_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1d, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldnf1h_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1h, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldnf1sb_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1sb, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldnf1sh_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1sh, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldnf1sw_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1sw, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldnf1w_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1w, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldapur(dc, Rt, mem) instr_create_1dst_1src(dc, OP_ldapur, Rt, mem) |
| #define | INSTR_CREATE_ldapurb(dc, Rt, mem) instr_create_1dst_1src(dc, OP_ldapurb, Rt, mem) |
| #define | INSTR_CREATE_ldapursb(dc, Rt, mem) instr_create_1dst_1src(dc, OP_ldapursb, Rt, mem) |
| #define | INSTR_CREATE_ldapurh(dc, Rt, mem) instr_create_1dst_1src(dc, OP_ldapurh, Rt, mem) |
| #define | INSTR_CREATE_ldapursh(dc, Rt, mem) instr_create_1dst_1src(dc, OP_ldapursh, Rt, mem) |
| #define | INSTR_CREATE_ldapursw(dc, Rt, mem) instr_create_1dst_1src(dc, OP_ldapursw, Rt, mem) |
| #define | INSTR_CREATE_stlur(dc, Rt, mem) instr_create_1dst_1src(dc, OP_stlur, mem, Rt) |
| #define | INSTR_CREATE_stlurb(dc, Rt, mem) instr_create_1dst_1src(dc, OP_stlurb, mem, Rt) |
| #define | INSTR_CREATE_stlurh(dc, Rt, mem) instr_create_1dst_1src(dc, OP_stlurh, mem, Rt) |
| #define | INSTR_CREATE_cfinv(dc) instr_create_0dst_0src(dc, OP_cfinv) |
| #define | INSTR_CREATE_rmif(dc, Rn, shift, mask) instr_create_0dst_3src(dc, OP_rmif, Rn, shift, mask) |
| #define | INSTR_CREATE_setf16(dc, Rn) instr_create_0dst_1src(dc, OP_setf16, Rn) |
| #define | INSTR_CREATE_setf8(dc, Rn) instr_create_0dst_1src(dc, OP_setf8, Rn) |
| #define | INSTR_CREATE_autda(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_autda, Rd, Rd, Rn) |
| #define | INSTR_CREATE_autdb(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_autdb, Rd, Rd, Rn) |
| #define | INSTR_CREATE_autdza(dc, Rd) instr_create_1dst_1src(dc, OP_autdza, Rd, Rd) |
| #define | INSTR_CREATE_autdzb(dc, Rd) instr_create_1dst_1src(dc, OP_autdzb, Rd, Rd) |
| #define | INSTR_CREATE_autia(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_autia, Rd, Rd, Rn) |
| #define | INSTR_CREATE_autia1716(dc) |
| #define | INSTR_CREATE_autiasp(dc) |
| #define | INSTR_CREATE_autiaz(dc) |
| #define | INSTR_CREATE_autib(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_autib, Rd, Rd, Rn) |
| #define | INSTR_CREATE_autib1716(dc) |
| #define | INSTR_CREATE_autibsp(dc) |
| #define | INSTR_CREATE_autibz(dc) |
| #define | INSTR_CREATE_autiza(dc, Rd) instr_create_1dst_1src(dc, OP_autiza, Rd, Rd) |
| #define | INSTR_CREATE_autizb(dc, Rd) instr_create_1dst_1src(dc, OP_autizb, Rd, Rd) |
| #define | INSTR_CREATE_blraa(dc, Rn, Rm) instr_create_1dst_2src(dc, OP_blraa, opnd_create_reg(DR_REG_X30), Rn, Rm) |
| #define | INSTR_CREATE_blraaz(dc, Rn) instr_create_1dst_1src(dc, OP_blraaz, opnd_create_reg(DR_REG_X30), Rn) |
| #define | INSTR_CREATE_blrab(dc, Rn, Rm) instr_create_1dst_2src(dc, OP_blrab, opnd_create_reg(DR_REG_X30), Rn, Rm) |
| #define | INSTR_CREATE_blrabz(dc, Rn) instr_create_1dst_1src(dc, OP_blrabz, opnd_create_reg(DR_REG_X30), Rn) |
| #define | INSTR_CREATE_braa(dc, Rn, Rm) instr_create_0dst_2src(dc, OP_braa, Rn, Rm) |
| #define | INSTR_CREATE_braaz(dc, Rn) instr_create_0dst_1src(dc, OP_braaz, Rn) |
| #define | INSTR_CREATE_brab(dc, Rn, Rm) instr_create_0dst_2src(dc, OP_brab, Rn, Rm) |
| #define | INSTR_CREATE_brabz(dc, Rn) instr_create_0dst_1src(dc, OP_brabz, Rn) |
| #define | INSTR_CREATE_pacda(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_pacda, Rd, Rd, Rn) |
| #define | INSTR_CREATE_pacdb(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_pacdb, Rd, Rd, Rn) |
| #define | INSTR_CREATE_pacdza(dc, Rd) instr_create_1dst_1src(dc, OP_pacdza, Rd, Rd) |
| #define | INSTR_CREATE_pacdzb(dc, Rd) instr_create_1dst_1src(dc, OP_pacdzb, Rd, Rd) |
| #define | INSTR_CREATE_pacga(dc, Rd, Rn, Rm) instr_create_1dst_2src(dc, OP_pacga, Rd, Rn, Rm) |
| #define | INSTR_CREATE_pacia(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_pacia, Rd, Rd, Rn) |
| #define | INSTR_CREATE_pacia1716(dc) |
| #define | INSTR_CREATE_paciasp(dc) |
| #define | INSTR_CREATE_paciaz(dc) |
| #define | INSTR_CREATE_pacib(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_pacib, Rd, Rd, Rn) |
| #define | INSTR_CREATE_pacib1716(dc) |
| #define | INSTR_CREATE_pacibsp(dc) |
| #define | INSTR_CREATE_pacibz(dc) |
| #define | INSTR_CREATE_paciza(dc, Rd) instr_create_1dst_1src(dc, OP_paciza, Rd, Rd) |
| #define | INSTR_CREATE_pacizb(dc, Rd) instr_create_1dst_1src(dc, OP_pacizb, Rd, Rd) |
| #define | INSTR_CREATE_ldraa(dc, Rt, Rn) instr_create_1dst_1src(dc, OP_ldraa, Rt, Rn) |
| #define | INSTR_CREATE_ldraa_imm(dc, Rt, Xn, Rn, simm) instr_create_2dst_3src(dc, OP_ldraa, Rt, Xn, Rn, Xn, simm) |
| #define | INSTR_CREATE_ldrab(dc, Rt, Rn) instr_create_1dst_1src(dc, OP_ldrab, Rt, Rn) |
| #define | INSTR_CREATE_ldrab_imm(dc, Rt, Xn, Rn, simm) instr_create_2dst_3src(dc, OP_ldrab, Rt, Xn, Rn, Xn, simm) |
| #define | INSTR_CREATE_xpacd(dc, Rd) instr_create_1dst_1src(dc, OP_xpacd, Rd, Rd) |
| #define | INSTR_CREATE_xpaci(dc, Rd) instr_create_1dst_1src(dc, OP_xpaci, Rd, Rd) |
| #define | INSTR_CREATE_xpaclri(dc) |
| #define | INSTR_CREATE_eretaa(dc) |
| #define | INSTR_CREATE_eretab(dc) |
| #define | INSTR_CREATE_retaa(dc) |
| #define | INSTR_CREATE_retab(dc) |
| #define | INSTR_CREATE_fjcvtzs(dc, Rd, Rn) instr_create_1dst_1src(dc, OP_fjcvtzs, Rd, Rn) |
| #define | INSTR_CREATE_dc_cvap(dc, Rn) |
| #define | INSTR_CREATE_dc_cvadp(dc, Rn) |
| #define | INSTR_CREATE_sdot_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_sdot, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sdot_sve_idx(dc, Zda, Zn, Zm, index) instr_create_1dst_4src(dc, OP_sdot, Zda, Zda, Zn, Zm, index) |
| #define | INSTR_CREATE_udot_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_udot, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_udot_sve_idx(dc, Zda, Zn, Zm, index) instr_create_1dst_4src(dc, OP_udot, Zda, Zda, Zn, Zm, index) |
| #define | INSTR_CREATE_bfcvtnt_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_3src(dc, OP_bfcvtnt, Zd, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_aesd_sve(dc, Zdn, Zm) instr_create_1dst_2src(dc, OP_aesd, Zdn, Zdn, Zm) |
| #define | INSTR_CREATE_aese_sve(dc, Zdn, Zm) instr_create_1dst_2src(dc, OP_aese, Zdn, Zdn, Zm) |
| #define | INSTR_CREATE_bcax_sve(dc, Zdn, Zm, Zk) instr_create_1dst_3src(dc, OP_bcax, Zdn, Zdn, Zm, Zk) |
| #define | INSTR_CREATE_bsl1n_sve(dc, Zdn, Zm, Zk) instr_create_1dst_3src(dc, OP_bsl1n, Zdn, Zdn, Zm, Zk) |
| #define | INSTR_CREATE_bsl2n_sve(dc, Zdn, Zm, Zk) instr_create_1dst_3src(dc, OP_bsl2n, Zdn, Zdn, Zm, Zk) |
| #define | INSTR_CREATE_bsl_sve(dc, Zdn, Zm, Zk) instr_create_1dst_3src(dc, OP_bsl, Zdn, Zdn, Zm, Zk) |
| #define | INSTR_CREATE_eor3_sve(dc, Zdn, Zm, Zk) instr_create_1dst_3src(dc, OP_eor3, Zdn, Zdn, Zm, Zk) |
| #define | INSTR_CREATE_fmlalb_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_fmlalb, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_fmlalt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_fmlalt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_fmlslb_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_fmlslb, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_fmlslt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_fmlslt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_histseg_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_histseg, Zd, Zn, Zm) |
| #define | INSTR_CREATE_nbsl_sve(dc, Zdn, Zm, Zk) instr_create_1dst_3src(dc, OP_nbsl, Zdn, Zdn, Zm, Zk) |
| #define | INSTR_CREATE_pmul_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_pmul, Zd, Zn, Zm) |
| #define | INSTR_CREATE_rax1_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_rax1, Zd, Zn, Zm) |
| #define | INSTR_CREATE_sm4e_sve(dc, Zdn, Zm) instr_create_1dst_2src(dc, OP_sm4e, Zdn, Zdn, Zm) |
| #define | INSTR_CREATE_sm4ekey_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_sm4ekey, Zd, Zn, Zm) |
| #define | INSTR_CREATE_adclb_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_adclb, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_adclt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_adclt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_bdep_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_bdep, Zd, Zn, Zm) |
| #define | INSTR_CREATE_bext_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_bext, Zd, Zn, Zm) |
| #define | INSTR_CREATE_bgrp_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_bgrp, Zd, Zn, Zm) |
| #define | INSTR_CREATE_eorbt_sve(dc, Zd, Zn, Zm) instr_create_1dst_3src(dc, OP_eorbt, Zd, Zd, Zn, Zm) |
| #define | INSTR_CREATE_eortb_sve(dc, Zd, Zn, Zm) instr_create_1dst_3src(dc, OP_eortb, Zd, Zd, Zn, Zm) |
| #define | INSTR_CREATE_saba_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_saba, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sbclb_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_sbclb, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sbclt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_sbclt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sqdmulh_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_sqdmulh, Zd, Zn, Zm) |
| #define | INSTR_CREATE_sqrdmlah_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_sqrdmlah, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sqrdmlsh_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_sqrdmlsh, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sqrdmulh_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_sqrdmulh, Zd, Zn, Zm) |
| #define | INSTR_CREATE_tbx_sve(dc, Zd, Zn, Zm) instr_create_1dst_3src(dc, OP_tbx, Zd, Zd, Zn, Zm) |
| #define | INSTR_CREATE_uaba_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_uaba, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_addhnb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_addhnb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_addhnt_sve(dc, Zd, Zn, Zm) instr_create_1dst_3src(dc, OP_addhnt, Zd, Zd, Zn, Zm) |
| #define | INSTR_CREATE_pmullb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_pmullb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_pmullt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_pmullt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_raddhnb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_raddhnb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_raddhnt_sve(dc, Zd, Zn, Zm) instr_create_1dst_3src(dc, OP_raddhnt, Zd, Zd, Zn, Zm) |
| #define | INSTR_CREATE_rsubhnb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_rsubhnb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_rsubhnt_sve(dc, Zd, Zn, Zm) instr_create_1dst_3src(dc, OP_rsubhnt, Zd, Zd, Zn, Zm) |
| #define | INSTR_CREATE_sabalb_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_sabalb, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sabalt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_sabalt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sabdlb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_sabdlb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_sabdlt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_sabdlt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_saddlb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_saddlb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_saddlbt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_saddlbt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_saddlt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_saddlt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_saddwb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_saddwb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_saddwt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_saddwt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_smlalb_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_smlalb, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_smlalt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_smlalt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_smlslb_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_smlslb, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_smlslt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_smlslt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_smullb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_smullb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_smullt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_smullt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_sqdmlalb_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_sqdmlalb, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sqdmlalbt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_sqdmlalbt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sqdmlalt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_sqdmlalt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sqdmlslb_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_sqdmlslb, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sqdmlslbt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_sqdmlslbt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sqdmlslt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_sqdmlslt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sqdmullb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_sqdmullb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_sqdmullt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_sqdmullt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_ssublb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_ssublb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_ssublbt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_ssublbt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_ssublt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_ssublt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_ssubltb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_ssubltb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_ssubwb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_ssubwb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_ssubwt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_ssubwt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_subhnb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_subhnb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_subhnt_sve(dc, Zd, Zn, Zm) instr_create_1dst_3src(dc, OP_subhnt, Zd, Zd, Zn, Zm) |
| #define | INSTR_CREATE_uabalb_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_uabalb, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_uabalt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_uabalt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_uabdlb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_uabdlb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_uabdlt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_uabdlt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_uaddlb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_uaddlb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_uaddlt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_uaddlt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_uaddwb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_uaddwb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_uaddwt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_uaddwt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_umlalb_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_umlalb, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_umlalt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_umlalt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_umlslb_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_umlslb, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_umlslt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_umlslt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_umullb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_umullb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_umullt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_umullt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_usublb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_usublb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_usublt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_usublt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_usubwb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_usubwb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_usubwt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_usubwt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_aesimc_sve(dc, Zdn) instr_create_1dst_1src(dc, OP_aesimc, Zdn, Zdn) |
| #define | INSTR_CREATE_aesmc_sve(dc, Zdn) instr_create_1dst_1src(dc, OP_aesmc, Zdn, Zdn) |
| #define | INSTR_CREATE_sqxtnb_sve(dc, Zd, Zn) instr_create_1dst_1src(dc, OP_sqxtnb, Zd, Zn) |
| #define | INSTR_CREATE_sqxtnt_sve(dc, Zd, Zn) instr_create_1dst_2src(dc, OP_sqxtnt, Zd, Zd, Zn) |
| #define | INSTR_CREATE_sqxtunb_sve(dc, Zd, Zn) instr_create_1dst_1src(dc, OP_sqxtunb, Zd, Zn) |
| #define | INSTR_CREATE_sqxtunt_sve(dc, Zd, Zn) instr_create_1dst_2src(dc, OP_sqxtunt, Zd, Zd, Zn) |
| #define | INSTR_CREATE_uqxtnb_sve(dc, Zd, Zn) instr_create_1dst_1src(dc, OP_uqxtnb, Zd, Zn) |
| #define | INSTR_CREATE_uqxtnt_sve(dc, Zd, Zn) instr_create_1dst_2src(dc, OP_uqxtnt, Zd, Zd, Zn) |
| #define | INSTR_CREATE_fmlalt_sve_idx(dc, Zda, Zn, Zm, i3) instr_create_1dst_4src(dc, OP_fmlalt, Zda, Zda, Zn, Zm, i3) |
| #define | INSTR_CREATE_fmlslb_sve_idx(dc, Zda, Zn, Zm, i3) instr_create_1dst_4src(dc, OP_fmlslb, Zda, Zda, Zn, Zm, i3) |
| #define | INSTR_CREATE_fmlslt_sve_idx(dc, Zda, Zn, Zm, i3) instr_create_1dst_4src(dc, OP_fmlslt, Zda, Zda, Zn, Zm, i3) |
| #define | INSTR_CREATE_smlalb_sve_idx_vector(dc, Zda, Zn, Zm, i2) instr_create_1dst_4src(dc, OP_smlalb, Zda, Zda, Zn, Zm, i2) |
| #define | INSTR_CREATE_smlalt_sve_idx_vector(dc, Zda, Zn, Zm, i2) instr_create_1dst_4src(dc, OP_smlalt, Zda, Zda, Zn, Zm, i2) |
| #define | INSTR_CREATE_smlslb_sve_idx_vector(dc, Zda, Zn, Zm, i2) instr_create_1dst_4src(dc, OP_smlslb, Zda, Zda, Zn, Zm, i2) |
| #define | INSTR_CREATE_smlslt_sve_idx_vector(dc, Zda, Zn, Zm, i2) instr_create_1dst_4src(dc, OP_smlslt, Zda, Zda, Zn, Zm, i2) |
| #define | INSTR_CREATE_smullb_sve_idx_vector(dc, Zd, Zn, Zm, i2) instr_create_1dst_3src(dc, OP_smullb, Zd, Zn, Zm, i2) |
| #define | INSTR_CREATE_smullt_sve_idx_vector(dc, Zd, Zn, Zm, i2) instr_create_1dst_3src(dc, OP_smullt, Zd, Zn, Zm, i2) |
| #define | INSTR_CREATE_sqdmlalb_sve_idx_vector(dc, Zda, Zn, Zm, i2) instr_create_1dst_4src(dc, OP_sqdmlalb, Zda, Zda, Zn, Zm, i2) |
| #define | INSTR_CREATE_sqdmlalt_sve_idx_vector(dc, Zda, Zn, Zm, i2) instr_create_1dst_4src(dc, OP_sqdmlalt, Zda, Zda, Zn, Zm, i2) |
| #define | INSTR_CREATE_sqdmlslb_sve_idx_vector(dc, Zda, Zn, Zm, i2) instr_create_1dst_4src(dc, OP_sqdmlslb, Zda, Zda, Zn, Zm, i2) |
| #define | INSTR_CREATE_sqdmlslt_sve_idx_vector(dc, Zda, Zn, Zm, i2) instr_create_1dst_4src(dc, OP_sqdmlslt, Zda, Zda, Zn, Zm, i2) |
| #define | INSTR_CREATE_sqdmulh_sve_idx(dc, Zd, Zn, Zm, i1) instr_create_1dst_3src(dc, OP_sqdmulh, Zd, Zn, Zm, i1) |
| #define | INSTR_CREATE_sqdmullb_sve_idx_vector(dc, Zd, Zn, Zm, i2) instr_create_1dst_3src(dc, OP_sqdmullb, Zd, Zn, Zm, i2) |
| #define | INSTR_CREATE_sqdmullt_sve_idx_vector(dc, Zd, Zn, Zm, i2) instr_create_1dst_3src(dc, OP_sqdmullt, Zd, Zn, Zm, i2) |
| #define | INSTR_CREATE_sqrdmlah_sve_idx(dc, Zda, Zn, Zm, i1) instr_create_1dst_4src(dc, OP_sqrdmlah, Zda, Zda, Zn, Zm, i1) |
| #define | INSTR_CREATE_sqrdmlsh_sve_idx(dc, Zda, Zn, Zm, i1) instr_create_1dst_4src(dc, OP_sqrdmlsh, Zda, Zda, Zn, Zm, i1) |
| #define | INSTR_CREATE_sqrdmulh_sve_idx(dc, Zd, Zn, Zm, i1) instr_create_1dst_3src(dc, OP_sqrdmulh, Zd, Zn, Zm, i1) |
| #define | INSTR_CREATE_umlalb_sve_idx_vector(dc, Zda, Zn, Zm, i2) instr_create_1dst_4src(dc, OP_umlalb, Zda, Zda, Zn, Zm, i2) |
| #define | INSTR_CREATE_umlalt_sve_idx_vector(dc, Zda, Zn, Zm, i2) instr_create_1dst_4src(dc, OP_umlalt, Zda, Zda, Zn, Zm, i2) |
| #define | INSTR_CREATE_umlslb_sve_idx_vector(dc, Zda, Zn, Zm, i2) instr_create_1dst_4src(dc, OP_umlslb, Zda, Zda, Zn, Zm, i2) |
| #define | INSTR_CREATE_umlslt_sve_idx_vector(dc, Zda, Zn, Zm, i2) instr_create_1dst_4src(dc, OP_umlslt, Zda, Zda, Zn, Zm, i2) |
| #define | INSTR_CREATE_umullb_sve_idx_vector(dc, Zd, Zn, Zm, i2) instr_create_1dst_3src(dc, OP_umullb, Zd, Zn, Zm, i2) |
| #define | INSTR_CREATE_umullt_sve_idx_vector(dc, Zd, Zn, Zm, i2) instr_create_1dst_3src(dc, OP_umullt, Zd, Zn, Zm, i2) |
| #define | INSTR_CREATE_addp_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_addp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_faddp_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_faddp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmaxnmp_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fmaxnmp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmaxp_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fmaxp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fminnmp_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fminnmp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fminp_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fminp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_histcnt_sve_pred(dc, Zd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_histcnt, Zd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_shadd_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_shadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_shsub_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_shsub, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_shsubr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_shsubr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_smaxp_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_smaxp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sminp_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_sminp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sqrshl_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_sqrshl, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sqrshlr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_sqrshlr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sqshl_sve_pred(dc, Zdn, Pg, Zm_imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_sqshl, Zdn, Pg, Zdn, Zm_imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sqshlr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_sqshlr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sqsubr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_sqsubr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_srhadd_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_srhadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_srshl_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_srshl, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_srshlr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_srshlr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_suqadd_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_suqadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uhadd_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_uhadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uhsub_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_uhsub, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uhsubr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_uhsubr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_umaxp_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_umaxp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uminp_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_uminp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uqrshl_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_uqrshl, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uqrshlr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_uqrshlr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uqshl_sve_pred(dc, Zdn, Pg, Zm_imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_uqshl, Zdn, Pg, Zdn, Zm_imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uqshlr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_uqshlr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uqsubr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_uqsubr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_urhadd_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_urhadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_urshl_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_urshl, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_urshlr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_urshlr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_usqadd_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_usqadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcvtlt_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvtlt, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcvtnt_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_3src(dc, OP_fcvtnt, Zd, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcvtx_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvtx, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcvtxnt_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_3src(dc, OP_fcvtxnt, Zd, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_flogb_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_flogb, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sadalp_sve_pred(dc, Zda, Pg, Zn) INSTR_PRED(instr_create_1dst_3src(dc, OP_sadalp, Zda, Zda, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sqabs_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_sqabs, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sqneg_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_sqneg, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uadalp_sve_pred(dc, Zda, Pg, Zn) INSTR_PRED(instr_create_1dst_3src(dc, OP_uadalp, Zda, Zda, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cadd_sve(dc, Zdn, Zm, rot) instr_create_1dst_3src(dc, OP_cadd, Zdn, Zdn, Zm, rot) |
| #define | INSTR_CREATE_cdot_sve(dc, Zda, Zn, Zm, rot) instr_create_1dst_4src(dc, OP_cdot, Zda, Zda, Zn, Zm, rot) |
| #define | INSTR_CREATE_cmla_sve(dc, Zda, Zn, Zm, rot) instr_create_1dst_4src(dc, OP_cmla, Zda, Zda, Zn, Zm, rot) |
| #define | INSTR_CREATE_rshrnb_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_rshrnb, Zd, Zn, imm) |
| #define | INSTR_CREATE_rshrnt_sve(dc, Zd, Zn, imm) instr_create_1dst_3src(dc, OP_rshrnt, Zd, Zd, Zn, imm) |
| #define | INSTR_CREATE_shrnb_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_shrnb, Zd, Zn, imm) |
| #define | INSTR_CREATE_shrnt_sve(dc, Zd, Zn, imm) instr_create_1dst_3src(dc, OP_shrnt, Zd, Zd, Zn, imm) |
| #define | INSTR_CREATE_sli_sve(dc, Zd, Zn, imm) instr_create_1dst_3src(dc, OP_sli, Zd, Zd, Zn, imm) |
| #define | INSTR_CREATE_sqcadd_sve(dc, Zdn, Zm, rot) instr_create_1dst_3src(dc, OP_sqcadd, Zdn, Zdn, Zm, rot) |
| #define | INSTR_CREATE_sqrdcmlah_sve(dc, Zda, Zn, Zm, rot) instr_create_1dst_4src(dc, OP_sqrdcmlah, Zda, Zda, Zn, Zm, rot) |
| #define | INSTR_CREATE_sqrshrnb_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_sqrshrnb, Zd, Zn, imm) |
| #define | INSTR_CREATE_sqrshrnt_sve(dc, Zd, Zn, imm) instr_create_1dst_3src(dc, OP_sqrshrnt, Zd, Zd, Zn, imm) |
| #define | INSTR_CREATE_sqrshrunb_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_sqrshrunb, Zd, Zn, imm) |
| #define | INSTR_CREATE_sqrshrunt_sve(dc, Zd, Zn, imm) instr_create_1dst_3src(dc, OP_sqrshrunt, Zd, Zd, Zn, imm) |
| #define | INSTR_CREATE_sqshlu_sve_pred(dc, Zdn, Pg, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_sqshlu, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sqshrnb_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_sqshrnb, Zd, Zn, imm) |
| #define | INSTR_CREATE_sqshrnt_sve(dc, Zd, Zn, imm) instr_create_1dst_3src(dc, OP_sqshrnt, Zd, Zd, Zn, imm) |
| #define | INSTR_CREATE_sqshrunb_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_sqshrunb, Zd, Zn, imm) |
| #define | INSTR_CREATE_sqshrunt_sve(dc, Zd, Zn, imm) instr_create_1dst_3src(dc, OP_sqshrunt, Zd, Zd, Zn, imm) |
| #define | INSTR_CREATE_sri_sve(dc, Zd, Zn, imm) instr_create_1dst_3src(dc, OP_sri, Zd, Zd, Zn, imm) |
| #define | INSTR_CREATE_srshr_sve_pred(dc, Zdn, Pg, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_srshr, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_srsra_sve(dc, Zda, Zn, imm) instr_create_1dst_3src(dc, OP_srsra, Zda, Zda, Zn, imm) |
| #define | INSTR_CREATE_sshllb_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_sshllb, Zd, Zn, imm) |
| #define | INSTR_CREATE_sshllt_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_sshllt, Zd, Zn, imm) |
| #define | INSTR_CREATE_ssra_sve(dc, Zda, Zn, imm) instr_create_1dst_3src(dc, OP_ssra, Zda, Zda, Zn, imm) |
| #define | INSTR_CREATE_uqrshrnb_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_uqrshrnb, Zd, Zn, imm) |
| #define | INSTR_CREATE_uqrshrnt_sve(dc, Zd, Zn, imm) instr_create_1dst_3src(dc, OP_uqrshrnt, Zd, Zd, Zn, imm) |
| #define | INSTR_CREATE_uqshrnb_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_uqshrnb, Zd, Zn, imm) |
| #define | INSTR_CREATE_uqshrnt_sve(dc, Zd, Zn, imm) instr_create_1dst_3src(dc, OP_uqshrnt, Zd, Zd, Zn, imm) |
| #define | INSTR_CREATE_urshr_sve_pred(dc, Zdn, Pg, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_urshr, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ursra_sve(dc, Zda, Zn, imm) instr_create_1dst_3src(dc, OP_ursra, Zda, Zda, Zn, imm) |
| #define | INSTR_CREATE_ushllb_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_ushllb, Zd, Zn, imm) |
| #define | INSTR_CREATE_ushllt_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_ushllt, Zd, Zn, imm) |
| #define | INSTR_CREATE_usra_sve(dc, Zda, Zn, imm) instr_create_1dst_3src(dc, OP_usra, Zda, Zda, Zn, imm) |
| #define | INSTR_CREATE_xar_sve(dc, Zdn, Zm, imm) instr_create_1dst_3src(dc, OP_xar, Zdn, Zdn, Zm, imm) |
| #define | INSTR_CREATE_ldnt1sb_sve_pred(dc, Zt, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1sb, Zt, Zn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldnt1sh_sve_pred(dc, Zt, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1sh, Zt, Zn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldnt1sw_sve_pred(dc, Zt, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1sw, Zt, Zn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uzp1_sve_vector(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_uzp1, Zd, Zn, Zm) |
| #define | INSTR_CREATE_cmla_sve_idx_imm_vector(dc, Zda, Zn, Zm, i1, rot) instr_create_1dst_5src(dc, OP_cmla, Zda, Zda, Zn, Zm, i1, rot) |
| #define | INSTR_CREATE_sqrdcmlah_sve_idx_imm_vector(dc, Zda, Zn, Zm, i1, rot) instr_create_1dst_5src(dc, OP_sqrdcmlah, Zda, Zda, Zn, Zm, i1, rot) |
| #define | INSTR_CREATE_match_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_match, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_nmatch_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_nmatch, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_urecpe_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_urecpe, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ursqrte_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ursqrte, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_whilege_sve(dc, Pd, Rn, Rm) instr_create_1dst_2src(dc, OP_whilege, Pd, Rn, Rm) |
| #define | INSTR_CREATE_whilegt_sve(dc, Pd, Rn, Rm) instr_create_1dst_2src(dc, OP_whilegt, Pd, Rn, Rm) |
| #define | INSTR_CREATE_whilehi_sve(dc, Pd, Rn, Rm) instr_create_1dst_2src(dc, OP_whilehi, Pd, Rn, Rm) |
| #define | INSTR_CREATE_whilehs_sve(dc, Pd, Rn, Rm) instr_create_1dst_2src(dc, OP_whilehs, Pd, Rn, Rm) |
| #define | INSTR_CREATE_whilerw_sve(dc, Pd, Rn, Rm) instr_create_1dst_2src(dc, OP_whilerw, Pd, Rn, Rm) |
| #define | INSTR_CREATE_whilewr_sve(dc, Pd, Rn, Rm) instr_create_1dst_2src(dc, OP_whilewr, Pd, Rn, Rm) |
| #define | INSTR_CREATE_ldg(dc, Rt, Rn) instr_create_1dst_2src(dc, OP_ldg, Rt, Rt, Rn) |
| #define | INSTR_CREATE_st2g_post(dc, Rn, Rt, simm) |
| #define | INSTR_CREATE_st2g_pre(dc, Rn, Rt) |
| #define | INSTR_CREATE_st2g_offset(dc, Rn, Rt) instr_create_1dst_1src(dc, OP_st2g, Rn, Rt) |
| #define | INSTR_CREATE_stg_post(dc, Rn, Rt, simm) |
| #define | INSTR_CREATE_stg_pre(dc, Rn, Rt) |
| #define | INSTR_CREATE_stg_offset(dc, Rn, Rt) instr_create_1dst_1src(dc, OP_stg, Rn, Rt) |
| #define | INSTR_CREATE_stz2g_post(dc, Rn, Rt, simm) |
| #define | INSTR_CREATE_stz2g_pre(dc, Rn, Rt) |
| #define | INSTR_CREATE_stz2g_offset(dc, Rn, Rt) instr_create_1dst_1src(dc, OP_stz2g, Rn, Rt) |
| #define | INSTR_CREATE_stzg_post(dc, Rn, Rt, simm) |
| #define | INSTR_CREATE_stzg_pre(dc, Rn, Rt) |
| #define | INSTR_CREATE_stzg_offset(dc, Rn, Rt) instr_create_1dst_1src(dc, OP_stzg, Rn, Rt) |
| #define | INSTR_CREATE_stgp_post(dc, Rn, Rt, Rt2, simm) |
| #define | INSTR_CREATE_stgp_pre(dc, Rn, Rt, Rt2) |
| #define | INSTR_CREATE_stgp_offset(dc, Rn, Rt, Rt2) instr_create_1dst_2src(dc, OP_stgp, Rn, Rt, Rt2) |
| #define | INSTR_CREATE_gmi(dc, Rd, Rn, Rm) instr_create_1dst_2src(dc, OP_gmi, Rd, Rn, Rm) |
| #define | INSTR_CREATE_irg(dc, Rd, Rn, Rm) instr_create_1dst_2src(dc, OP_irg, Rd, Rn, Rm) |
| #define | INSTR_CREATE_subp(dc, Rd, Rn, Rm) instr_create_1dst_2src(dc, OP_subp, Rd, Rn, Rm) |
| #define | INSTR_CREATE_subps(dc, Rd, Rn, Rm) instr_create_1dst_2src(dc, OP_subps, Rd, Rn, Rm) |
| #define | INSTR_CREATE_addg(dc, Rd, Rn, imm1, imm2) instr_create_1dst_3src(dc, OP_addg, Rd, Rn, imm1, imm2) |
| #define | INSTR_CREATE_subg(dc, Rd, Rn, imm1, imm2) instr_create_1dst_3src(dc, OP_subg, Rd, Rn, imm1, imm2) |
| #define | INSTR_CREATE_dc_gva(dc, Rn) |
| #define | INSTR_CREATE_dc_gzva(dc, Rn) |
| #define | INSTR_CREATE_mul_sve_vector(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_mul, Zd, Zn, Zm) |
| #define | INSTR_CREATE_mul_sve_idx(dc, Zd, Zn, Zm, index) instr_create_1dst_3src(dc, OP_mul, Zd, Zn, Zm, index) |
| #define | INSTR_CREATE_frint32x(dc, Rd, Rn) instr_create_1dst_1src(dc, OP_frint32x, Rd, Rn) |
| #define | INSTR_CREATE_frint32x_vector(dc, Rd, Rn) instr_create_1dst_1src(dc, OP_frint32x, Rd, Rn) |
| #define | INSTR_CREATE_frint32z(dc, Rd, Rn) instr_create_1dst_1src(dc, OP_frint32z, Rd, Rn) |
| #define | INSTR_CREATE_frint32z_vector(dc, Rd, Rn) instr_create_1dst_1src(dc, OP_frint32z, Rd, Rn) |
| #define | INSTR_CREATE_frint64x(dc, Rd, Rn) instr_create_1dst_1src(dc, OP_frint64x, Rd, Rn) |
| #define | INSTR_CREATE_frint64x_vector(dc, Rd, Rn) instr_create_1dst_1src(dc, OP_frint64x, Rd, Rn) |
| #define | INSTR_CREATE_frint64z(dc, Rd, Rn) instr_create_1dst_1src(dc, OP_frint64z, Rd, Rn) |
| #define | INSTR_CREATE_frint64z_vector(dc, Rd, Rn) instr_create_1dst_1src(dc, OP_frint64z, Rd, Rn) |
| #define | INSTR_CREATE_stgm(dc, Rn, Rt) instr_create_1dst_1src(dc, OP_stgm, Rn, Rt) |
| #define | INSTR_CREATE_stzgm(dc, Rn, Rt) instr_create_1dst_1src(dc, OP_stzgm, Rn, Rt) |
| #define | INSTR_CREATE_ldgm(dc, Rt, Rn) instr_create_1dst_1src(dc, OP_ldgm, Rt, Rn) |
| #define | INSTR_CREATE_axflag(dc) instr_create_0dst_0src(dc, OP_axflag) |
| #define | INSTR_CREATE_xaflag(dc) instr_create_0dst_0src(dc, OP_xaflag) |
| #define | INSTR_CREATE_wfe(dc) instr_create_0dst_0src(dc, OP_wfe) |
| #define | INSTR_CREATE_wfi(dc) instr_create_0dst_0src(dc, OP_wfi) |
| #define | INSTR_CREATE_wfet(dc, Rt) instr_create_0dst_1src(dc, OP_wfet, Rt) |
| #define | INSTR_CREATE_wfit(dc, Rt) instr_create_0dst_1src(dc, OP_wfit, Rt) |
Platform-independent macros | |
| #define | XINST_CREATE_debug_instr(dc) INSTR_CREATE_brk((dc), OPND_CREATE_INT16(0)) |
| #define | XINST_CREATE_load(dc, r, m) |
| #define | XINST_CREATE_load_1byte_zext4(dc, r, m) INSTR_CREATE_ldrb(dc, r, m) |
| #define | XINST_CREATE_load_1byte(dc, r, m) INSTR_CREATE_ldrb(dc, r, m) |
| #define | XINST_CREATE_load_2bytes(dc, r, m) INSTR_CREATE_ldrh(dc, r, m) |
| #define | XINST_CREATE_store(dc, m, r) |
| #define | XINST_CREATE_store_1byte(dc, m, r) INSTR_CREATE_strb(dc, m, opnd_create_reg(reg_resize_to_opsz(opnd_get_reg(r), OPSZ_4))) |
| #define | XINST_CREATE_store_2bytes(dc, m, r) INSTR_CREATE_strh(dc, m, opnd_create_reg(reg_resize_to_opsz(opnd_get_reg(r), OPSZ_4))) |
| #define | XINST_CREATE_store_pair(dc, m, r1, r2) INSTR_CREATE_stp(dc, m, r1, r2) |
| #define | XINST_CREATE_load_pair(dc, r1, r2, m) INSTR_CREATE_ldp(dc, r1, r2, m) |
| #define | XINST_CREATE_move(dc, d, s) |
| #define | XINST_CREATE_load_simd(dc, r, m) INSTR_CREATE_ldr((dc), (r), (m)) |
| #define | XINST_CREATE_store_simd(dc, m, r) INSTR_CREATE_str((dc), (m), (r)) |
| #define | XINST_CREATE_jump_reg(dc, r) INSTR_CREATE_br((dc), (r)) |
| #define | XINST_CREATE_load_int(dc, r, i) |
| #define | XINST_CREATE_return(dc) INSTR_CREATE_ret(dc, opnd_create_reg(DR_REG_X30)) |
| #define | XINST_CREATE_jump(dc, t) INSTR_CREATE_b((dc), (t)) |
| #define | XINST_CREATE_jump_short(dc, t) INSTR_CREATE_b((dc), (t)) |
| #define | XINST_CREATE_call(dc, t) INSTR_CREATE_bl(dc, t) |
| #define | XINST_CREATE_jump_cond(dc, pred, t) (INSTR_PRED(INSTR_CREATE_bcond((dc), (t)), (pred))) |
| #define | XINST_CREATE_add(dc, d, s) INSTR_CREATE_add(dc, d, d, s) |
| #define | XINST_CREATE_add_2src(dc, d, s1, s2) INSTR_CREATE_add(dc, d, s1, s2) |
| #define | XINST_CREATE_add_sll(dc, d, s1, s2_toshift, shift_amount) |
| #define | XINST_CREATE_add_s(dc, d, s) INSTR_CREATE_adds(dc, d, d, s) |
| #define | XINST_CREATE_sub(dc, d, s) INSTR_CREATE_sub(dc, d, d, s) |
| #define | XINST_CREATE_sub_s(dc, d, s) INSTR_CREATE_subs(dc, d, d, s) |
| #define | XINST_CREATE_and_s(dc, d, s) INSTR_CREATE_ands(dc, d, d, s) |
| #define | XINST_CREATE_cmp(dc, s1, s2) INSTR_CREATE_cmp(dc, s1, s2) |
| #define | XINST_CREATE_interrupt(dc, i) INSTR_CREATE_svc(dc, (i)) |
| #define | XINST_CREATE_slr_s(dc, d, rm_or_imm) |
| #define | XINST_CREATE_nop(dc) INSTR_CREATE_nop(dc) |
| #define | XINST_CREATE_call_reg(dc, r) INSTR_CREATE_blr(dc, r) |
Detailed Description
AArch64-specific instruction creation convenience macros.
Macro Definition Documentation
◆ INSTR_CREATE_abs_sve_pred
| #define INSTR_CREATE_abs_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_abs, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates an ABS instruction.
This macro is used to encode the forms:
* ABS <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable)
◆ INSTR_CREATE_adclb_sve
| #define INSTR_CREATE_adclb_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_adclb, Zda, Zda, Zn, Zm) |
Creates an ADCLB instruction.
This macro is used to encode the forms:
* ADCLB <Zda>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_adclt_sve
| #define INSTR_CREATE_adclt_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_adclt, Zda, Zda, Zn, Zm) |
Creates an ADCLT instruction.
This macro is used to encode the forms:
* ADCLT <Zda>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_add_sve
| #define INSTR_CREATE_add_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_add, Zd, Zn, Zm) |
Creates a ADD instruction.
This macro is used to encode the forms:
* ADD <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The first destination vector register, Z (Scalable) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_add_sve_pred
| #define INSTR_CREATE_add_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_add, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a ADD instruction.
This macro is used to encode the forms:
* ADD <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and first destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_add_sve_shift
| #define INSTR_CREATE_add_sve_shift | ( | dc, | |
| Zdn, | |||
| imm, | |||
| shift | |||
| ) | instr_create_1dst_4src(dc, OP_add, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift) |
Creates a ADD instruction.
This macro is used to encode the forms:
* ADD <Zdn>.<Ts>, <Zdn>.<Ts>, #<imm>, <shift> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and first destination vector register, Z (Scalable) imm The immediate imm shift The immediate shiftOp for imm
◆ INSTR_CREATE_add_vector
| #define INSTR_CREATE_add_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_add, Rd, Rm, Rn, width) |
Creates a ADD vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_addg
| #define INSTR_CREATE_addg | ( | dc, | |
| Rd, | |||
| Rn, | |||
| imm1, | |||
| imm2 | |||
| ) | instr_create_1dst_3src(dc, OP_addg, Rd, Rn, imm1, imm2) |
Creates an ADDG instruction.
This macro is used to encode the forms:
ADDG <Xd|SP>, <Xn|SP>, #<imm1>, #<imm2>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register, X (Extended, 64 bits). Rn The first source register, X (Extended, 64 bits). imm1 The immediate unsigned imm (must be a multiple of 16). imm2 The immediate unsigned imm.
◆ INSTR_CREATE_addhn2_vector
| #define INSTR_CREATE_addhn2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_addhn2, Rd, Rm, Rn, width) |
Creates a ADDHN2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_addhn_vector
| #define INSTR_CREATE_addhn_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_addhn, Rd, Rm, Rn, width) |
Creates a ADDHN vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_addhnb_sve
| #define INSTR_CREATE_addhnb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_addhnb, Zd, Zn, Zm) |
Creates an ADDHNB instruction.
This macro is used to encode the forms:
ADDHNB <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.b, Z.h or Z.s. Zn The first source vector register. Can be Z.h, Z.s or Z.d. Zm The second source vector register. Can be Z.h, Z.s or Z.d.
◆ INSTR_CREATE_addhnt_sve
| #define INSTR_CREATE_addhnt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_addhnt, Zd, Zd, Zn, Zm) |
Creates an ADDHNT instruction.
This macro is used to encode the forms:
ADDHNT <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The source and destination vector register. Can be Z.b, Z.h or Z.s. Zn The second source vector register. Can be Z.h, Z.s or Z.d. Zm The third source vector register. Can be Z.h, Z.s or Z.d.
◆ INSTR_CREATE_addp_sve_pred
| #define INSTR_CREATE_addp_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_addp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an ADDP instruction.
This macro is used to encode the forms:
ADDP <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_addp_vector
| #define INSTR_CREATE_addp_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_addp, Rd, Rm, Rn, width) |
Creates a ADDP vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_addpl
| #define INSTR_CREATE_addpl | ( | dc, | |
| Rd, | |||
| Rn, | |||
| simm | |||
| ) | instr_create_1dst_2src(dc, OP_addpl, Rd, Rn, simm) |
Creates an ADDPL instruction.
This macro is used to encode the forms:
* ADDPL <Xd|SP>, <Xn|SP>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register, X (Extended, 64 bits). Rn The first source register, X (Extended, 64 bits). simm The signed immediate imm.
◆ INSTR_CREATE_addvl
| #define INSTR_CREATE_addvl | ( | dc, | |
| Rd, | |||
| Rn, | |||
| simm | |||
| ) | instr_create_1dst_2src(dc, OP_addvl, Rd, Rn, simm) |
Creates an ADDVL instruction.
This macro is used to encode the forms:
* ADDVL <Xd|SP>, <Xn|SP>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register, X (Extended, 64 bits). Rn The first source register, X (Extended, 64 bits). simm The signed immediate imm.
◆ INSTR_CREATE_adr_sve
| #define INSTR_CREATE_adr_sve | ( | dc, | |
| Zd, | |||
| Zn | |||
| ) | instr_create_1dst_1src(dc, OP_adr, Zd, Zn) |
Creates an ADR instruction.
This macro is used to encode the forms:
* ADR <Zd>.D, [<Zn>.D, <Zm>.D, SXTW <amount>] * ADR <Zd>.D, [<Zn>.D, <Zm>.D, UXTW <amount>] * ADR <Zd>.<Ts>, [<Zn>.<Ts>, <Zm>.<Ts>, <extend> <amount>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector base register with a register offset, constructed with one of: opnd_create_vector_base_disp_aarch64(Zn, Zm, OPSZ_8, DR_EXTEND_SXTW, 0, 0, 0, OPSZ_0, shift_amount) opnd_create_vector_base_disp_aarch64(Zn, Zm, OPSZ_8, DR_EXTEND_UXTW, 0, 0, 0, OPSZ_0, shift_amount) opnd_create_vector_base_disp_aarch64(Zn, Zm, elsz, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_0, shift_amount)
◆ INSTR_CREATE_aesd_sve
| #define INSTR_CREATE_aesd_sve | ( | dc, | |
| Zdn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_aesd, Zdn, Zdn, Zm) |
Creates an AESD instruction.
This macro is used to encode the forms:
* AESD <Zdn>.B, <Zdn>.B, <Zm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_aese_sve
| #define INSTR_CREATE_aese_sve | ( | dc, | |
| Zdn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_aese, Zdn, Zdn, Zm) |
Creates an AESE instruction.
This macro is used to encode the forms:
* AESE <Zdn>.B, <Zdn>.B, <Zm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_aesimc_sve
| #define INSTR_CREATE_aesimc_sve | ( | dc, | |
| Zdn | |||
| ) | instr_create_1dst_1src(dc, OP_aesimc, Zdn, Zdn) |
Creates an AESIMC instruction.
This macro is used to encode the forms:
AESIMC <Zdn>.B, <Zdn>.B
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z.b.
◆ INSTR_CREATE_aesmc_sve
| #define INSTR_CREATE_aesmc_sve | ( | dc, | |
| Zdn | |||
| ) | instr_create_1dst_1src(dc, OP_aesmc, Zdn, Zdn) |
Creates an AESMC instruction.
This macro is used to encode the forms:
AESMC <Zdn>.B, <Zdn>.B
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z.b.
◆ INSTR_CREATE_and
| #define INSTR_CREATE_and | ( | dc, | |
| rd, | |||
| rn, | |||
| rm_or_imm | |||
| ) |
Value:
(opnd_is_immed(rm_or_imm) \
? instr_create_1dst_2src((dc), OP_and, (rd), (rn), (rm_or_imm)) \
: INSTR_CREATE_and_shift(dc, rd, rn, rm_or_imm, OPND_CREATE_LSL(), \
OPND_CREATE_INT(0)))
disabled_until_i4106_is_fixed Creates an AND instruction with one output and two inputs.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. rd The output register. rn The first input register. rm_or_imm The second input register or immediate.
◆ INSTR_CREATE_and_sve
| #define INSTR_CREATE_and_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_and, Zd, Zn, Zm) |
Creates an AND instruction.
This macro is used to encode the forms:
* AND <Zd>.D, <Zn>.D, <Zm>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_and_sve_imm
| #define INSTR_CREATE_and_sve_imm | ( | dc, | |
| Zdn, | |||
| imm | |||
| ) | instr_create_1dst_2src(dc, OP_and, Zdn, Zdn, imm) |
Creates an AND instruction.
This macro is used to encode the forms:
* AND <Zdn>.<T>, <Zdn>.<T>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). imm The immediate logicalImm. The 13 bit immediate defining a 64, 32, 16 or 8 bit mask of 2, 4, 8, 16, 32 or 64 bit fields.
◆ INSTR_CREATE_and_sve_pred
| #define INSTR_CREATE_and_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_and, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an AND instruction.
This macro is used to encode the forms:
* AND <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_and_sve_pred_b
| #define INSTR_CREATE_and_sve_pred_b | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_and, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates an AND instruction.
This macro is used to encode the forms:
* AND <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_and_vector
| #define INSTR_CREATE_and_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_and, Rd, Rm, Rn) |
Creates a AND vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register.
◆ INSTR_CREATE_ands
| #define INSTR_CREATE_ands | ( | dc, | |
| rd, | |||
| rn, | |||
| rm_or_imm | |||
| ) |
Value:
(opnd_is_immed(rm_or_imm) \
? instr_create_1dst_2src((dc), OP_ands, (rd), (rn), (rm_or_imm)) \
: INSTR_CREATE_ands_shift(dc, rd, rn, rm_or_imm, OPND_CREATE_LSL(), \
OPND_CREATE_INT(0)))
disabled_until_i4106_is_fixed Creates an ANDS instruction with one output and two inputs.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. rd The output register. rn The first input register. rm_or_imm The second input register or immediate.
◆ INSTR_CREATE_ands_sve_pred
| #define INSTR_CREATE_ands_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_ands, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates an ANDS instruction.
This macro is used to encode the forms:
* ANDS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_andv_sve_pred
| #define INSTR_CREATE_andv_sve_pred | ( | dc, | |
| Vd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_andv, Vd, Pg, Zn), DR_PRED_MASKED) |
Creates an ANDV instruction.
This macro is used to encode the forms:
* ANDV <V><d>, <Pg>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vd The destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits), B (byte, 8 bits) or D (doubleword, 64 bits). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_asr_sve
| #define INSTR_CREATE_asr_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_2src(dc, OP_asr, Zd, Zn, imm) |
Creates an ASR instruction.
This macro is used to encode the forms:
* ASR <Zd>.<Ts>, <Zn>.<Ts>, #<const> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). imm The immediate imm, one indexed.
◆ INSTR_CREATE_asr_sve_pred
| #define INSTR_CREATE_asr_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_asr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an ASR instruction.
This macro is used to encode the forms:
* ASR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_asr_sve_pred_wide
| #define INSTR_CREATE_asr_sve_pred_wide | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_asr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an ASR instruction.
This macro is used to encode the forms:
* ASR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_asr_sve_wide
| #define INSTR_CREATE_asr_sve_wide | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_asr, Zd, Zn, Zm) |
Creates an ASR instruction.
This macro is used to encode the forms:
* ASR <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_asrd_sve_pred
| #define INSTR_CREATE_asrd_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| imm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_asrd, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
Creates an ASRD instruction.
This macro is used to encode the forms:
* ASRD <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, #<const> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). imm The immediate imm, one indexed.
◆ INSTR_CREATE_asrr_sve_pred
| #define INSTR_CREATE_asrr_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_asrr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an ASRR instruction.
This macro is used to encode the forms:
* ASRR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_autda
| #define INSTR_CREATE_autda | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_autda, Rd, Rd, Rn) |
Creates an AUTDA instruction.
This macro is used to encode the forms:
* AUTDA <Xd>, <Xn|SP> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination register, X (Extended, 64 bits). Rn The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_autdb
| #define INSTR_CREATE_autdb | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_autdb, Rd, Rd, Rn) |
Creates an AUTDB instruction.
This macro is used to encode the forms:
* AUTDB <Xd>, <Xn|SP> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination register, X (Extended, 64 bits). Rn The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_autdza
| #define INSTR_CREATE_autdza | ( | dc, | |
| Rd | |||
| ) | instr_create_1dst_1src(dc, OP_autdza, Rd, Rd) |
Creates an AUTDZA instruction.
This macro is used to encode the forms:
* AUTDZA <Xd> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination register, X (Extended, 64 bits).
◆ INSTR_CREATE_autdzb
| #define INSTR_CREATE_autdzb | ( | dc, | |
| Rd | |||
| ) | instr_create_1dst_1src(dc, OP_autdzb, Rd, Rd) |
Creates an AUTDZB instruction.
This macro is used to encode the forms:
* AUTDZB <Xd> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination register, X (Extended, 64 bits).
◆ INSTR_CREATE_autia
| #define INSTR_CREATE_autia | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_autia, Rd, Rd, Rn) |
Creates an AUTIA instruction.
This macro is used to encode the forms:
* AUTIA <Xd>, <Xn|SP> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination register, X (Extended, 64 bits). Rn The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_autia1716
| #define INSTR_CREATE_autia1716 | ( | dc | ) |
Value:
instr_create_1dst_2src(dc, OP_autia1716, opnd_create_reg(DR_REG_X17), \
opnd_create_reg(DR_REG_X17), opnd_create_reg(DR_REG_X16))
Creates an AUTIA1716 instruction.
This macro is used to encode the forms:
* AUTIA1716 *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_autiasp
| #define INSTR_CREATE_autiasp | ( | dc | ) |
Value:
instr_create_1dst_2src(dc, OP_autiasp, opnd_create_reg(DR_REG_X30), \
Creates an AUTIASP instruction.
This macro is used to encode the forms:
* AUTIASP *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_autiaz
| #define INSTR_CREATE_autiaz | ( | dc | ) |
Value:
instr_create_1dst_1src(dc, OP_autiaz, opnd_create_reg(DR_REG_X30), \
opnd_create_reg(DR_REG_X30))
Creates an AUTIAZ instruction.
This macro is used to encode the forms:
* AUTIAZ *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_autib
| #define INSTR_CREATE_autib | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_autib, Rd, Rd, Rn) |
Creates an AUTIB instruction.
This macro is used to encode the forms:
* AUTIB <Xd>, <Xn|SP> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination register, X (Extended, 64 bits). Rn The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_autib1716
| #define INSTR_CREATE_autib1716 | ( | dc | ) |
Value:
instr_create_1dst_2src(dc, OP_autib1716, opnd_create_reg(DR_REG_X17), \
opnd_create_reg(DR_REG_X17), opnd_create_reg(DR_REG_X16))
Creates an AUTIB1716 instruction.
This macro is used to encode the forms:
* AUTIB1716 *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_autibsp
| #define INSTR_CREATE_autibsp | ( | dc | ) |
Value:
instr_create_1dst_2src(dc, OP_autibsp, opnd_create_reg(DR_REG_X30), \
Creates an AUTIBSP instruction.
This macro is used to encode the forms:
* AUTIBSP *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_autibz
| #define INSTR_CREATE_autibz | ( | dc | ) |
Value:
instr_create_1dst_1src(dc, OP_autibz, opnd_create_reg(DR_REG_X30), \
opnd_create_reg(DR_REG_X30))
Creates an AUTIBZ instruction.
This macro is used to encode the forms:
* AUTIBZ *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_autiza
| #define INSTR_CREATE_autiza | ( | dc, | |
| Rd | |||
| ) | instr_create_1dst_1src(dc, OP_autiza, Rd, Rd) |
Creates an AUTIZA instruction.
This macro is used to encode the forms:
* AUTIZA <Xd> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination register, X (Extended, 64 bits).
◆ INSTR_CREATE_autizb
| #define INSTR_CREATE_autizb | ( | dc, | |
| Rd | |||
| ) | instr_create_1dst_1src(dc, OP_autizb, Rd, Rd) |
Creates an AUTIZB instruction.
This macro is used to encode the forms:
* AUTIZB <Xd> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination register, X (Extended, 64 bits).
◆ INSTR_CREATE_axflag
| #define INSTR_CREATE_axflag | ( | dc | ) | instr_create_0dst_0src(dc, OP_axflag) |
Creates an AXFLAG instruction.
This macro is used to encode the forms:
AXFLAG
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_bcax
| #define INSTR_CREATE_bcax | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Ra | |||
| ) | instr_create_1dst_4src(dc, OP_bcax, Rd, Rn, Rm, Ra, OPND_CREATE_BYTE()) |
Creates a BCAX instruction.
This macro is used to encode the forms:
* BCAX <Bd>.16B, <Bn>.16B, <Bm>.16B, <Ba>.16B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register, Q (quadword, 128 bits) Rn The second source vector register, Q (quadword, 128 bits) Rm The third source vector register, Q (quadword, 128 bits) Ra The fourth source vector register, Q (quadword, 128 bits)
◆ INSTR_CREATE_bcax_sve
| #define INSTR_CREATE_bcax_sve | ( | dc, | |
| Zdn, | |||
| Zm, | |||
| Zk | |||
| ) | instr_create_1dst_3src(dc, OP_bcax, Zdn, Zdn, Zm, Zk) |
Creates a BCAX instruction.
This macro is used to encode the forms:
* BCAX <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Zm The second source vector register, Z (Scalable). Zk The third source vector register, Z (Scalable).
◆ INSTR_CREATE_bcond
| #define INSTR_CREATE_bcond | ( | dc, | |
| pc | |||
| ) | instr_create_0dst_1src((dc), OP_bcond, (pc)) |
◆ INSTR_CREATE_bdep_sve
| #define INSTR_CREATE_bdep_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_bdep, Zd, Zn, Zm) |
Creates a BDEP instruction.
This macro is used to encode the forms:
* BDEP <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_bext_sve
| #define INSTR_CREATE_bext_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_bext, Zd, Zn, Zm) |
Creates a BEXT instruction.
This macro is used to encode the forms:
* BEXT <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_bfcvt
| #define INSTR_CREATE_bfcvt | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_bfcvt, Rd, Rn) |
Creates a BFCVT instruction.
This macro is used to encode the forms:
* BFCVT <Hd>, <Sn> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register, H (halfword, 16 bits). Rn The source register, S (singleword, 32 bits).
◆ INSTR_CREATE_bfcvt_sve_pred
| #define INSTR_CREATE_bfcvt_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_bfcvt, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a BFCVT instruction.
This macro is used to encode the forms:
* BFCVT <Zd>.H, <Pg>/M, <Zn>.S *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_bfcvtn2_vector
| #define INSTR_CREATE_bfcvtn2_vector | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_bfcvtn2, Rd, Rn, OPND_CREATE_SINGLE()) |
Creates a BFCVTN2 instruction.
This macro is used to encode the forms:
* BFCVTN2 <Vd>.8H, <Vn>.4S *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination vector register, Q (quadword, 128 bits). Rn The source vector register, Q (quadword, 128 bits).
◆ INSTR_CREATE_bfcvtn_vector
| #define INSTR_CREATE_bfcvtn_vector | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_bfcvtn, Rd, Rn, OPND_CREATE_SINGLE()) |
Creates a BFCVTN instruction.
This macro is used to encode the forms:
* BFCVTN <Vd>.4H, <Vn>.4S *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination vector register, D (doubleword, 64 bits). Rn The source vector register, Q (quadword, 128 bits).
◆ INSTR_CREATE_bfcvtnt_sve_pred
| #define INSTR_CREATE_bfcvtnt_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_bfcvtnt, Zd, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a BFCVTNT instruction.
This macro is used to encode the forms:
* BFCVTNT <Zd>.H, <Pg>/M, <Zn>.S *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The second source vector register, Z (Scalable).
◆ INSTR_CREATE_bfdot_sve
| #define INSTR_CREATE_bfdot_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_bfdot, Zda, Zda, Zn, Zm) |
Creates a BFDOT instruction.
This macro is used to encode the forms:
* BFDOT <Zda>.S, <Zn>.H, <Zm>.H *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_bfdot_sve_idx
| #define INSTR_CREATE_bfdot_sve_idx | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| index | |||
| ) | instr_create_1dst_4src(dc, OP_bfdot, Zda, Zda, Zn, Zm, index) |
Creates a BFDOT instruction.
This macro is used to encode the forms:
* BFDOT <Zda>.S, <Zn>.H, <Zm>.H[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable). index The immediate index
◆ INSTR_CREATE_bfdot_vector
| #define INSTR_CREATE_bfdot_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_4src(dc, OP_bfdot, Rd, Rd, Rn, Rm, OPND_CREATE_HALF()) |
Creates a BFDOT instruction.
This macro is used to encode the forms:
* BFDOT <Vd>.<Ts>, <Vn>.<Tb>, <Vm>.<Tb> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits). Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits). Rm The third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits).
◆ INSTR_CREATE_bfdot_vector_idx
| #define INSTR_CREATE_bfdot_vector_idx | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| index | |||
| ) | instr_create_1dst_5src(dc, OP_bfdot, Rd, Rd, Rn, Rm, index, OPND_CREATE_HALF()) |
Creates a BFDOT instruction.
This macro is used to encode the forms:
* BFDOT <Vd>.<Ts>, <Vn>.<Tb>, <Vm>.2H[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits). Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits). Rm The third source vector register, Q (quadword, 128 bits). index The immediate index for Rm, in the range 0-3.
◆ INSTR_CREATE_bfmlalb_sve
| #define INSTR_CREATE_bfmlalb_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_bfmlalb, Zda, Zda, Zn, Zm) |
Creates a BFMLALB instruction.
This macro is used to encode the forms:
* BFMLALB <Zda>.S, <Zn>.H, <Zm>.H *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_bfmlalb_sve_idx
| #define INSTR_CREATE_bfmlalb_sve_idx | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| index | |||
| ) | instr_create_1dst_4src(dc, OP_bfmlalb, Zda, Zda, Zn, Zm, index) |
Creates a BFMLALB instruction.
This macro is used to encode the forms:
* BFMLALB <Zda>.S, <Zn>.H, <Zm>.H[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable). index The immediate index
◆ INSTR_CREATE_bfmlalb_vector
| #define INSTR_CREATE_bfmlalb_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_4src(dc, OP_bfmlalb, Rd, Rd, Rn, Rm, OPND_CREATE_HALF()) |
Creates a BFMLALB instruction.
This macro is used to encode the forms:
* BFMLALB <Vd>.4S, <Vn>.8H, <Vm>.8H *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination vector register, Q (quadword, 128 bits). Rn The second source vector register, Q (quadword, 128 bits). Rm The third source vector register, Q (quadword, 128 bits).
◆ INSTR_CREATE_bfmlalb_vector_idx
| #define INSTR_CREATE_bfmlalb_vector_idx | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| index | |||
| ) | instr_create_1dst_5src(dc, OP_bfmlalb, Rd, Rd, Rn, Rm, index, OPND_CREATE_HALF()) |
Creates a BFMLALB instruction.
This macro is used to encode the forms:
* BFMLALB <Vd>.4S, <Vn>.8H, <Vm>.H[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination vector register, Q (quadword, 128 bits). Rn The second source vector register, Q (quadword, 128 bits). Rm The third source vector register, Q (quadword, 128 bits). index The immediate index for Rm, in the range 0-7.
◆ INSTR_CREATE_bfmlalt_sve
| #define INSTR_CREATE_bfmlalt_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_bfmlalt, Zda, Zda, Zn, Zm) |
Creates a BFMLALT instruction.
This macro is used to encode the forms:
* BFMLALT <Zda>.S, <Zn>.H, <Zm>.H *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_bfmlalt_sve_idx
| #define INSTR_CREATE_bfmlalt_sve_idx | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| index | |||
| ) | instr_create_1dst_4src(dc, OP_bfmlalt, Zda, Zda, Zn, Zm, index) |
Creates a BFMLALT instruction.
This macro is used to encode the forms:
* BFMLALT <Zda>.S, <Zn>.H, <Zm>.H[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable). index The immediate index
◆ INSTR_CREATE_bfmlalt_vector
| #define INSTR_CREATE_bfmlalt_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_4src(dc, OP_bfmlalt, Rd, Rd, Rn, Rm, OPND_CREATE_HALF()) |
Creates a BFMLALT instruction.
This macro is used to encode the forms:
* BFMLALT <Vd>.4S, <Vn>.8H, <Vm>.8H *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination vector register, Q (quadword, 128 bits). Rn The second source vector register, Q (quadword, 128 bits). Rm The third source vector register, Q (quadword, 128 bits).
◆ INSTR_CREATE_bfmlalt_vector_idx
| #define INSTR_CREATE_bfmlalt_vector_idx | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| index | |||
| ) | instr_create_1dst_5src(dc, OP_bfmlalt, Rd, Rd, Rn, Rm, index, OPND_CREATE_HALF()) |
Creates a BFMLALT instruction.
This macro is used to encode the forms:
* BFMLALT <Vd>.4S, <Vn>.8H, <Vm>.H[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination vector register, Q (quadword, 128 bits). Rn The second source vector register, Q (quadword, 128 bits). Rm The third source vector register, Q (quadword, 128 bits). index The immediate index for Rm, in the range 0-7.
◆ INSTR_CREATE_bfmmla_sve
| #define INSTR_CREATE_bfmmla_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_bfmmla, Zda, Zda, Zn, Zm) |
Creates a BFMMLA instruction.
This macro is used to encode the forms:
* BFMMLA <Zda>.S, <Zn>.H, <Zm>.H *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_bfmmla_vector
| #define INSTR_CREATE_bfmmla_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_4src(dc, OP_bfmmla, Rd, Rd, Rn, Rm, OPND_CREATE_HALF()) |
Creates a BFMMLA instruction.
This macro is used to encode the forms:
* BFMMLA <Vd>.4S, <Vn>.8H, <Vm>.8H *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination vector register, Q (quadword, 128 bits). Rn The second source vector register, Q (quadword, 128 bits). Rm The third source vector register, Q (quadword, 128 bits).
◆ INSTR_CREATE_bgrp_sve
| #define INSTR_CREATE_bgrp_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_bgrp, Zd, Zn, Zm) |
Creates a BGRP instruction.
This macro is used to encode the forms:
* BGRP <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_bic_sve
| #define INSTR_CREATE_bic_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_bic, Zd, Zn, Zm) |
Creates a BIC instruction.
This macro is used to encode the forms:
* BIC <Zd>.D, <Zn>.D, <Zm>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_bic_sve_imm
| #define INSTR_CREATE_bic_sve_imm | ( | dc, | |
| Zdn, | |||
| imm | |||
| ) | instr_create_1dst_2src(dc, OP_and, Zdn, Zdn, opnd_invert_immed_int(imm)) |
Creates a BIC instruction.
This macro is used to encode the forms:
* BIC <Zdn>.<T>, <Zdn>.<T>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). imm The immediate logicalImm. The 13 bit immediate defining a 64, 32, 16 or 8 bit mask of 2, 4, 8, 16, 32 or 64 bit fields.
◆ INSTR_CREATE_bic_sve_pred
| #define INSTR_CREATE_bic_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_bic, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a BIC instruction.
This macro is used to encode the forms:
* BIC <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_bic_sve_pred_b
| #define INSTR_CREATE_bic_sve_pred_b | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_bic, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates a BIC instruction.
This macro is used to encode the forms:
* BIC <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_bic_vector
| #define INSTR_CREATE_bic_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_bic, Rd, Rm, Rn) |
Creates a BIC vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register.
◆ INSTR_CREATE_bics_sve_pred
| #define INSTR_CREATE_bics_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_bics, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates a BICS instruction.
This macro is used to encode the forms:
* BICS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_bif_vector
| #define INSTR_CREATE_bif_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_bif, Rd, Rm, Rn) |
Creates a BIF vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register.
◆ INSTR_CREATE_bit_vector
| #define INSTR_CREATE_bit_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_bit, Rd, Rm, Rn) |
Creates a BIT vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register.
◆ INSTR_CREATE_bl
| #define INSTR_CREATE_bl | ( | dc, | |
| pc | |||
| ) | instr_create_1dst_1src((dc), OP_bl, opnd_create_reg(DR_REG_X30), (pc)) |
◆ INSTR_CREATE_blraa
| #define INSTR_CREATE_blraa | ( | dc, | |
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_blraa, opnd_create_reg(DR_REG_X30), Rn, Rm) |
Creates a BLRAA instruction.
This macro is used to encode the forms:
* BLRAA <Xn>, <Xm|SP> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The first source register, X (Extended, 64 bits). Rm The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_blraaz
| #define INSTR_CREATE_blraaz | ( | dc, | |
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_blraaz, opnd_create_reg(DR_REG_X30), Rn) |
Creates a BLRAAZ instruction.
This macro is used to encode the forms:
* BLRAAZ <Xn> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The source register, X (Extended, 64 bits).
◆ INSTR_CREATE_blrab
| #define INSTR_CREATE_blrab | ( | dc, | |
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_blrab, opnd_create_reg(DR_REG_X30), Rn, Rm) |
Creates a BLRAB instruction.
This macro is used to encode the forms:
* BLRAB <Xn>, <Xm|SP> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The first source register, X (Extended, 64 bits). Rm The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_blrabz
| #define INSTR_CREATE_blrabz | ( | dc, | |
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_blrabz, opnd_create_reg(DR_REG_X30), Rn) |
Creates a BLRABZ instruction.
This macro is used to encode the forms:
* BLRABZ <Xn> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The source register, X (Extended, 64 bits).
◆ INSTR_CREATE_braa
| #define INSTR_CREATE_braa | ( | dc, | |
| Rn, | |||
| Rm | |||
| ) | instr_create_0dst_2src(dc, OP_braa, Rn, Rm) |
Creates a BRAA instruction.
This macro is used to encode the forms:
* BRAA <Xn>, <Xm|SP> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The first source register, X (Extended, 64 bits). Rm The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_braaz
| #define INSTR_CREATE_braaz | ( | dc, | |
| Rn | |||
| ) | instr_create_0dst_1src(dc, OP_braaz, Rn) |
Creates a BRAAZ instruction.
This macro is used to encode the forms:
* BRAAZ <Xn> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The source register, X (Extended, 64 bits).
◆ INSTR_CREATE_brab
| #define INSTR_CREATE_brab | ( | dc, | |
| Rn, | |||
| Rm | |||
| ) | instr_create_0dst_2src(dc, OP_brab, Rn, Rm) |
Creates a BRAB instruction.
This macro is used to encode the forms:
* BRAB <Xn>, <Xm|SP> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The first source register, X (Extended, 64 bits). Rm The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_brabz
| #define INSTR_CREATE_brabz | ( | dc, | |
| Rn | |||
| ) | instr_create_0dst_1src(dc, OP_brabz, Rn) |
Creates a BRABZ instruction.
This macro is used to encode the forms:
* BRABZ <Xn> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The source register, X (Extended, 64 bits).
◆ INSTR_CREATE_brka_sve_pred
| #define INSTR_CREATE_brka_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_brka, Pd, Pg, Pn), DR_PRED_MASKED) |
Creates a BRKA instruction.
This macro is used to encode the forms:
* BRKA <Pd>.B, <Pg>/<ZM>, <Pn>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The source predicate register, P (Predicate).
◆ INSTR_CREATE_brkas_sve_pred
| #define INSTR_CREATE_brkas_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_brkas, Pd, Pg, Pn), DR_PRED_MASKED) |
Creates a BRKAS instruction.
This macro is used to encode the forms:
* BRKAS <Pd>.B, <Pg>/Z, <Pn>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The source predicate register, P (Predicate).
◆ INSTR_CREATE_brkb_sve_pred
| #define INSTR_CREATE_brkb_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_brkb, Pd, Pg, Pn), DR_PRED_MASKED) |
Creates a BRKB instruction.
This macro is used to encode the forms:
* BRKB <Pd>.B, <Pg>/<ZM>, <Pn>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The source predicate register, P (Predicate).
◆ INSTR_CREATE_brkbs_sve_pred
| #define INSTR_CREATE_brkbs_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_brkbs, Pd, Pg, Pn), DR_PRED_MASKED) |
Creates a BRKBS instruction.
This macro is used to encode the forms:
* BRKBS <Pd>.B, <Pg>/Z, <Pn>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The source predicate register, P (Predicate).
◆ INSTR_CREATE_brkn_sve_pred
| #define INSTR_CREATE_brkn_sve_pred | ( | dc, | |
| Pdm, | |||
| Pg, | |||
| Pn | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_brkn, Pdm, Pg, Pn, Pdm), DR_PRED_MASKED) |
Creates a BRKN instruction.
This macro is used to encode the forms:
* BRKN <Pdm>.B, <Pg>/Z, <Pn>.B, <Pdm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pdm The second source and destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate).
◆ INSTR_CREATE_brkns_sve_pred
| #define INSTR_CREATE_brkns_sve_pred | ( | dc, | |
| Pdm, | |||
| Pg, | |||
| Pn | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_brkns, Pdm, Pg, Pn, Pdm), DR_PRED_MASKED) |
Creates a BRKNS instruction.
This macro is used to encode the forms:
* BRKNS <Pdm>.B, <Pg>/Z, <Pn>.B, <Pdm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pdm The second source and destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate).
◆ INSTR_CREATE_brkpa_sve_pred
| #define INSTR_CREATE_brkpa_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpa, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates a BRKPA instruction.
This macro is used to encode the forms:
* BRKPA <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_brkpas_sve_pred
| #define INSTR_CREATE_brkpas_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpas, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates a BRKPAS instruction.
This macro is used to encode the forms:
* BRKPAS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_brkpb_sve_pred
| #define INSTR_CREATE_brkpb_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpb, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates a BRKPB instruction.
This macro is used to encode the forms:
* BRKPB <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_brkpbs_sve_pred
| #define INSTR_CREATE_brkpbs_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpbs, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates a BRKPBS instruction.
This macro is used to encode the forms:
* BRKPBS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_bsl1n_sve
| #define INSTR_CREATE_bsl1n_sve | ( | dc, | |
| Zdn, | |||
| Zm, | |||
| Zk | |||
| ) | instr_create_1dst_3src(dc, OP_bsl1n, Zdn, Zdn, Zm, Zk) |
Creates a BSL1N instruction.
This macro is used to encode the forms:
* BSL1N <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Zm The second source vector register, Z (Scalable). Zk The third source vector register, Z (Scalable).
◆ INSTR_CREATE_bsl2n_sve
| #define INSTR_CREATE_bsl2n_sve | ( | dc, | |
| Zdn, | |||
| Zm, | |||
| Zk | |||
| ) | instr_create_1dst_3src(dc, OP_bsl2n, Zdn, Zdn, Zm, Zk) |
Creates a BSL2N instruction.
This macro is used to encode the forms:
* BSL2N <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Zm The second source vector register, Z (Scalable). Zk The third source vector register, Z (Scalable).
◆ INSTR_CREATE_bsl_sve
| #define INSTR_CREATE_bsl_sve | ( | dc, | |
| Zdn, | |||
| Zm, | |||
| Zk | |||
| ) | instr_create_1dst_3src(dc, OP_bsl, Zdn, Zdn, Zm, Zk) |
Creates a BSL instruction.
This macro is used to encode the forms:
* BSL <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Zm The second source vector register, Z (Scalable). Zk The third source vector register, Z (Scalable).
◆ INSTR_CREATE_bsl_vector
| #define INSTR_CREATE_bsl_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_bsl, Rd, Rm, Rn) |
Creates a BSL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register.
◆ INSTR_CREATE_cadd_sve
| #define INSTR_CREATE_cadd_sve | ( | dc, | |
| Zdn, | |||
| Zm, | |||
| rot | |||
| ) | instr_create_1dst_3src(dc, OP_cadd, Zdn, Zdn, Zm, rot) |
Creates a CADD instruction.
This macro is used to encode the forms:
CADD <Zdn>.<Ts>, <Zdn>.<Ts>, <Zm>.<Ts>, <const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. rot The immediate rotation which must be 90 or 270.
◆ INSTR_CREATE_ccmn
| #define INSTR_CREATE_ccmn | ( | dc, | |
| Rn, | |||
| Op, | |||
| nzcv, | |||
| cond | |||
| ) | instr_create_0dst_4src(dc, OP_ccmn, Rn, Op, nzcv, cond) |
Creates a CCMN (Conditional Compare Negative) instruction. Sets the NZCV flags to the result of a comparison of its two source values if the named input condition is true, or to an immediate value if the input condition is false. The comparison is based on a negated second source value (Op) if an immediate, inverted if a register.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. cond A 4-bit immediate value created using cond_create_cond() specifying the condition used for the comparison. For example opnd_create_cond(DR_PRED_EQ). Rn The GPR source register. Op Either a 5-bit immediate (use opnd_create_immed_uint() to create the operand, e.g. opnd_create_immed_uint(val, OPSZ_5b)) or a GPR source register. nzcv The 4 bit NZCV flags value used if the input condition is false. (use opnd_create_immed_uint() to create the operand, e.g. opnd_create_immed_uint(val, OPSZ_4b)).
◆ INSTR_CREATE_ccmp
| #define INSTR_CREATE_ccmp | ( | dc, | |
| Rn, | |||
| Op, | |||
| nzcv, | |||
| cond | |||
| ) | instr_create_0dst_4src(dc, OP_ccmp, Rn, Op, nzcv, cond) |
Creates a CCMP (Conditional Compare) instruction. Sets the NZCV flags to the result of a comparison of its two source values if the named input condition is true, or to an immediate value if the input condition is false.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. cond A 4-bit immediate value created using cond_create_cond() specifying the condition used for the comparison. For example opnd_create_cond(DR_PRED_EQ). Rn The GPR source register. Op Either a 5-bit immediate (use opnd_create_immed_uint() to create the operand, e.g. opnd_create_immed_uint(val, OPSZ_5b)) or a GPR source register. nzcv The 4 bit NZCV flags value used if the input condition is false. (use opnd_create_immed_uint() to create the operand, e.g. opnd_create_immed_uint(val, OPSZ_4b)).
◆ INSTR_CREATE_cdot_sve
| #define INSTR_CREATE_cdot_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| rot | |||
| ) | instr_create_1dst_4src(dc, OP_cdot, Zda, Zda, Zn, Zm, rot) |
Creates a CDOT instruction.
This macro is used to encode the forms:
CDOT <Zda>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>, <const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.s or Z.d. Zn The second source vector register. Can be Z.b or Z.h. Zm The third source vector register. Can be Z.b or Z.h. rot The immediate rotation which must be 0, 90, 180 or 270.
◆ INSTR_CREATE_cfinv
| #define INSTR_CREATE_cfinv | ( | dc | ) | instr_create_0dst_0src(dc, OP_cfinv) |
Creates a CFINV instruction.
This macro is used to encode the forms:
* CFINV *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_clasta_sve_scalar
| #define INSTR_CREATE_clasta_sve_scalar | ( | dc, | |
| Rdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_clasta, Rdn, Pg, Rdn, Zm), DR_PRED_MASKED) |
Creates a CLASTA instruction.
This macro is used to encode the forms:
* CLASTA <R><dn>, <Pg>, <R><dn>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register. Can be W (Word, 32 bits) or X (Extended, 64 bits). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_clasta_sve_simd_fp
| #define INSTR_CREATE_clasta_sve_simd_fp | ( | dc, | |
| Vdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_clasta, Vdn, Pg, Vdn, Zm), DR_PRED_MASKED) |
Creates a CLASTA instruction.
This macro is used to encode the forms:
* CLASTA <V><dn>, <Pg>, <V><dn>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vdn The first source and destination register. Can be D (doubleword, 64 bits), S (singleword, 32 bits), H (halfword, 16 bits) or B (byte, 8 bits). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_clasta_sve_vector
| #define INSTR_CREATE_clasta_sve_vector | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_clasta, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a CLASTA instruction.
This macro is used to encode the forms:
* CLASTA <Zdn>.<Ts>, <Pg>, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_clastb_sve_scalar
| #define INSTR_CREATE_clastb_sve_scalar | ( | dc, | |
| Rdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_clastb, Rdn, Pg, Rdn, Zm), DR_PRED_MASKED) |
Creates a CLASTB instruction.
This macro is used to encode the forms:
* CLASTB <R><dn>, <Pg>, <R><dn>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register. Can be W (Word, 32 bits) or X (Extended, 64 bits). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_clastb_sve_simd_fp
| #define INSTR_CREATE_clastb_sve_simd_fp | ( | dc, | |
| Vdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_clastb, Vdn, Pg, Vdn, Zm), DR_PRED_MASKED) |
Creates a CLASTB instruction.
This macro is used to encode the forms:
* CLASTB <V><dn>, <Pg>, <V><dn>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vdn The first source and destination register. Can be D (doubleword, 64 bits), S (singleword, 32 bits), H (halfword, 16 bits) or B (byte, 8 bits). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_clastb_sve_vector
| #define INSTR_CREATE_clastb_sve_vector | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_clastb, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a CLASTB instruction.
This macro is used to encode the forms:
* CLASTB <Zdn>.<Ts>, <Pg>, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_cls_sve_pred
| #define INSTR_CREATE_cls_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_cls, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a CLS instruction.
This macro is used to encode the forms:
* CLS <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_clz_sve_pred
| #define INSTR_CREATE_clz_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_clz, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a CLZ instruction.
This macro is used to encode the forms:
* CLZ <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_cmeq_vector
| #define INSTR_CREATE_cmeq_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_cmeq, Rd, Rm, Rn, width) |
Creates a CMEQ vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_cmge_vector
| #define INSTR_CREATE_cmge_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_cmge, Rd, Rm, Rn, width) |
Creates a CMGE vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_cmgt_vector
| #define INSTR_CREATE_cmgt_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_cmgt, Rd, Rm, Rn, width) |
Creates a CMGT vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_cmhi_vector
| #define INSTR_CREATE_cmhi_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_cmhi, Rd, Rm, Rn, width) |
Creates a CMHI vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_cmhs_vector
| #define INSTR_CREATE_cmhs_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_cmhs, Rd, Rm, Rn, width) |
Creates a CMHS vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_cmla_sve
| #define INSTR_CREATE_cmla_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| rot | |||
| ) | instr_create_1dst_4src(dc, OP_cmla, Zda, Zda, Zn, Zm, rot) |
Creates a CMLA instruction.
This macro is used to encode the forms:
CMLA <Zda>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts>, <const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. Zm The third source vector register. Can be Z.b, Z.h, Z.s or Z.d. rot The immediate rotation which must be 0, 90, 180 or 270.
◆ INSTR_CREATE_cmla_sve_idx_imm_vector
| #define INSTR_CREATE_cmla_sve_idx_imm_vector | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| i1, | |||
| rot | |||
| ) | instr_create_1dst_5src(dc, OP_cmla, Zda, Zda, Zn, Zm, i1, rot) |
Creates a CMLA instruction.
This macro is used to encode the forms:
CMLA <Zda>.S, <Zn>.S, <Zm>.S[<imm>], <const> CMLA <Zda>.H, <Zn>.H, <Zm>.H[<imm>], <const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.s or Z.h. Zn The second source vector register. Can be Z.s or Z.h. Zm The third source vector register. Can be Z.s or Z.h. i1 The immediate index for Zm. rot The immediate rotation which must be 0, 90, 180 or 270.
◆ INSTR_CREATE_cmpeq_sve_pred
| #define INSTR_CREATE_cmpeq_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpeq, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a CMPEQ instruction.
This macro is used to encode the forms:
* CMPEQ <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D * CMPEQ <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_cmpeq_sve_pred_simm
| #define INSTR_CREATE_cmpeq_sve_pred_simm | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| simm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpeq, Pd, Pg, Zn, simm), DR_PRED_MASKED) |
Creates a CMPEQ instruction.
This macro is used to encode the forms:
* CMPEQ <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable) simm The signed immediate imm
◆ INSTR_CREATE_cmpge_sve_pred
| #define INSTR_CREATE_cmpge_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpge, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a CMPGE instruction.
This macro is used to encode the forms:
* CMPGE <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D * CMPGE <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_cmpge_sve_pred_simm
| #define INSTR_CREATE_cmpge_sve_pred_simm | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| simm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpge, Pd, Pg, Zn, simm), DR_PRED_MASKED) |
Creates a CMPGE instruction.
This macro is used to encode the forms:
* CMPGE <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable) simm The signed immediate imm
◆ INSTR_CREATE_cmpgt_sve_pred
| #define INSTR_CREATE_cmpgt_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpgt, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a CMPGT instruction.
This macro is used to encode the forms:
* CMPGT <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D * CMPGT <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_cmpgt_sve_pred_simm
| #define INSTR_CREATE_cmpgt_sve_pred_simm | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| simm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpgt, Pd, Pg, Zn, simm), DR_PRED_MASKED) |
Creates a CMPGT instruction.
This macro is used to encode the forms:
* CMPGT <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable) simm The signed immediate imm
◆ INSTR_CREATE_cmphi_sve_pred
| #define INSTR_CREATE_cmphi_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphi, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a CMPHI instruction.
This macro is used to encode the forms:
* CMPHI <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D * CMPHI <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_cmphi_sve_pred_imm
| #define INSTR_CREATE_cmphi_sve_pred_imm | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| imm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphi, Pd, Pg, Zn, imm), DR_PRED_MASKED) |
Creates a CMPHI instruction.
This macro is used to encode the forms:
* CMPHI <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable) imm The immediate imm
◆ INSTR_CREATE_cmphs_sve_pred
| #define INSTR_CREATE_cmphs_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphs, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a CMPHS instruction.
This macro is used to encode the forms:
* CMPHS <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D * CMPHS <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_cmphs_sve_pred_imm
| #define INSTR_CREATE_cmphs_sve_pred_imm | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| imm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphs, Pd, Pg, Zn, imm), DR_PRED_MASKED) |
Creates a CMPHS instruction.
This macro is used to encode the forms:
* CMPHS <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable) imm The immediate imm
◆ INSTR_CREATE_cmple_sve_pred
| #define INSTR_CREATE_cmple_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmple, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a CMPLE instruction.
This macro is used to encode the forms:
* CMPLE <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_cmple_sve_pred_simm
| #define INSTR_CREATE_cmple_sve_pred_simm | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| simm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmple, Pd, Pg, Zn, simm), DR_PRED_MASKED) |
Creates a CMPLE instruction.
This macro is used to encode the forms:
* CMPLE <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable) simm The signed immediate imm
◆ INSTR_CREATE_cmplo_sve_pred
| #define INSTR_CREATE_cmplo_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplo, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a CMPLO instruction.
This macro is used to encode the forms:
* CMPLO <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_cmplo_sve_pred_imm
| #define INSTR_CREATE_cmplo_sve_pred_imm | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| imm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplo, Pd, Pg, Zn, imm), DR_PRED_MASKED) |
Creates a CMPLO instruction.
This macro is used to encode the forms:
* CMPLO <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable) imm The immediate imm
◆ INSTR_CREATE_cmpls_sve_pred
| #define INSTR_CREATE_cmpls_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpls, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a CMPLS instruction.
This macro is used to encode the forms:
* CMPLS <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_cmpls_sve_pred_imm
| #define INSTR_CREATE_cmpls_sve_pred_imm | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| imm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpls, Pd, Pg, Zn, imm), DR_PRED_MASKED) |
Creates a CMPLS instruction.
This macro is used to encode the forms:
* CMPLS <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable) imm The immediate imm
◆ INSTR_CREATE_cmplt_sve_pred
| #define INSTR_CREATE_cmplt_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplt, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a CMPLT instruction.
This macro is used to encode the forms:
* CMPLT <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_cmplt_sve_pred_simm
| #define INSTR_CREATE_cmplt_sve_pred_simm | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| simm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplt, Pd, Pg, Zn, simm), DR_PRED_MASKED) |
Creates a CMPLT instruction.
This macro is used to encode the forms:
* CMPLT <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable) simm The signed immediate imm
◆ INSTR_CREATE_cmpne_sve_pred
| #define INSTR_CREATE_cmpne_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpne, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a CMPNE instruction.
This macro is used to encode the forms:
* CMPNE <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D * CMPNE <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_cmpne_sve_pred_simm
| #define INSTR_CREATE_cmpne_sve_pred_simm | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| simm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpne, Pd, Pg, Zn, simm), DR_PRED_MASKED) |
Creates a CMPNE instruction.
This macro is used to encode the forms:
* CMPNE <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable) simm The signed immediate imm
◆ INSTR_CREATE_cmtst_vector
| #define INSTR_CREATE_cmtst_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_cmtst, Rd, Rm, Rn, width) |
Creates a CMTST vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_cnot_sve_pred
| #define INSTR_CREATE_cnot_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_cnot, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a CNOT instruction.
This macro is used to encode the forms:
* CNOT <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable)
◆ INSTR_CREATE_cnt_sve_pred [1/2]
| #define INSTR_CREATE_cnt_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_cnt, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a CNT instruction.
This macro is used to encode the forms:
* CNT <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_cnt_sve_pred [2/2]
| #define INSTR_CREATE_cnt_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_cnt, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a CNT instruction.
This macro is used to encode the forms:
* CNT <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_cntb
| #define INSTR_CREATE_cntb | ( | dc, | |
| Rd, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_3src(dc, OP_cntb, Rd, pattern, OPND_CREATE_MUL(), imm) |
Creates a CNTB instruction.
This macro is used to encode the forms:
* CNTB <Xd>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register, X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_cntd
| #define INSTR_CREATE_cntd | ( | dc, | |
| Rd, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_3src(dc, OP_cntd, Rd, pattern, OPND_CREATE_MUL(), imm) |
Creates a CNTD instruction.
This macro is used to encode the forms:
* CNTD <Xd>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register, X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_cnth
| #define INSTR_CREATE_cnth | ( | dc, | |
| Rd, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_3src(dc, OP_cnth, Rd, pattern, OPND_CREATE_MUL(), imm) |
Creates a CNTH instruction.
This macro is used to encode the forms:
* CNTH <Xd>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register, X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_cntp_sve_pred
| #define INSTR_CREATE_cntp_sve_pred | ( | dc, | |
| Rd, | |||
| Pg, | |||
| Pn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_cntp, Rd, Pg, Pn), DR_PRED_MASKED) |
Creates a CNTP instruction.
This macro is used to encode the forms:
* CNTP <Xd>, <Pg>, <Pn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register, X (Extended, 64 bits). Pg The governing predicate register, P (Predicate). Pn The source predicate register, P (Predicate).
◆ INSTR_CREATE_cntw
| #define INSTR_CREATE_cntw | ( | dc, | |
| Rd, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_3src(dc, OP_cntw, Rd, pattern, OPND_CREATE_MUL(), imm) |
Creates a CNTW instruction.
This macro is used to encode the forms:
* CNTW <Xd>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register, X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_compact_sve
| #define INSTR_CREATE_compact_sve | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_compact, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a COMPACT instruction.
This macro is used to encode the forms:
* COMPACT <Zd>.<Ts>, <Pg>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.