dr_ir_macros_aarch64.h File Reference

AArch64-specific instruction creation convenience macros. More...

Macros

#define VECTOR_ELEM_WIDTH_BYTE   0
 
#define VECTOR_ELEM_WIDTH_HALF   1
 
#define VECTOR_ELEM_WIDTH_SINGLE   2
 
#define VECTOR_ELEM_WIDTH_DOUBLE   3
 
#define VECTOR_ELEM_WIDTH_QUAD   4
 
#define OPND_CREATE_BYTE()   OPND_CREATE_INT8(VECTOR_ELEM_WIDTH_BYTE)
 
#define OPND_CREATE_HALF()   OPND_CREATE_INT8(VECTOR_ELEM_WIDTH_HALF)
 
#define OPND_CREATE_SINGLE()   OPND_CREATE_INT8(VECTOR_ELEM_WIDTH_SINGLE)
 
#define OPND_CREATE_DOUBLE()   OPND_CREATE_INT8(VECTOR_ELEM_WIDTH_DOUBLE)
 
#define OPND_CREATE_ABSMEM(addr, size)   opnd_create_rel_addr(addr, size)
 
#define OPND_CREATE_INT(val)   OPND_CREATE_INTPTR(val)
 
#define OPND_CREATE_ZR(reg)   opnd_create_reg(opnd_get_size(reg) == OPSZ_4 ? DR_REG_WZR : DR_REG_XZR)
 
#define OPND_CREATE_LSL()   opnd_add_flags(OPND_CREATE_INT(DR_SHIFT_LSL), DR_OPND_IS_SHIFT)
 
#define OPND_CREATE_MUL()   opnd_add_flags(OPND_CREATE_INT(DR_SHIFT_MUL), DR_OPND_IS_SHIFT)
 
#define INSTR_CREATE_and(dc, rd, rn, rm_or_imm)
 
#define INSTR_CREATE_ands(dc, rd, rn, rm_or_imm)
 
#define INSTR_CREATE_bcond(dc, pc)   instr_create_0dst_1src((dc), OP_bcond, (pc))
 
#define INSTR_CREATE_bl(dc, pc)   instr_create_1dst_1src((dc), OP_bl, opnd_create_reg(DR_REG_X30), (pc))
 
#define INSTR_CREATE_ccmp(dc, Rn, Op, nzcv, cond)   (INSTR_PRED(instr_create_0dst_3src(dc, OP_ccmp, Rn, Op, nzcv), (cond)))
 
#define INSTR_CREATE_ccmn(dc, Rn, Op, nzcv, cond)   (INSTR_PRED(instr_create_0dst_3src(dc, OP_ccmn, Rn, Op, nzcv), (cond)))
 
#define INSTR_CREATE_fmov_general(dc, Rd, Rn)   instr_create_1dst_1src(dc, OP_fmov, Rd, Rn)
 
#define INSTR_CREATE_fmov_upper_vec(dc, Rd, Rn)
 
#define INSTR_CREATE_shadd_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_shadd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sqadd_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sqadd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_srhadd_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_srhadd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_shsub_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_shsub, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sqsub_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sqsub, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_cmgt_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_cmgt, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_cmge_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_cmge, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sshl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sshl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sqshl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sqshl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_srshl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_srshl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sqrshl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sqrshl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_smax_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_smax, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_smin_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_smin, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sabd_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sabd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_saba_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_saba, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_add_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_add, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sve_add_vector(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_add, Rd, Rm, Rn)
 
#define INSTR_CREATE_cmtst_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_cmtst, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_mla_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_4src(dc, OP_mla, Rd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_mul_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_mul, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_smaxp_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_smaxp, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sminp_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sminp, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sqdmulh_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sqdmulh, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_addp_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_addp, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_fmaxnm_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_fmaxnm, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_fmla_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_4src(dc, OP_fmla, Rd, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_fmla_vector_idx(dc, Rd, Rn, Rm, index, Rm_elsz)   instr_create_1dst_5src(dc, OP_fmla, Rd, Rd, Rn, Rm, index, Rm_elsz)
 
#define INSTR_CREATE_fadd_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_fadd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_fmulx_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_fmulx, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_fmulx_vector_idx(dc, Rd, Rn, Rm, index, Rm_elsz)   instr_create_1dst_4src(dc, OP_fmulx, Rd, Rn, Rm, index, Rm_elsz)
 
#define INSTR_CREATE_fmulx(dc, Rd, Rn, Rm)   instr_create_1dst_2src(dc, OP_fmulx, Rd, Rn, Rm)
 
#define INSTR_CREATE_fcmeq_vector_zero(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_3src(dc, OP_fcmeq, Rd, Rn, opnd_create_immed_float(0), Rn_elsz)
 
#define INSTR_CREATE_fcmeq_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_fcmeq, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_fcmeq_zero(dc, Rd, Rn)   instr_create_1dst_2src(dc, OP_fcmeq, Rd, Rn, opnd_create_immed_float(0))
 
#define INSTR_CREATE_fcmeq(dc, Rd, Rn, Rm)   instr_create_1dst_2src(dc, OP_fcmeq, Rd, Rn, Rm)
 
#define INSTR_CREATE_fmlal_vector(dc, Rd, Rn, Rm)   instr_create_1dst_4src(dc, OP_fmlal, Rd, Rd, Rn, Rm, OPND_CREATE_HALF())
 
#define INSTR_CREATE_fmlal_vector_idx(dc, Rd, Rn, Rm, index)   instr_create_1dst_5src(dc, OP_fmlal, Rd, Rd, Rn, Rm, index, OPND_CREATE_HALF())
 
#define INSTR_CREATE_fmax_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_fmax, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_frecpe_vector(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_2src(dc, OP_frecpe, Rd, Rn, Rn_elsz)
 
#define INSTR_CREATE_frecpe(dc, Rd, Rn)   instr_create_1dst_1src(dc, OP_frecpe, Rd, Rn)
 
#define INSTR_CREATE_frecps_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_frecps, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_frecps(dc, Rd, Rn, Rm)   instr_create_1dst_2src(dc, OP_frecps, Rd, Rn, Rm)
 
#define INSTR_CREATE_frsqrte_vector(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_2src(dc, OP_frsqrte, Rd, Rn, Rn_elsz)
 
#define INSTR_CREATE_frsqrte(dc, Rd, Rn)   instr_create_1dst_1src(dc, OP_frsqrte, Rd, Rn)
 
#define INSTR_CREATE_and_vector(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_and, Rd, Rm, Rn)
 
#define INSTR_CREATE_bic_vector(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_bic, Rd, Rm, Rn)
 
#define INSTR_CREATE_fminnm_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_fminnm, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_fmls_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_4src(dc, OP_fmls, Rd, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_fmls_vector_idx(dc, Rd, Rn, Rm, index, Rm_elsz)   instr_create_1dst_5src(dc, OP_fmls, Rd, Rd, Rn, Rm, index, Rm_elsz)
 
#define INSTR_CREATE_fsub_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_fsub, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_fmlsl_vector(dc, Rd, Rm, Rn)   instr_create_1dst_4src(dc, OP_fmlsl, Rd, Rd, Rm, Rn, OPND_CREATE_HALF())
 
#define INSTR_CREATE_fmlsl_vector_idx(dc, Rd, Rm, Rn, index)   instr_create_1dst_5src(dc, OP_fmlsl, Rd, Rd, Rm, Rn, index, OPND_CREATE_HALF())
 
#define INSTR_CREATE_fmin_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_fmin, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_frsqrts_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_frsqrts, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_frsqrts(dc, Rd, Rn, Rm)   instr_create_1dst_2src(dc, OP_frsqrts, Rd, Rn, Rm)
 
#define INSTR_CREATE_orr_vector(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_orr, Rd, Rm, Rn)
 
#define INSTR_CREATE_orn_vector(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_orn, Rd, Rm, Rn)
 
#define INSTR_CREATE_uhadd_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uhadd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uqadd_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uqadd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_urhadd_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_urhadd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uhsub_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uhsub, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uqsub_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uqsub, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_cmhi_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_cmhi, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_cmhs_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_cmhs, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_ushl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_ushl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uqshl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uqshl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_urshl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_urshl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uqrshl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uqrshl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_umax_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_umax, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_umin_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_umin, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uabd_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uabd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uaba_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uaba, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sub_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sub, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_cmeq_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_cmeq, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_mls_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_4src(dc, OP_mls, Rd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_pmul_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_pmul, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_umaxp_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_umaxp, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uminp_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uminp, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sqrdmulh_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sqrdmulh, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sqrdmlsh_scalar(dc, Rd, Rm, Rn)   instr_create_1dst_3src(dc, OP_sqrdmlsh, Rd, Rd, Rm, Rn)
 
#define INSTR_CREATE_sqrdmlsh_scalar_idx(dc, Rd, Rm, Rn, index, elsz)   instr_create_1dst_5src(dc, OP_sqrdmlsh, Rd, Rd, Rm, Rn, index, elsz)
 
#define INSTR_CREATE_sqrdmlsh_vector(dc, Rd, Rm, Rn, elsz)   instr_create_1dst_4src(dc, OP_sqrdmlsh, Rd, Rd, Rm, Rn, elsz)
 
#define INSTR_CREATE_sqrdmlsh_vector_idx(dc, Rd, Rm, Rn, index, elsz)   instr_create_1dst_5src(dc, OP_sqrdmlsh, Rd, Rd, Rm, Rn, index, elsz)
 
#define INSTR_CREATE_fmlal2_vector(dc, Rd, Rn, Rm)   instr_create_1dst_4src(dc, OP_fmlal2, Rd, Rd, Rn, Rm, OPND_CREATE_HALF())
 
#define INSTR_CREATE_fmlal2_vector_idx(dc, Rd, Rn, Rm, index)   instr_create_1dst_5src(dc, OP_fmlal2, Rd, Rd, Rn, Rm, index, OPND_CREATE_HALF())
 
#define INSTR_CREATE_faddp_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_faddp, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_faddp_scalar(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_2src(dc, OP_faddp, Rd, Rn, Rn_elsz)
 
#define INSTR_CREATE_fmul_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_fmul, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_fcmge_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_fcmge, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_fmaxnmp_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_fmaxnmp, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_fmaxnmp_scalar(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_2src(dc, OP_fmaxnmp, Rd, Rn, Rn_elsz)
 
#define INSTR_CREATE_fmaxp_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_fmaxp, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_fmaxp_scalar(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_2src(dc, OP_fmaxp, Rd, Rn, Rn_elsz)
 
#define INSTR_CREATE_facge_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_facge, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_facge(dc, Rd, Rn, Rm)   instr_create_1dst_2src(dc, OP_facge, Rd, Rn, Rm)
 
#define INSTR_CREATE_fcmle_vector_zero(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_3src(dc, OP_fcmle, Rd, Rn, opnd_create_immed_float(0.0), Rn_elsz)
 
#define INSTR_CREATE_fcmle_zero(dc, Rd, Rn)   instr_create_1dst_2src(dc, OP_fcmle, Rd, Rn, opnd_create_immed_float(0.0))
 
#define INSTR_CREATE_fcmlt_vector_zero(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_3src(dc, OP_fcmlt, Rd, Rn, opnd_create_immed_float(0.0), Rn_elsz)
 
#define INSTR_CREATE_fcmlt_zero(dc, Rd, Rn)   instr_create_1dst_2src(dc, OP_fcmlt, Rd, Rn, opnd_create_immed_float(0.0))
 
#define INSTR_CREATE_fdiv_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_fdiv, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_eor_vector(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_eor, Rd, Rm, Rn)
 
#define INSTR_CREATE_bsl_vector(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_bsl, Rd, Rm, Rn)
 
#define INSTR_CREATE_fminnmp_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_fminnmp, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_fminnmp_scalar(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_2src(dc, OP_fminnmp, Rd, Rn, Rn_elsz)
 
#define INSTR_CREATE_fminnmv_vector(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_2src(dc, OP_fminnmv, Rd, Rn, Rn_elsz)
 
#define INSTR_CREATE_fmlsl2_vector(dc, Rd, Rm, Rn)   instr_create_1dst_4src(dc, OP_fmlsl2, Rd, Rd, Rm, Rn, OPND_CREATE_HALF())
 
#define INSTR_CREATE_fmlsl2_vector_idx(dc, Rd, Rm, Rn, index)   instr_create_1dst_5src(dc, OP_fmlsl2, Rd, Rd, Rm, Rn, index, OPND_CREATE_HALF())
 
#define INSTR_CREATE_fabd_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_fabd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_facgt_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_facgt, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_facgt(dc, Rd, Rn, Rm)   instr_create_1dst_2src(dc, OP_facgt, Rd, Rn, Rm)
 
#define INSTR_CREATE_fcmgt_vector_zero(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_3src(dc, OP_fcmgt, Rd, Rn, opnd_create_immed_float(0.0), Rn_elsz)
 
#define INSTR_CREATE_fcmgt_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_fcmgt, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_fcmgt_zero(dc, Rd, Rn)   instr_create_1dst_2src(dc, OP_fcmgt, Rd, Rn, opnd_create_immed_float(0.0))
 
#define INSTR_CREATE_fcmgt(dc, Rd, Rn, Rm)   instr_create_1dst_2src(dc, OP_fcmgt, Rd, Rn, Rm)
 
#define INSTR_CREATE_fminp_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_fminp, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_fminp_scalar(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_2src(dc, OP_fminp, Rd, Rn, Rn_elsz)
 
#define INSTR_CREATE_bit_vector(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_bit, Rd, Rm, Rn)
 
#define INSTR_CREATE_bif_vector(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_bif, Rd, Rm, Rn)
 
#define INSTR_CREATE_fcvtas_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_fcvtas, Rd, Rm, width)
 
#define INSTR_CREATE_fcvtau_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_fcvtau, Rd, Rm, width)
 
#define INSTR_CREATE_fcvtms_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_fcvtms, Rd, Rm, width)
 
#define INSTR_CREATE_fcvtmu_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_fcvtmu, Rd, Rm, width)
 
#define INSTR_CREATE_fcvtns_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_fcvtns, Rd, Rm, width)
 
#define INSTR_CREATE_fcvtnu_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_fcvtnu, Rd, Rm, width)
 
#define INSTR_CREATE_fcvtps_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_fcvtps, Rd, Rm, width)
 
#define INSTR_CREATE_fcvtpu_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_fcvtpu, Rd, Rm, width)
 
#define INSTR_CREATE_fcvtzs_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_fcvtzs, Rd, Rm, width)
 
#define INSTR_CREATE_fcvtzu_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_fcvtzu, Rd, Rm, width)
 
#define INSTR_CREATE_fcvtzu_vector_fixed(dc, Rd, Rm, width, fbits)   instr_create_1dst_3src(dc, OP_fcvtzu, Rd, Rm, width, fbits)
 
#define INSTR_CREATE_sli_vector(dc, Rd, Rn, width, shift)   instr_create_1dst_3src(dc, OP_sli, Rd, Rn, width, shift)
 
#define INSTR_CREATE_uqshrn_vector(dc, Rd, Rn, width, shift)   instr_create_1dst_3src(dc, OP_uqshrn, Rd, Rn, width, shift)
 
#define INSTR_CREATE_ucvtf_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_ucvtf, Rd, Rm, width)
 
#define INSTR_CREATE_ucvtf_vector_fixed(dc, Rd, Rm, width, fbits)   instr_create_1dst_3src(dc, OP_ucvtf, Rd, Rm, width, fbits)
 
#define INSTR_CREATE_scvtf_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_scvtf, Rd, Rm, width)
 
#define INSTR_CREATE_scvtf_vector_fixed(dc, Rd, Rm, width, fbits)   instr_create_1dst_3src(dc, OP_scvtf, Rd, Rm, width, fbits)
 
#define INSTR_CREATE_sha512h(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_4src(dc, OP_sha512h, Rd, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_sha512h2(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_4src(dc, OP_sha512h2, Rd, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_sha512su0(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_3src(dc, OP_sha512su0, Rd, Rd, Rn, Rn_elsz)
 
#define INSTR_CREATE_sha512su1(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_4src(dc, OP_sha512su1, Rd, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_rax1(dc, Rd, Rn, Rm)   instr_create_1dst_3src(dc, OP_rax1, Rd, Rn, Rm, OPND_CREATE_DOUBLE())
 
#define INSTR_CREATE_xar(dc, Rd, Rn, Rm, imm6)   instr_create_1dst_4src(dc, OP_xar, Rd, Rn, Rm, imm6, OPND_CREATE_DOUBLE())
 
#define INSTR_CREATE_ldr_imm(dc, Rt, Xn, Rn, imm)   instr_create_2dst_3src(dc, OP_ldr, Rt, Xn, Rn, Xn, imm)
 
#define INSTR_CREATE_str_imm(dc, Rt, Xt, Xn, imm)   instr_create_2dst_3src(dc, OP_str, Rt, Xn, Xt, Xn, imm)
 
#define INSTR_CREATE_fmov_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fmov, Rd, Rm)
 
#define INSTR_CREATE_fabs_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fabs, Rd, Rm)
 
#define INSTR_CREATE_fneg_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fneg, Rd, Rm)
 
#define INSTR_CREATE_fsqrt_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fsqrt, Rd, Rm)
 
#define INSTR_CREATE_fsqrt_vector(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_2src(dc, OP_fsqrt, Rd, Rn, Rn_elsz)
 
#define INSTR_CREATE_fcvt_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fcvt, Rd, Rm)
 
#define INSTR_CREATE_fcvtas_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fcvtas, Rd, Rm)
 
#define INSTR_CREATE_fcvtau_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fcvtau, Rd, Rm)
 
#define INSTR_CREATE_fcvtms_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fcvtms, Rd, Rm)
 
#define INSTR_CREATE_fcvtmu_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fcvtmu, Rd, Rm)
 
#define INSTR_CREATE_fcvtns_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fcvtns, Rd, Rm)
 
#define INSTR_CREATE_fcvtnu_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fcvtnu, Rd, Rm)
 
#define INSTR_CREATE_fcvtps_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fcvtps, Rd, Rm)
 
#define INSTR_CREATE_fcvtpu_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fcvtpu, Rd, Rm)
 
#define INSTR_CREATE_fcvtzs_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fcvtzs, Rd, Rm)
 
#define INSTR_CREATE_fcvtzs_scalar_fixed(dc, Rd, Rm, fbits)   instr_create_1dst_2src(dc, OP_fcvtzs, Rd, Rm, fbits)
 
#define INSTR_CREATE_fcvtzu_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_fcvtzu, Rd, Rm)
 
#define INSTR_CREATE_fcvtzu_scalar_fixed(dc, Rd, Rm, fbits)   instr_create_1dst_2src(dc, OP_fcvtzu, Rd, Rm, fbits)
 
#define INSTR_CREATE_ucvtf_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_ucvtf, Rd, Rm)
 
#define INSTR_CREATE_ucvtf_scalar_fixed(dc, Rd, Rm, fbits)   instr_create_1dst_2src(dc, OP_ucvtf, Rd, Rm, fbits)
 
#define INSTR_CREATE_scvtf_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_scvtf, Rd, Rm)
 
#define INSTR_CREATE_scvtf_scalar_fixed(dc, Rd, Rm, fbits)   instr_create_1dst_2src(dc, OP_scvtf, Rd, Rm, fbits)
 
#define INSTR_CREATE_frintn_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_frintn, Rd, Rm)
 
#define INSTR_CREATE_frintn_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_frintn, Rd, Rm, width)
 
#define INSTR_CREATE_frintp_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_frintp, Rd, Rm)
 
#define INSTR_CREATE_frintp_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_frintp, Rd, Rm, width)
 
#define INSTR_CREATE_frintm_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_frintm, Rd, Rm)
 
#define INSTR_CREATE_frintm_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_frintm, Rd, Rm, width)
 
#define INSTR_CREATE_frintz_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_frintz, Rd, Rm)
 
#define INSTR_CREATE_frintz_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_frintz, Rd, Rm, width)
 
#define INSTR_CREATE_frinta_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_frinta, Rd, Rm)
 
#define INSTR_CREATE_frinta_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_frinta, Rd, Rm, width)
 
#define INSTR_CREATE_frintx_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_frintx, Rd, Rm)
 
#define INSTR_CREATE_frintx_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_frintx, Rd, Rm, width)
 
#define INSTR_CREATE_frinti_scalar(dc, Rd, Rm)   instr_create_1dst_1src(dc, OP_frinti, Rd, Rm)
 
#define INSTR_CREATE_frinti_vector(dc, Rd, Rm, width)   instr_create_1dst_2src(dc, OP_frinti, Rd, Rm, width)
 
#define INSTR_CREATE_ldpsw(dc, Xt1, Xt2, Xn, Xr, imm)   instr_create_3dst_3src(dc, OP_ldpsw, Xt1, Xt2, Xn, Xr, Xn, imm)
 
#define INSTR_CREATE_ldpsw_2(dc, Xt1, Xt2, Xn)   instr_create_2dst_1src(dc, OP_ldpsw, Xt1, Xt2, Xn)
 
#define INSTR_CREATE_fmul_scalar(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_fmul, Rd, Rm, Rn)
 
#define INSTR_CREATE_fdiv_scalar(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_fdiv, Rd, Rm, Rn)
 
#define INSTR_CREATE_fadd_scalar(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_fadd, Rd, Rm, Rn)
 
#define INSTR_CREATE_fsub_scalar(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_fsub, Rd, Rm, Rn)
 
#define INSTR_CREATE_fmax_scalar(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_fmax, Rd, Rm, Rn)
 
#define INSTR_CREATE_fmin_scalar(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_fmin, Rd, Rm, Rn)
 
#define INSTR_CREATE_fmaxnm_scalar(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_fmaxnm, Rd, Rm, Rn)
 
#define INSTR_CREATE_fminnm_scalar(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_fminnm, Rd, Rm, Rn)
 
#define INSTR_CREATE_fnmul_scalar(dc, Rd, Rm, Rn)   instr_create_1dst_2src(dc, OP_fnmul, Rd, Rm, Rn)
 
#define INSTR_CREATE_fmadd_scalar(dc, Rd, Rm, Rn, Ra)   instr_create_1dst_3src(dc, OP_fmadd, Rd, Rm, Rn, Ra)
 
#define INSTR_CREATE_fmsub_scalar(dc, Rd, Rm, Rn, Ra)   instr_create_1dst_3src(dc, OP_fmsub, Rd, Rm, Rn, Ra)
 
#define INSTR_CREATE_fnmadd_scalar(dc, Rd, Rm, Rn, Ra)   instr_create_1dst_3src(dc, OP_fnmadd, Rd, Rm, Rn, Ra)
 
#define INSTR_CREATE_fnmsub_scalar(dc, Rd, Rm, Rn, Ra)   instr_create_1dst_3src(dc, OP_fnmsub, Rd, Rm, Rn, Ra)
 
#define INSTR_CREATE_ld2_multi_2(dc, Vt1, Vt2, Xn, disp, offset, elsz)   instr_create_3dst_4src(dc, OP_ld2, Vt1, Vt2, Xn, disp, Xn, offset, elsz)
 
#define INSTR_CREATE_ld2(dc, Vt1, Vt2, Xn, index, elsz)   instr_create_2dst_3src(dc, OP_ld2, Vt1, Vt2, Xn, index, elsz)
 
#define INSTR_CREATE_ld2_2(dc, Vt1, Vt2, Xn, Xnd, index, offset, elsz)   instr_create_3dst_5src(dc, OP_ld2, Vt1, Vt2, Xn, Xnd, index, Xn, offset, elsz)
 
#define INSTR_CREATE_ld2r(dc, Vt1, Vt2, Xn, elsz)   instr_create_2dst_2src(dc, OP_ld2r, Vt1, Vt2, Xn, elsz)
 
#define INSTR_CREATE_ld2r_2(dc, Vt1, Vt2, Xn, Xnd, Xm, elsz)   instr_create_3dst_4src(dc, OP_ld2r, Vt1, Vt2, Xn, Xnd, Xn, Xm, elsz)
 
#define INSTR_CREATE_ld3_multi(dc, Vt1, Vt2, Vt3, Xn, elsz)   instr_create_3dst_2src(dc, OP_ld3, Vt1, Vt2, Vt3, Xn, elsz)
 
#define INSTR_CREATE_ld3_multi_2(dc, Vt1, Vt2, Vt3, Xn, Xnd, Xm, elsz)   instr_create_4dst_4src(dc, OP_ld3, Vt1, Vt2, Vt3, Xn, Xnd, Xn, Xm, elsz)
 
#define INSTR_CREATE_ld3(dc, Vt1, Vt2, Vt3, Xn, index, elsz)   instr_create_3dst_3src(dc, OP_ld3, Vt1, Vt2, Vt3, Xn, index, elsz)
 
#define INSTR_CREATE_ld3_2(dc, Vt1, Vt2, Vt3, Xn, Xnd, index, offset, elsz)   instr_create_4dst_5src(dc, OP_ld3, Vt1, Vt2, Vt3, Xn, Xnd, index, Xn, offset, elsz)
 
#define INSTR_CREATE_ld3r(dc, Vt1, Vt2, Vt3, Xn, elsz)   instr_create_3dst_2src(dc, OP_ld3r, Vt1, Vt2, Vt3, Xn, elsz)
 
#define INSTR_CREATE_ld3r_2(dc, Vt1, Vt2, Vt3, Xn, Xnd, offset, elsz)   instr_create_4dst_4src(dc, OP_ld3r, Vt1, Vt2, Vt3, Xn, Xnd, Xn, offset, elsz)
 
#define INSTR_CREATE_ld4_multi(dc, Vt1, Vt2, Vt3, Vt4, Xn, elsz)   instr_create_4dst_2src(dc, OP_ld4, Vt1, Vt2, Vt3, Vt4, Xn, elsz)
 
#define INSTR_CREATE_ld4_multi_2(dc, Vt1, Vt2, Vt3, Vt4, Xn, Xnd, offset, elsz)   instr_create_5dst_4src(dc, OP_ld4, Vt1, Vt2, Vt3, Vt4, Xn, Xnd, Xn, offset, elsz)
 
#define INSTR_CREATE_ld4(dc, Vt1, Vt2, Vt3, Vt4, Xn, index, elsz)   instr_create_4dst_3src(dc, OP_ld4, Vt1, Vt2, Vt3, Vt4, Xn, index, elsz)
 
#define INSTR_CREATE_ld4_2(dc, Vt1, Vt2, Vt3, Vt4, Xn, Xnd, index, offset, elsz)
 
#define INSTR_CREATE_ld4r(dc, Vt1, Vt2, Vt3, Vt4, Xn, elsz)   instr_create_4dst_2src(dc, OP_ld4r, Vt1, Vt2, Vt3, Vt4, Xn, elsz)
 
#define INSTR_CREATE_ld4r_2(dc, Vt1, Vt2, Vt3, Vt4, Xn, Xnd, offset, elsz)   instr_create_5dst_4src(dc, OP_ld4r, Vt1, Vt2, Vt3, Vt4, Xn, Xnd, Xn, offset, elsz)
 
#define INSTR_CREATE_ld1_multi_1(dc, q, r, s)   instr_create_1dst_2src(dc, OP_ld1, q, r, s)
 
#define INSTR_CREATE_st1_multi_1(dc, r, q, s)   instr_create_1dst_2src(dc, OP_st1, r, q, s)
 
#define INSTR_CREATE_saddl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_saddl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_saddl2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_saddl2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_saddw_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_saddw, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_saddw2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_saddw2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_ssubl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_ssubl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_ssubl2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_ssubl2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_ssubw_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_ssubw, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_ssubw2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_ssubw2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_addhn_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_addhn, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_addhn2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_addhn2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sabal_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sabal, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sabal2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sabal2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_subhn_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_subhn, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_subhn2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_subhn2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sabdl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sabdl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sabdl2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sabdl2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_smlal_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_smlal, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_smlal2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_smlal2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sqdmlal_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sqdmlal, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sqdmlal2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sqdmlal2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_smlsl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_smlsl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_smlsl2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_smlsl2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sqdmlsl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sqdmlsl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sqdmlsl2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sqdmlsl2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_smull_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_smull, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_smull2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_smull2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sqdmull_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sqdmull, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_sqdmull2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_sqdmull2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_pmull_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_pmull, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_pmull2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_pmull2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uaddl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uaddl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uaddl2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uaddl2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uaddw_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uaddw, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uaddw2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uaddw2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_usubl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_usubl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_usubl2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_usubl2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_usubw_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_usubw, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_usubw2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_usubw2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_raddhn_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_raddhn, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_raddhn2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_raddhn2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uabal_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uabal, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uabal2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uabal2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_rsubhn_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_rsubhn, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_rsubhn2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_rsubhn2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uabdl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uabdl, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_uabdl2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_uabdl2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_umlal_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_4src(dc, OP_umlal, Rd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_umlal2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_4src(dc, OP_umlal2, Rd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_umlsl_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_4src(dc, OP_umlsl, Rd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_umlsl2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_4src(dc, OP_umlsl2, Rd, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_umull_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_umull, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_umull2_vector(dc, Rd, Rm, Rn, width)   instr_create_1dst_3src(dc, OP_umull2, Rd, Rm, Rn, width)
 
#define INSTR_CREATE_fmov_vector_imm(dc, Rd, f, width)   instr_create_1dst_2src(dc, OP_fmov, Rd, f, width)
 
#define INSTR_CREATE_fmov_scalar_imm(dc, Rd, f)   instr_create_1dst_1src(dc, OP_fmov, Rd, f)
 
#define INSTR_CREATE_ldlar(dc, Rt, Rn)   instr_create_1dst_1src(dc, OP_ldlar, Rt, Rn)
 
#define INSTR_CREATE_ldlarb(dc, Rt, Rn)   instr_create_1dst_1src(dc, OP_ldlarb, Rt, Rn)
 
#define INSTR_CREATE_ldlarh(dc, Rt, Rn)   instr_create_1dst_1src(dc, OP_ldlarh, Rt, Rn)
 
#define INSTR_CREATE_stllr(dc, Rt, Rn)   instr_create_1dst_1src(dc, OP_stllr, Rt, Rn)
 
#define INSTR_CREATE_stllrb(dc, Rt, Rn)   instr_create_1dst_1src(dc, OP_stllrb, Rt, Rn)
 
#define INSTR_CREATE_stllrh(dc, Rt, Rn)   instr_create_1dst_1src(dc, OP_stllrh, Rt, Rn)
 
#define INSTR_CREATE_ldapr(dc, Rt, mem)   instr_create_1dst_1src((dc), OP_ldapr, (Rt), (mem))
 
#define INSTR_CREATE_ldaprb(dc, Rt, mem)   instr_create_1dst_1src((dc), OP_ldaprb, (Rt), (mem))
 
#define INSTR_CREATE_ldaprh(dc, Rt, mem)   instr_create_1dst_1src((dc), OP_ldaprh, (Rt), (mem))
 
#define INSTR_CREATE_sm3partw1_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_sm3partw1, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_sm3partw2_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_sm3partw2, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_sm3ss1_vector(dc, Rd, Rn, Rm, Ra, Ra_elsz)   instr_create_1dst_4src(dc, OP_sm3ss1, Rd, Rn, Rm, Ra, Ra_elsz)
 
#define INSTR_CREATE_sm3tt1a_vector_indexed(dc, Rd, Rn, Rm, imm2, Rm_elsz)   instr_create_1dst_4src(dc, OP_sm3tt1a, Rd, Rn, Rm, imm2, Rm_elsz)
 
#define INSTR_CREATE_sm3tt1b_vector_indexed(dc, Rd, Rn, Rm, imm2, Rm_elsz)   instr_create_1dst_4src(dc, OP_sm3tt1b, Rd, Rn, Rm, imm2, Rm_elsz)
 
#define INSTR_CREATE_sm3tt2a_vector_indexed(dc, Rd, Rn, Rm, imm2, Rm_elsz)   instr_create_1dst_4src(dc, OP_sm3tt2a, Rd, Rn, Rm, imm2, Rm_elsz)
 
#define INSTR_CREATE_sm3tt2b_vector_indexed(dc, Rd, Rn, Rm, imm2, Rm_elsz)   instr_create_1dst_4src(dc, OP_sm3tt2b, Rd, Rn, Rm, imm2, Rm_elsz)
 
#define INSTR_CREATE_sm4e_vector(dc, Rd, Rn, Rn_elsz)   instr_create_1dst_2src(dc, OP_sm4e, Rd, Rn, Rn_elsz)
 
#define INSTR_CREATE_sm4ekey_vector(dc, Rd, Rn, Rm, Rm_elsz)   instr_create_1dst_3src(dc, OP_sm4ekey, Rd, Rn, Rm, Rm_elsz)
 
#define INSTR_CREATE_bcax(dc, Rd, Rn, Rm, Ra)   instr_create_1dst_4src(dc, OP_bcax, Rd, Rn, Rm, Ra, OPND_CREATE_BYTE())
 
#define INSTR_CREATE_eor3(dc, Rd, Rn, Rm, Ra)   instr_create_1dst_4src(dc, OP_eor3, Rd, Rn, Rm, Ra, OPND_CREATE_BYTE())
 
#define INSTR_CREATE_esb(dc)   instr_create_0dst_0src(dc, OP_esb)
 
#define INSTR_CREATE_psb_csync(dc)   instr_create_0dst_0src(dc, OP_psb)
 
#define INSTR_CREATE_fccmp(dc, Rn, Rm, nzcv, condition_code)   INSTR_PRED(instr_create_0dst_3src(dc, OP_fccmp, Rn, Rm, nzcv), (condition_code))
 
#define INSTR_CREATE_fccmpe(dc, Rn, Rm, nzcv, condition_code)   INSTR_PRED(instr_create_0dst_3src(dc, OP_fccmpe, Rn, Rm, nzcv), (condition_code))
 
#define INSTR_CREATE_fcsel(dc, Rd, Rn, Rm, condition_code)   INSTR_PRED(instr_create_1dst_2src(dc, OP_fcsel, Rd, Rn, Rm), (condition_code))
 
#define INSTR_CREATE_fcmp_zero(dc, Rn)   instr_create_0dst_2src(dc, OP_fcmp, Rn, opnd_create_immed_float(0.0))
 
#define INSTR_CREATE_fcmp(dc, Rn, Rm)   instr_create_0dst_2src(dc, OP_fcmp, Rn, Rm)
 
#define INSTR_CREATE_fcmpe_zero(dc, Rn)   instr_create_0dst_2src(dc, OP_fcmpe, Rn, opnd_create_immed_float(0.0))
 
#define INSTR_CREATE_fcmpe(dc, Rn, Rm)   instr_create_0dst_2src(dc, OP_fcmpe, Rn, Rm)
 
#define INSTR_CREATE_sdot_vector(dc, Rd, Rn, Rm)   instr_create_1dst_4src(dc, OP_sdot, Rd, Rd, Rn, Rm, OPND_CREATE_BYTE())
 
#define INSTR_CREATE_sdot_vector_indexed(dc, Rd, Rn, Rm, index)   instr_create_1dst_5src(dc, OP_sdot, Rd, Rd, Rn, Rm, index, OPND_CREATE_BYTE())
 
#define INSTR_CREATE_udot_vector(dc, Rd, Rn, Rm)   instr_create_1dst_4src(dc, OP_udot, Rd, Rd, Rn, Rm, OPND_CREATE_BYTE())
 
#define INSTR_CREATE_udot_vector_indexed(dc, Rd, Rn, Rm, index)   instr_create_1dst_5src(dc, OP_udot, Rd, Rd, Rn, Rm, index, OPND_CREATE_BYTE())
 
#define INSTR_CREATE_xpaci(dc, Rd)   instr_create_0dst_1src((dc), OP_xpaci, (Rd))
 
#define INSTR_CREATE_orr_sve_pred(dc, Zd, Pg, Zd_, Zm, width)   instr_create_1dst_4src(dc, OP_orr, Zd, Pg, Zd_, Zm, width)
 
#define INSTR_CREATE_eor_sve_pred(dc, Zd, Pg, Zd_, Zm, width)   instr_create_1dst_4src(dc, OP_eor, Zd, Pg, Zd_, Zm, width)
 
#define INSTR_CREATE_and_sve_pred(dc, Zd, Pg, Zd_, Zm, width)   instr_create_1dst_4src(dc, OP_and, Zd, Pg, Zd_, Zm, width)
 
#define INSTR_CREATE_bic_sve_pred(dc, Zd, Pg, Zd_, Zm, width)   instr_create_1dst_4src(dc, OP_bic, Zd, Pg, Zd_, Zm, width)
 
#define INSTR_CREATE_zip2_vector(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_zip2, Zd, Zn, Zm)
 
#define INSTR_CREATE_movprfx_vector(dc, Zd, Zn)   instr_create_1dst_1src(dc, OP_movprfx, Zd, Zn)
 
#define INSTR_CREATE_movprfx_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_movprfx, Zd, Pg, Zn)
 
#define INSTR_CREATE_sqadd_sve_shift(dc, Zdn, imm, shift)   instr_create_1dst_4src(dc, OP_sqadd, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift)
 
#define INSTR_CREATE_sqadd_sve(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_sqadd, Zd, Zn, Zm)
 
#define INSTR_CREATE_sqsub_sve_shift(dc, Zdn, imm, shift)   instr_create_1dst_4src(dc, OP_sqsub, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift)
 
#define INSTR_CREATE_sqsub_sve(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_sqsub, Zd, Zn, Zm)
 
#define INSTR_CREATE_sub_sve_pred(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_sub, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_sub_sve_shift(dc, Zdn, imm, shift)   instr_create_1dst_4src(dc, OP_sub, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift)
 
#define INSTR_CREATE_sub_sve(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_sub, Zd, Zn, Zm)
 
#define INSTR_CREATE_subr_sve_pred(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_subr, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_subr_sve_shift(dc, Zdn, imm, shift)   instr_create_1dst_4src(dc, OP_subr, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift)
 
#define INSTR_CREATE_uqadd_sve_shift(dc, Zdn, imm, shift)   instr_create_1dst_4src(dc, OP_uqadd, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift)
 
#define INSTR_CREATE_uqadd_sve(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_uqadd, Zd, Zn, Zm)
 
#define INSTR_CREATE_uqsub_sve_shift(dc, Zdn, imm, shift)   instr_create_1dst_4src(dc, OP_uqsub, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift)
 
#define INSTR_CREATE_uqsub_sve(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_uqsub, Zd, Zn, Zm)
 
#define INSTR_CREATE_add_sve_pred(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_add, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_add_sve_shift(dc, Zdn, imm, shift)   instr_create_1dst_4src(dc, OP_add, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift)
 
#define INSTR_CREATE_add_sve(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_add, Zd, Zn, Zm)
 
#define INSTR_CREATE_cpy_sve_shift_pred(dc, Zd, Pg, simm, shift)   instr_create_1dst_4src(dc, OP_cpy, Zd, Pg, simm, OPND_CREATE_LSL(), shift)
 
#define INSTR_CREATE_cpy_sve_pred(dc, Zd, Pg, Rn_or_Vn)   instr_create_1dst_2src(dc, OP_cpy, Zd, Pg, Rn_or_Vn)
 
#define INSTR_CREATE_ptest_sve_pred(dc, Pg, Pn)   instr_create_0dst_2src(dc, OP_ptest, Pg, Pn)
 
#define INSTR_CREATE_mad_sve_pred(dc, Zdn, Pg, Zm, Za)   instr_create_1dst_4src(dc, OP_mad, Zdn, Pg, Zdn, Zm, Za)
 
#define INSTR_CREATE_mla_sve_pred(dc, Zda, Pg, Zn, Zm)   instr_create_1dst_4src(dc, OP_mla, Zda, Pg, Zn, Zm, Zda)
 
#define INSTR_CREATE_mls_sve_pred(dc, Zda, Pg, Zn, Zm)   instr_create_1dst_4src(dc, OP_mls, Zda, Pg, Zn, Zm, Zda)
 
#define INSTR_CREATE_msb_sve_pred(dc, Zdn, Pg, Zm, Za)   instr_create_1dst_4src(dc, OP_msb, Zdn, Pg, Zdn, Zm, Za)
 
#define INSTR_CREATE_mul_sve_pred(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_mul, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_mul_sve(dc, Zdn, simm)   instr_create_1dst_2src(dc, OP_mul, Zdn, Zdn, simm)
 
#define INSTR_CREATE_smulh_sve_pred(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_smulh, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_umulh_sve_pred(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_umulh, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_fexpa_sve(dc, Zd, Zn)   instr_create_1dst_1src(dc, OP_fexpa, Zd, Zn)
 
#define INSTR_CREATE_ftmad_sve(dc, Zdn, Zm, imm)   instr_create_1dst_3src(dc, OP_ftmad, Zdn, Zdn, Zm, imm)
 
#define INSTR_CREATE_ftsmul_sve(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_ftsmul, Zd, Zn, Zm)
 
#define INSTR_CREATE_ftssel_sve(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_ftssel, Zd, Zn, Zm)
 
#define INSTR_CREATE_abs_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_abs, Zd, Pg, Zn)
 
#define INSTR_CREATE_cnot_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_cnot, Zd, Pg, Zn)
 
#define INSTR_CREATE_neg_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_neg, Zd, Pg, Zn)
 
#define INSTR_CREATE_sabd_sve_pred(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_sabd, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_smax_sve_pred(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_smax, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_smax_sve(dc, Zdn, simm)   instr_create_1dst_2src(dc, OP_smax, Zdn, Zdn, simm)
 
#define INSTR_CREATE_smin_sve_pred(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_smin, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_smin_sve(dc, Zdn, simm)   instr_create_1dst_2src(dc, OP_smin, Zdn, Zdn, simm)
 
#define INSTR_CREATE_uabd_sve_pred(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_uabd, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_facge_sve_pred(dc, Pd, Pg, Zn, Zm)   instr_create_1dst_3src(dc, OP_facge, Pd, Pg, Zn, Zm)
 
#define INSTR_CREATE_facgt_sve_pred(dc, Pd, Pg, Zn, Zm)   instr_create_1dst_3src(dc, OP_facgt, Pd, Pg, Zn, Zm)
 
#define INSTR_CREATE_sdiv_sve_pred(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_sdiv, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_sdivr_sve_pred(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_sdivr, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_udiv_sve_pred(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_udiv, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_udivr_sve_pred(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_udivr, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_umax_sve_pred(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_umax, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_umax_sve(dc, Zdn, imm)   instr_create_1dst_2src(dc, OP_umax, Zdn, Zdn, imm)
 
#define INSTR_CREATE_umin_sve_pred(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_umin, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_umin_sve(dc, Zdn, imm)   instr_create_1dst_2src(dc, OP_umin, Zdn, Zdn, imm)
 
#define INSTR_CREATE_sxtb_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_sxtb, Zd, Pg, Zn)
 
#define INSTR_CREATE_sxth_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_sxth, Zd, Pg, Zn)
 
#define INSTR_CREATE_sxtw_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_sxtw, Zd, Pg, Zn)
 
#define INSTR_CREATE_uxtb_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_uxtb, Zd, Pg, Zn)
 
#define INSTR_CREATE_uxth_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_uxth, Zd, Pg, Zn)
 
#define INSTR_CREATE_uxtw_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_uxtw, Zd, Pg, Zn)
 
#define INSTR_CREATE_fcmeq_sve_zero_pred(dc, Pd, Pg, Zn)   instr_create_1dst_3src(dc, OP_fcmeq, Pd, Pg, Zn, opnd_create_immed_float(0.0))
 
#define INSTR_CREATE_fcmeq_sve_pred(dc, Pd, Pg, Zn, Zm)   instr_create_1dst_3src(dc, OP_fcmeq, Pd, Pg, Zn, Zm)
 
#define INSTR_CREATE_fcmge_sve_zero_pred(dc, Pd, Pg, Zn)   instr_create_1dst_3src(dc, OP_fcmge, Pd, Pg, Zn, opnd_create_immed_float(0.0))
 
#define INSTR_CREATE_fcmge_sve_pred(dc, Pd, Pg, Zn, Zm)   instr_create_1dst_3src(dc, OP_fcmge, Pd, Pg, Zn, Zm)
 
#define INSTR_CREATE_fcmgt_sve_zero_pred(dc, Pd, Pg, Zn)   instr_create_1dst_3src(dc, OP_fcmgt, Pd, Pg, Zn, opnd_create_immed_float(0.0))
 
#define INSTR_CREATE_fcmgt_sve_pred(dc, Pd, Pg, Zn, Zm)   instr_create_1dst_3src(dc, OP_fcmgt, Pd, Pg, Zn, Zm)
 
#define INSTR_CREATE_fcmle_sve_zero_pred(dc, Pd, Pg, Zn)   instr_create_1dst_3src(dc, OP_fcmle, Pd, Pg, Zn, opnd_create_immed_float(0.0))
 
#define INSTR_CREATE_fcmlt_sve_zero_pred(dc, Pd, Pg, Zn)   instr_create_1dst_3src(dc, OP_fcmlt, Pd, Pg, Zn, opnd_create_immed_float(0.0))
 
#define INSTR_CREATE_fcmne_sve_zero_pred(dc, Pd, Pg, Zn)   instr_create_1dst_3src(dc, OP_fcmne, Pd, Pg, Zn, opnd_create_immed_float(0.0))
 
#define INSTR_CREATE_fcmne_sve_pred(dc, Pd, Pg, Zn, Zm)   instr_create_1dst_3src(dc, OP_fcmne, Pd, Pg, Zn, Zm)
 
#define INSTR_CREATE_fcmuo_sve_pred(dc, Pd, Pg, Zn, Zm)   instr_create_1dst_3src(dc, OP_fcmuo, Pd, Pg, Zn, Zm)
 
#define INSTR_CREATE_fcmle_sve_pred(dc, Pd, Pg, Zm, Zn)   instr_create_1dst_3src(dc, OP_fcmle, Pd, Pg, Zm, Zn)
 
#define INSTR_CREATE_fcmlt_sve_pred(dc, Pd, Pg, Zm, Zn)   instr_create_1dst_3src(dc, OP_fcmlt, Pd, Pg, Zm, Zn)
 
#define INSTR_CREATE_cmpeq_sve_pred_simm(dc, Pd, Pg, Zn, simm)   instr_create_1dst_3src(dc, OP_cmpeq, Pd, Pg, Zn, simm)
 
#define INSTR_CREATE_cmpeq_sve_pred(dc, Pd, Pg, Zn, Zm)   instr_create_1dst_3src(dc, OP_cmpeq, Pd, Pg, Zn, Zm)
 
#define INSTR_CREATE_cmpge_sve_pred_simm(dc, Pd, Pg, Zn, simm)   instr_create_1dst_3src(dc, OP_cmpge, Pd, Pg, Zn, simm)
 
#define INSTR_CREATE_cmpge_sve_pred(dc, Pd, Pg, Zn, Zm)   instr_create_1dst_3src(dc, OP_cmpge, Pd, Pg, Zn, Zm)
 
#define INSTR_CREATE_cmpgt_sve_pred_simm(dc, Pd, Pg, Zn, simm)   instr_create_1dst_3src(dc, OP_cmpgt, Pd, Pg, Zn, simm)
 
#define INSTR_CREATE_cmpgt_sve_pred(dc, Pd, Pg, Zn, Zm)   instr_create_1dst_3src(dc, OP_cmpgt, Pd, Pg, Zn, Zm)
 
#define INSTR_CREATE_cmphi_sve_pred_imm(dc, Pd, Pg, Zn, imm)   instr_create_1dst_3src(dc, OP_cmphi, Pd, Pg, Zn, imm)
 
#define INSTR_CREATE_cmphi_sve_pred(dc, Pd, Pg, Zn, Zm)   instr_create_1dst_3src(dc, OP_cmphi, Pd, Pg, Zn, Zm)
 
#define INSTR_CREATE_cmphs_sve_pred_imm(dc, Pd, Pg, Zn, imm)   instr_create_1dst_3src(dc, OP_cmphs, Pd, Pg, Zn, imm)
 
#define INSTR_CREATE_cmphs_sve_pred(dc, Pd, Pg, Zn, Zm)   instr_create_1dst_3src(dc, OP_cmphs, Pd, Pg, Zn, Zm)
 
#define INSTR_CREATE_cmple_sve_pred_simm(dc, Pd, Pg, Zn, simm)   instr_create_1dst_3src(dc, OP_cmple, Pd, Pg, Zn, simm)
 
#define INSTR_CREATE_cmple_sve_pred(dc, Pd, Pg, Zn, Zm)   instr_create_1dst_3src(dc, OP_cmple, Pd, Pg, Zn, Zm)
 
#define INSTR_CREATE_cmplo_sve_pred_imm(dc, Pd, Pg, Zn, imm)   instr_create_1dst_3src(dc, OP_cmplo, Pd, Pg, Zn, imm)
 
#define INSTR_CREATE_cmplo_sve_pred(dc, Pd, Pg, Zn, Zm)   instr_create_1dst_3src(dc, OP_cmplo, Pd, Pg, Zn, Zm)
 
#define INSTR_CREATE_cmpls_sve_pred_imm(dc, Pd, Pg, Zn, imm)   instr_create_1dst_3src(dc, OP_cmpls, Pd, Pg, Zn, imm)
 
#define INSTR_CREATE_cmpls_sve_pred(dc, Pd, Pg, Zn, Zm)   instr_create_1dst_3src(dc, OP_cmpls, Pd, Pg, Zn, Zm)
 
#define INSTR_CREATE_cmplt_sve_pred_simm(dc, Pd, Pg, Zn, simm)   instr_create_1dst_3src(dc, OP_cmplt, Pd, Pg, Zn, simm)
 
#define INSTR_CREATE_cmplt_sve_pred(dc, Pd, Pg, Zn, Zm)   instr_create_1dst_3src(dc, OP_cmplt, Pd, Pg, Zn, Zm)
 
#define INSTR_CREATE_cmpne_sve_pred_simm(dc, Pd, Pg, Zn, simm)   instr_create_1dst_3src(dc, OP_cmpne, Pd, Pg, Zn, simm)
 
#define INSTR_CREATE_cmpne_sve_pred(dc, Pd, Pg, Zn, Zm)   instr_create_1dst_3src(dc, OP_cmpne, Pd, Pg, Zn, Zm)
 
#define INSTR_CREATE_setffr_sve(dc)   instr_create_0dst_0src(dc, OP_setffr)
 
#define INSTR_CREATE_rdffr_sve(dc, Pd)   instr_create_1dst_0src(dc, OP_rdffr, Pd)
 
#define INSTR_CREATE_rdffr_sve_pred(dc, Pd, Pg)   instr_create_1dst_1src(dc, OP_rdffr, Pd, Pg)
 
#define INSTR_CREATE_rdffrs_sve_pred(dc, Pd, Pg)   instr_create_1dst_1src(dc, OP_rdffrs, Pd, Pg)
 
#define INSTR_CREATE_wrffr_sve(dc, Pn)   instr_create_0dst_1src(dc, OP_wrffr, Pn)
 
#define INSTR_CREATE_cntp_sve_pred(dc, Rd, Pg, Pn)   instr_create_1dst_2src(dc, OP_cntp, Rd, Pg, Pn)
 
#define INSTR_CREATE_decp_sve(dc, Rdn, Pm)   instr_create_1dst_2src(dc, OP_decp, Rdn, Pm, Rdn)
 
#define INSTR_CREATE_decp_sve_vector(dc, Zdn, Pm)   instr_create_1dst_2src(dc, OP_decp, Zdn, Pm, Zdn)
 
#define INSTR_CREATE_incp_sve(dc, Rdn, Pm)   instr_create_1dst_2src(dc, OP_incp, Rdn, Pm, Rdn)
 
#define INSTR_CREATE_incp_sve_vector(dc, Zdn, Pm)   instr_create_1dst_2src(dc, OP_incp, Zdn, Pm, Zdn)
 
#define INSTR_CREATE_sqdecp_sve(dc, Rdn, Pm)   instr_create_1dst_2src(dc, OP_sqdecp, Rdn, Pm, Rdn)
 
#define INSTR_CREATE_sqdecp_sve_wide(dc, Rdn, Pm)
 
#define INSTR_CREATE_sqdecp_sve_vector(dc, Zdn, Pm)   instr_create_1dst_2src(dc, OP_sqdecp, Zdn, Pm, Zdn)
 
#define INSTR_CREATE_sqincp_sve(dc, Rdn, Pm)   instr_create_1dst_2src(dc, OP_sqincp, Rdn, Pm, Rdn)
 
#define INSTR_CREATE_sqincp_sve_wide(dc, Rdn, Pm)
 
#define INSTR_CREATE_sqincp_sve_vector(dc, Zdn, Pm)   instr_create_1dst_2src(dc, OP_sqincp, Zdn, Pm, Zdn)
 
#define INSTR_CREATE_uqdecp_sve(dc, Rdn, Pm)   instr_create_1dst_2src(dc, OP_uqdecp, Rdn, Pm, Rdn)
 
#define INSTR_CREATE_uqdecp_sve_vector(dc, Zdn, Pm)   instr_create_1dst_2src(dc, OP_uqdecp, Zdn, Pm, Zdn)
 
#define INSTR_CREATE_uqincp_sve(dc, Rdn, Pm)   instr_create_1dst_2src(dc, OP_uqincp, Rdn, Pm, Rdn)
 
#define INSTR_CREATE_uqincp_sve_vector(dc, Zdn, Pm)   instr_create_1dst_2src(dc, OP_uqincp, Zdn, Pm, Zdn)
 
#define INSTR_CREATE_and_sve_imm(dc, Zdn, imm)   instr_create_1dst_2src(dc, OP_and, Zdn, Zdn, imm)
 
#define INSTR_CREATE_bic_sve_imm(dc, Zdn, imm)   instr_create_1dst_2src(dc, OP_and, Zdn, Zdn, opnd_invert_immed_int(imm))
 
#define INSTR_CREATE_eor_sve_imm(dc, Zdn, imm)   instr_create_1dst_2src(dc, OP_eor, Zdn, Zdn, imm)
 
#define INSTR_CREATE_orr_sve_imm(dc, Zdn, imm)   instr_create_1dst_2src(dc, OP_orr, Zdn, Zdn, imm)
 
#define INSTR_CREATE_orn_sve_imm(dc, Zdn, imm)   instr_create_1dst_2src(dc, OP_orr, Zdn, Zdn, opnd_invert_immed_int(imm))
 
#define INSTR_CREATE_and_sve_pred_b(dc, Pd, Pg, Pn, Pm)   instr_create_1dst_3src(dc, OP_and, Pd, Pg, Pn, Pm)
 
#define INSTR_CREATE_and_sve(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_and, Zd, Zn, Zm)
 
#define INSTR_CREATE_ands_sve_pred(dc, Pd, Pg, Pn, Pm)   instr_create_1dst_3src(dc, OP_ands, Pd, Pg, Pn, Pm)
 
#define INSTR_CREATE_bic_sve_pred_b(dc, Pd, Pg, Pn, Pm)   instr_create_1dst_3src(dc, OP_bic, Pd, Pg, Pn, Pm)
 
#define INSTR_CREATE_bic_sve(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_bic, Zd, Zn, Zm)
 
#define INSTR_CREATE_bics_sve_pred(dc, Pd, Pg, Pn, Pm)   instr_create_1dst_3src(dc, OP_bics, Pd, Pg, Pn, Pm)
 
#define INSTR_CREATE_eor_sve_pred_b(dc, Pd, Pg, Pn, Pm)   instr_create_1dst_3src(dc, OP_eor, Pd, Pg, Pn, Pm)
 
#define INSTR_CREATE_eor_sve(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_eor, Zd, Zn, Zm)
 
#define INSTR_CREATE_eors_sve_pred(dc, Pd, Pg, Pn, Pm)   instr_create_1dst_3src(dc, OP_eors, Pd, Pg, Pn, Pm)
 
#define INSTR_CREATE_nand_sve_pred(dc, Pd, Pg, Pn, Pm)   instr_create_1dst_3src(dc, OP_nand, Pd, Pg, Pn, Pm)
 
#define INSTR_CREATE_nands_sve_pred(dc, Pd, Pg, Pn, Pm)   instr_create_1dst_3src(dc, OP_nands, Pd, Pg, Pn, Pm)
 
#define INSTR_CREATE_nor_sve_pred(dc, Pd, Pg, Pn, Pm)   instr_create_1dst_3src(dc, OP_nor, Pd, Pg, Pn, Pm)
 
#define INSTR_CREATE_nors_sve_pred(dc, Pd, Pg, Pn, Pm)   instr_create_1dst_3src(dc, OP_nors, Pd, Pg, Pn, Pm)
 
#define INSTR_CREATE_not_sve_pred_vec(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_not, Zd, Pg, Zn)
 
#define INSTR_CREATE_orn_sve_pred(dc, Pd, Pg, Pn, Pm)   instr_create_1dst_3src(dc, OP_orn, Pd, Pg, Pn, Pm)
 
#define INSTR_CREATE_orns_sve_pred(dc, Pd, Pg, Pn, Pm)   instr_create_1dst_3src(dc, OP_orns, Pd, Pg, Pn, Pm)
 
#define INSTR_CREATE_orr_sve_pred_b(dc, Pd, Pg, Pn, Pm)   instr_create_1dst_3src(dc, OP_orr, Pd, Pg, Pn, Pm)
 
#define INSTR_CREATE_orr_sve(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_orr, Zd, Zn, Zm)
 
#define INSTR_CREATE_orrs_sve_pred(dc, Pd, Pg, Pn, Pm)   instr_create_1dst_3src(dc, OP_orrs, Pd, Pg, Pn, Pm)
 
#define INSTR_CREATE_clasta_sve_scalar(dc, Rdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_clasta, Rdn, Pg, Rdn, Zm)
 
#define INSTR_CREATE_clasta_sve_simd_fp(dc, Vdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_clasta, Vdn, Pg, Vdn, Zm)
 
#define INSTR_CREATE_clasta_sve_vector(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_clasta, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_clastb_sve_scalar(dc, Rdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_clastb, Rdn, Pg, Rdn, Zm)
 
#define INSTR_CREATE_clastb_sve_simd_fp(dc, Vdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_clastb, Vdn, Pg, Vdn, Zm)
 
#define INSTR_CREATE_clastb_sve_vector(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_clastb, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_lasta_sve_scalar(dc, Rd, Pg, Zn)   instr_create_1dst_2src(dc, OP_lasta, Rd, Pg, Zn)
 
#define INSTR_CREATE_lasta_sve_simd_fp(dc, Vd, Pg, Zn)   instr_create_1dst_2src(dc, OP_lasta, Vd, Pg, Zn)
 
#define INSTR_CREATE_lastb_sve_scalar(dc, Rd, Pg, Zn)   instr_create_1dst_2src(dc, OP_lastb, Rd, Pg, Zn)
 
#define INSTR_CREATE_lastb_sve_simd_fp(dc, Vd, Pg, Zn)   instr_create_1dst_2src(dc, OP_lastb, Vd, Pg, Zn)
 
#define INSTR_CREATE_cnt_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_cnt, Zd, Pg, Zn)
 
#define INSTR_CREATE_cntb(dc, Rd, pattern, imm)   instr_create_1dst_3src(dc, OP_cntb, Rd, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_cntd(dc, Rd, pattern, imm)   instr_create_1dst_3src(dc, OP_cntd, Rd, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_cnth(dc, Rd, pattern, imm)   instr_create_1dst_3src(dc, OP_cnth, Rd, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_cntw(dc, Rd, pattern, imm)   instr_create_1dst_3src(dc, OP_cntw, Rd, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_decb(dc, Rdn, pattern, imm)   instr_create_1dst_4src(dc, OP_decb, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_decd(dc, Rdn, pattern, imm)   instr_create_1dst_4src(dc, OP_decd, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_decd_sve(dc, Zdn, pattern, imm)   instr_create_1dst_4src(dc, OP_decd, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_dech(dc, Rdn, pattern, imm)   instr_create_1dst_4src(dc, OP_dech, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_dech_sve(dc, Zdn, pattern, imm)   instr_create_1dst_4src(dc, OP_dech, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_decw(dc, Rdn, pattern, imm)   instr_create_1dst_4src(dc, OP_decw, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_decw_sve(dc, Zdn, pattern, imm)   instr_create_1dst_4src(dc, OP_decw, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_incb(dc, Rdn, pattern, imm)   instr_create_1dst_4src(dc, OP_incb, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_incd(dc, Rdn, pattern, imm)   instr_create_1dst_4src(dc, OP_incd, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_incd_sve(dc, Zdn, pattern, imm)   instr_create_1dst_4src(dc, OP_incd, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_inch(dc, Rdn, pattern, imm)   instr_create_1dst_4src(dc, OP_inch, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_inch_sve(dc, Zdn, pattern, imm)   instr_create_1dst_4src(dc, OP_inch, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_incw(dc, Rdn, pattern, imm)   instr_create_1dst_4src(dc, OP_incw, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_incw_sve(dc, Zdn, pattern, imm)   instr_create_1dst_4src(dc, OP_incw, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_sqdecb_wide(dc, Rdn, pattern, imm)
 
#define INSTR_CREATE_sqdecb(dc, Rdn, pattern, imm)   instr_create_1dst_4src(dc, OP_sqdecb, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_sqdecd_wide(dc, Rdn, pattern, imm)
 
#define INSTR_CREATE_sqdecd(dc, Rdn, pattern, imm)   instr_create_1dst_4src(dc, OP_sqdecd, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_sqdecd_sve(dc, Zdn, pattern, imm)   instr_create_1dst_4src(dc, OP_sqdecd, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_sqdech_wide(dc, Rdn, pattern, imm)
 
#define INSTR_CREATE_sqdech(dc, Rdn, pattern, imm)   instr_create_1dst_4src(dc, OP_sqdech, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_sqdech_sve(dc, Zdn, pattern, imm)   instr_create_1dst_4src(dc, OP_sqdech, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_sqdecw_wide(dc, Rdn, pattern, imm)
 
#define INSTR_CREATE_sqdecw(dc, Rdn, pattern, imm)   instr_create_1dst_4src(dc, OP_sqdecw, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_sqdecw_sve(dc, Zdn, pattern, imm)   instr_create_1dst_4src(dc, OP_sqdecw, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_sqincb_wide(dc, Rdn, pattern, imm)
 
#define INSTR_CREATE_sqincb(dc, Rdn, pattern, imm)   instr_create_1dst_4src(dc, OP_sqincb, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_sqincd_wide(dc, Rdn, pattern, imm)
 
#define INSTR_CREATE_sqincd(dc, Rdn, pattern, imm)   instr_create_1dst_4src(dc, OP_sqincd, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_sqincd_sve(dc, Zdn, pattern, imm)   instr_create_1dst_4src(dc, OP_sqincd, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_sqinch_wide(dc, Rdn, pattern, imm)
 
#define INSTR_CREATE_sqinch(dc, Rdn, pattern, imm)   instr_create_1dst_4src(dc, OP_sqinch, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_sqinch_sve(dc, Zdn, pattern, imm)   instr_create_1dst_4src(dc, OP_sqinch, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_sqincw_wide(dc, Rdn, pattern, imm)
 
#define INSTR_CREATE_sqincw(dc, Rdn, pattern, imm)   instr_create_1dst_4src(dc, OP_sqincw, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_sqincw_sve(dc, Zdn, pattern, imm)   instr_create_1dst_4src(dc, OP_sqincw, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_uqdecb(dc, Rdn, pattern, imm)   instr_create_1dst_4src(dc, OP_uqdecb, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_uqdecd(dc, Rdn, pattern, imm)   instr_create_1dst_4src(dc, OP_uqdecd, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_uqdecd_sve(dc, Zdn, pattern, imm)   instr_create_1dst_4src(dc, OP_uqdecd, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_uqdech(dc, Rdn, pattern, imm)   instr_create_1dst_4src(dc, OP_uqdech, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_uqdech_sve(dc, Zdn, pattern, imm)   instr_create_1dst_4src(dc, OP_uqdech, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_uqdecw(dc, Rdn, pattern, imm)   instr_create_1dst_4src(dc, OP_uqdecw, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_uqdecw_sve(dc, Zdn, pattern, imm)   instr_create_1dst_4src(dc, OP_uqdecw, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_uqincb(dc, Rdn, pattern, imm)   instr_create_1dst_4src(dc, OP_uqincb, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_uqincd(dc, Rdn, pattern, imm)   instr_create_1dst_4src(dc, OP_uqincd, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_uqincd_sve(dc, Zdn, pattern, imm)   instr_create_1dst_4src(dc, OP_uqincd, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_uqinch(dc, Rdn, pattern, imm)   instr_create_1dst_4src(dc, OP_uqinch, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_uqinch_sve(dc, Zdn, pattern, imm)   instr_create_1dst_4src(dc, OP_uqinch, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_uqincw(dc, Rdn, pattern, imm)   instr_create_1dst_4src(dc, OP_uqincw, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_uqincw_sve(dc, Zdn, pattern, imm)   instr_create_1dst_4src(dc, OP_uqincw, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm)
 
#define INSTR_CREATE_brka_sve_pred(dc, Pd, Pg, Pn)   instr_create_1dst_2src(dc, OP_brka, Pd, Pg, Pn)
 
#define INSTR_CREATE_brkas_sve_pred(dc, Pd, Pg, Pn)   instr_create_1dst_2src(dc, OP_brkas, Pd, Pg, Pn)
 
#define INSTR_CREATE_brkb_sve_pred(dc, Pd, Pg, Pn)   instr_create_1dst_2src(dc, OP_brkb, Pd, Pg, Pn)
 
#define INSTR_CREATE_brkbs_sve_pred(dc, Pd, Pg, Pn)   instr_create_1dst_2src(dc, OP_brkbs, Pd, Pg, Pn)
 
#define INSTR_CREATE_brkn_sve_pred(dc, Pdm, Pg, Pn)   instr_create_1dst_3src(dc, OP_brkn, Pdm, Pg, Pn, Pdm)
 
#define INSTR_CREATE_brkns_sve_pred(dc, Pdm, Pg, Pn)   instr_create_1dst_3src(dc, OP_brkns, Pdm, Pg, Pn, Pdm)
 
#define INSTR_CREATE_brkpa_sve_pred(dc, Pd, Pg, Pn, Pm)   instr_create_1dst_3src(dc, OP_brkpa, Pd, Pg, Pn, Pm)
 
#define INSTR_CREATE_brkpas_sve_pred(dc, Pd, Pg, Pn, Pm)   instr_create_1dst_3src(dc, OP_brkpas, Pd, Pg, Pn, Pm)
 
#define INSTR_CREATE_brkpb_sve_pred(dc, Pd, Pg, Pn, Pm)   instr_create_1dst_3src(dc, OP_brkpb, Pd, Pg, Pn, Pm)
 
#define INSTR_CREATE_brkpbs_sve_pred(dc, Pd, Pg, Pn, Pm)   instr_create_1dst_3src(dc, OP_brkpbs, Pd, Pg, Pn, Pm)
 
#define INSTR_CREATE_whilele_sve(dc, Pd, Rn, Rm)   instr_create_1dst_2src(dc, OP_whilele, Pd, Rn, Rm)
 
#define INSTR_CREATE_whilelo_sve(dc, Pd, Rn, Rm)   instr_create_1dst_2src(dc, OP_whilelo, Pd, Rn, Rm)
 
#define INSTR_CREATE_whilels_sve(dc, Pd, Rn, Rm)   instr_create_1dst_2src(dc, OP_whilels, Pd, Rn, Rm)
 
#define INSTR_CREATE_whilelt_sve(dc, Pd, Rn, Rm)   instr_create_1dst_2src(dc, OP_whilelt, Pd, Rn, Rm)
 
#define INSTR_CREATE_tbl_sve(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_tbl, Zd, Zn, Zm)
 
#define INSTR_CREATE_dup_sve_shift(dc, Zd, simm, shift)   instr_create_1dst_3src(dc, OP_dup, Zd, simm, OPND_CREATE_LSL(), shift)
 
#define INSTR_CREATE_dup_sve_idx(dc, Zd, Zn, index)   instr_create_1dst_2src(dc, OP_dup, Zd, Zn, index)
 
#define INSTR_CREATE_dup_sve_scalar(dc, Zd, Rn)   instr_create_1dst_1src(dc, OP_dup, Zd, Rn)
 
#define INSTR_CREATE_insr_sve_scalar(dc, Zd, Rm)   instr_create_1dst_2src(dc, OP_insr, Zd, Zd, Rm)
 
#define INSTR_CREATE_insr_sve_simd_fp(dc, Zdn, Vm)   instr_create_1dst_2src(dc, OP_insr, Zdn, Zdn, Vm)
 
#define INSTR_CREATE_ext_sve(dc, Zdn, Zm, imm)   instr_create_1dst_3src(dc, OP_ext, Zdn, Zdn, Zm, imm)
 
#define INSTR_CREATE_splice_sve(dc, Zdn, Pv, Zm)   instr_create_1dst_3src(dc, OP_splice, Zdn, Pv, Zdn, Zm)
 
#define INSTR_CREATE_rev_sve_pred(dc, Pd, Pn)   instr_create_1dst_1src(dc, OP_rev, Pd, Pn)
 
#define INSTR_CREATE_rev_sve(dc, Zd, Zn)   instr_create_1dst_1src(dc, OP_rev, Zd, Zn)
 
#define INSTR_CREATE_revb_sve(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_revb, Zd, Pg, Zn)
 
#define INSTR_CREATE_revh_sve(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_revh, Zd, Pg, Zn)
 
#define INSTR_CREATE_revw_sve(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_revw, Zd, Pg, Zn)
 
#define INSTR_CREATE_compact_sve(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_compact, Zd, Pg, Zn)
 
#define INSTR_CREATE_punpkhi_sve(dc, Pd, Pn)   instr_create_1dst_1src(dc, OP_punpkhi, Pd, Pn)
 
#define INSTR_CREATE_punpklo_sve(dc, Pd, Pn)   instr_create_1dst_1src(dc, OP_punpklo, Pd, Pn)
 
#define INSTR_CREATE_sunpkhi_sve(dc, Zd, Zn)   instr_create_1dst_1src(dc, OP_sunpkhi, Zd, Zn)
 
#define INSTR_CREATE_sunpklo_sve(dc, Zd, Zn)   instr_create_1dst_1src(dc, OP_sunpklo, Zd, Zn)
 
#define INSTR_CREATE_uunpkhi_sve(dc, Zd, Zn)   instr_create_1dst_1src(dc, OP_uunpkhi, Zd, Zn)
 
#define INSTR_CREATE_uunpklo_sve(dc, Zd, Zn)   instr_create_1dst_1src(dc, OP_uunpklo, Zd, Zn)
 
#define INSTR_CREATE_uzp1_sve_pred(dc, Pd, Pn, Pm)   instr_create_1dst_2src(dc, OP_uzp1, Pd, Pn, Pm)
 
#define INSTR_CREATE_uzp1_sve_vector(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_uzp1, Zd, Zn, Zm)
 
#define INSTR_CREATE_uzp2_sve_pred(dc, Pd, Pn, Pm)   instr_create_1dst_2src(dc, OP_uzp2, Pd, Pn, Pm)
 
#define INSTR_CREATE_uzp2_sve_vector(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_uzp2, Zd, Zn, Zm)
 
#define INSTR_CREATE_zip1_sve_pred(dc, Pd, Pn, Pm)   instr_create_1dst_2src(dc, OP_zip1, Pd, Pn, Pm)
 
#define INSTR_CREATE_zip1_sve_vector(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_zip1, Zd, Zn, Zm)
 
#define INSTR_CREATE_zip2_sve_pred(dc, Pd, Pn, Pm)   instr_create_1dst_2src(dc, OP_zip2, Pd, Pn, Pm)
 
#define INSTR_CREATE_zip2_sve_vector(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_zip2, Zd, Zn, Zm)
 
#define INSTR_CREATE_trn1_sve_pred(dc, Pd, Pn, Pm)   instr_create_1dst_2src(dc, OP_trn1, Pd, Pn, Pm)
 
#define INSTR_CREATE_trn1_sve_vector(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_trn1, Zd, Zn, Zm)
 
#define INSTR_CREATE_trn2_sve_pred(dc, Pd, Pn, Pm)   instr_create_1dst_2src(dc, OP_trn2, Pd, Pn, Pm)
 
#define INSTR_CREATE_trn2_sve_vector(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_trn2, Zd, Zn, Zm)
 
#define INSTR_CREATE_dupm_sve(dc, Zd, imm)   instr_create_1dst_1src(dc, OP_dupm, Zd, imm)
 
#define INSTR_CREATE_eon_sve_imm(dc, Zdn, imm)   instr_create_1dst_2src(dc, OP_eor, Zdn, Zdn, opnd_invert_immed_int(imm))
 
#define INSTR_CREATE_pfalse_sve(dc, Pd)   instr_create_1dst_0src(dc, OP_pfalse, Pd)
 
#define INSTR_CREATE_pfirst_sve(dc, Pdn, Pg)   instr_create_1dst_2src(dc, OP_pfirst, Pdn, Pg, Pdn)
 
#define INSTR_CREATE_sel_sve_pred(dc, Pd, Pg, Pn, Pm)   instr_create_1dst_3src(dc, OP_sel, Pd, Pg, Pn, Pm)
 
#define INSTR_CREATE_sel_sve_vector(dc, Zd, Pv, Zn, Zm)   instr_create_1dst_3src(dc, OP_sel, Zd, Pv, Zn, Zm)
 
#define INSTR_CREATE_mov_sve_pred(dc, Pd, Pn)
 
#define INSTR_CREATE_movs_sve_pred(dc, Pd, Pg, Pn)   instr_create_1dst_3src(dc, OP_ands, Pd, Pg, Pn, Pn)
 
#define INSTR_CREATE_ptrue_sve(dc, Pd, pattern)   instr_create_1dst_1src(dc, OP_ptrue, Pd, pattern)
 
#define INSTR_CREATE_ptrues_sve(dc, Pd, pattern)   instr_create_1dst_1src(dc, OP_ptrues, Pd, pattern)
 
#define INSTR_CREATE_asr_sve(dc, Zd, Zn, imm)   instr_create_1dst_2src(dc, OP_asr, Zd, Zn, imm)
 
#define INSTR_CREATE_asr_sve_pred(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_asr, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_asr_sve_pred_wide(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_asr, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_asr_sve_wide(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_asr, Zd, Zn, Zm)
 
#define INSTR_CREATE_asrd_sve_pred(dc, Zdn, Pg, imm)   instr_create_1dst_3src(dc, OP_asrd, Zdn, Pg, Zdn, imm)
 
#define INSTR_CREATE_asrr_sve_pred(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_asrr, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_cls_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_cls, Zd, Pg, Zn)
 
#define INSTR_CREATE_clz_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_clz, Zd, Pg, Zn)
 
#define INSTR_CREATE_cnt_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_cnt, Zd, Pg, Zn)
 
#define INSTR_CREATE_lsl_sve(dc, Zd, Zn, imm)   instr_create_1dst_2src(dc, OP_lsl, Zd, Zn, imm)
 
#define INSTR_CREATE_lsl_sve_pred(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_lsl, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_lsl_sve_pred_wide(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_lsl, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_lsl_sve_wide(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_lsl, Zd, Zn, Zm)
 
#define INSTR_CREATE_lslr_sve_pred(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_lslr, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_lsr_sve(dc, Zd, Zn, imm)   instr_create_1dst_2src(dc, OP_lsr, Zd, Zn, imm)
 
#define INSTR_CREATE_lsr_sve_pred(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_lsr, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_lsr_sve_pred_wide(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_lsr, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_lsr_sve_wide(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_lsr, Zd, Zn, Zm)
 
#define INSTR_CREATE_lsrr_sve_pred(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_lsrr, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_rbit_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_rbit, Zd, Pg, Zn)
 
#define INSTR_CREATE_andv_sve_pred(dc, Vd, Pg, Zn)   instr_create_1dst_2src(dc, OP_andv, Vd, Pg, Zn)
 
#define INSTR_CREATE_eorv_sve_pred(dc, Vd, Pg, Zn)   instr_create_1dst_2src(dc, OP_eorv, Vd, Pg, Zn)
 
#define INSTR_CREATE_fadda_sve_pred(dc, Vdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_fadda, Vdn, Pg, Vdn, Zm)
 
#define INSTR_CREATE_faddv_sve_pred(dc, Vd, Pg, Zn)   instr_create_1dst_2src(dc, OP_faddv, Vd, Pg, Zn)
 
#define INSTR_CREATE_fmaxnmv_sve_pred(dc, Vd, Pg, Zn)   instr_create_1dst_2src(dc, OP_fmaxnmv, Vd, Pg, Zn)
 
#define INSTR_CREATE_fmaxv_sve_pred(dc, Vd, Pg, Zn)   instr_create_1dst_2src(dc, OP_fmaxv, Vd, Pg, Zn)
 
#define INSTR_CREATE_fminnmv_sve_pred(dc, Vd, Pg, Zn)   instr_create_1dst_2src(dc, OP_fminnmv, Vd, Pg, Zn)
 
#define INSTR_CREATE_fminv_sve_pred(dc, Vd, Pg, Zn)   instr_create_1dst_2src(dc, OP_fminv, Vd, Pg, Zn)
 
#define INSTR_CREATE_orv_sve_pred(dc, Vd, Pg, Zn)   instr_create_1dst_2src(dc, OP_orv, Vd, Pg, Zn)
 
#define INSTR_CREATE_saddv_sve_pred(dc, Vd, Pg, Zn)   instr_create_1dst_2src(dc, OP_saddv, Vd, Pg, Zn)
 
#define INSTR_CREATE_smaxv_sve_pred(dc, Vd, Pg, Zn)   instr_create_1dst_2src(dc, OP_smaxv, Vd, Pg, Zn)
 
#define INSTR_CREATE_sminv_sve_pred(dc, Vd, Pg, Zn)   instr_create_1dst_2src(dc, OP_sminv, Vd, Pg, Zn)
 
#define INSTR_CREATE_uaddv_sve_pred(dc, Vd, Pg, Zn)   instr_create_1dst_2src(dc, OP_uaddv, Vd, Pg, Zn)
 
#define INSTR_CREATE_umaxv_sve_pred(dc, Vd, Pg, Zn)   instr_create_1dst_2src(dc, OP_umaxv, Vd, Pg, Zn)
 
#define INSTR_CREATE_uminv_sve_pred(dc, Vd, Pg, Zn)   instr_create_1dst_2src(dc, OP_uminv, Vd, Pg, Zn)
 
#define INSTR_CREATE_fdup_sve(dc, Zd, imm)   instr_create_1dst_1src(dc, OP_fdup, Zd, imm)
 
#define INSTR_CREATE_ld1rb_sve(dc, Zt, Pg, Rn)   instr_create_1dst_2src(dc, OP_ld1rb, Zt, Rn, Pg)
 
#define INSTR_CREATE_ld1rh_sve(dc, Zt, Pg, Rn)   instr_create_1dst_2src(dc, OP_ld1rh, Zt, Rn, Pg)
 
#define INSTR_CREATE_ld1rw_sve(dc, Zt, Pg, Rn)   instr_create_1dst_2src(dc, OP_ld1rw, Zt, Rn, Pg)
 
#define INSTR_CREATE_ld1rd_sve(dc, Zt, Pg, Rn)   instr_create_1dst_2src(dc, OP_ld1rd, Zt, Rn, Pg)
 
#define INSTR_CREATE_ld1rsb_sve(dc, Zt, Pg, Rn)   instr_create_1dst_2src(dc, OP_ld1rsb, Zt, Rn, Pg)
 
#define INSTR_CREATE_ld1rsh_sve(dc, Zt, Pg, Rn)   instr_create_1dst_2src(dc, OP_ld1rsh, Zt, Rn, Pg)
 
#define INSTR_CREATE_ld1rsw_sve(dc, Zt, Pg, Rn)   instr_create_1dst_2src(dc, OP_ld1rsw, Zt, Rn, Pg)
 
#define INSTR_CREATE_index_sve(dc, Zd, Rn_or_imm, Rm_or_imm)   instr_create_1dst_2src(dc, OP_index, Zd, Rn_or_imm, Rm_or_imm)
 
#define INSTR_CREATE_fcvt_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_fcvt, Zd, Pg, Zn)
 
#define INSTR_CREATE_fcvtzs_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_fcvtzs, Zd, Pg, Zn)
 
#define INSTR_CREATE_fcvtzu_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_fcvtzu, Zd, Pg, Zn)
 
#define INSTR_CREATE_frinta_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_frinta, Zd, Pg, Zn)
 
#define INSTR_CREATE_frinti_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_frinti, Zd, Pg, Zn)
 
#define INSTR_CREATE_frintm_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_frintm, Zd, Pg, Zn)
 
#define INSTR_CREATE_frintn_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_frintn, Zd, Pg, Zn)
 
#define INSTR_CREATE_frintp_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_frintp, Zd, Pg, Zn)
 
#define INSTR_CREATE_frintx_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_frintx, Zd, Pg, Zn)
 
#define INSTR_CREATE_frintz_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_frintz, Zd, Pg, Zn)
 
#define INSTR_CREATE_scvtf_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_scvtf, Zd, Pg, Zn)
 
#define INSTR_CREATE_ucvtf_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_ucvtf, Zd, Pg, Zn)
 
#define INSTR_CREATE_ctermeq(dc, Rn, Rm)   instr_create_0dst_2src(dc, OP_ctermeq, Rn, Rm)
 
#define INSTR_CREATE_ctermne(dc, Rn, Rm)   instr_create_0dst_2src(dc, OP_ctermne, Rn, Rm)
 
#define INSTR_CREATE_pnext_sve(dc, Pdn, Pv)   instr_create_1dst_2src(dc, OP_pnext, Pdn, Pv, Pdn)
 
#define INSTR_CREATE_fabd_sve(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_fabd, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_fabs_sve(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_fabs, Zd, Pg, Zn)
 
#define INSTR_CREATE_fdiv_sve(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_fdiv, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_fdivr_sve(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_fdivr, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_fmad_sve(dc, Zdn, Pg, Zm, Za)   instr_create_1dst_4src(dc, OP_fmad, Zdn, Zdn, Pg, Zm, Za)
 
#define INSTR_CREATE_fmulx_sve(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_fmulx, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_fneg_sve(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_fneg, Zd, Pg, Zn)
 
#define INSTR_CREATE_fnmad_sve(dc, Zdn, Pg, Zm, Za)   instr_create_1dst_4src(dc, OP_fnmad, Zdn, Zdn, Pg, Zm, Za)
 
#define INSTR_CREATE_fnmla_sve(dc, Zda, Pg, Zn, Zm)   instr_create_1dst_4src(dc, OP_fnmla, Zda, Zda, Pg, Zn, Zm)
 
#define INSTR_CREATE_fnmls_sve(dc, Zda, Pg, Zn, Zm)   instr_create_1dst_4src(dc, OP_fnmls, Zda, Zda, Pg, Zn, Zm)
 
#define INSTR_CREATE_frecpe_sve(dc, Zd, Zn)   instr_create_1dst_1src(dc, OP_frecpe, Zd, Zn)
 
#define INSTR_CREATE_frecps_sve(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_frecps, Zd, Zn, Zm)
 
#define INSTR_CREATE_frecpx_sve_pred(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_frecpx, Zd, Pg, Zn)
 
#define INSTR_CREATE_frsqrte_sve(dc, Zd, Zn)   instr_create_1dst_1src(dc, OP_frsqrte, Zd, Zn)
 
#define INSTR_CREATE_frsqrts_sve(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_frsqrts, Zd, Zn, Zm)
 
#define INSTR_CREATE_fscale_sve(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_fscale, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_fsqrt_sve(dc, Zd, Pg, Zn)   instr_create_1dst_2src(dc, OP_fsqrt, Zd, Pg, Zn)
 
#define INSTR_CREATE_fadd_sve(dc, Zdn, Pg, imm)   instr_create_1dst_3src(dc, OP_fadd, Zdn, Pg, Zdn, imm)
 
#define INSTR_CREATE_fadd_sve_pred(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_fadd, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_fadd_sve_vector(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_fadd, Zd, Zn, Zm)
 
#define INSTR_CREATE_fsub_sve(dc, Zdn, Pg, imm)   instr_create_1dst_3src(dc, OP_fsub, Zdn, Pg, Zdn, imm)
 
#define INSTR_CREATE_fsub_sve_pred(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_fsub, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_fsub_sve_vector(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_fsub, Zd, Zn, Zm)
 
#define INSTR_CREATE_fsubr_sve(dc, Zdn, Pg, imm)   instr_create_1dst_3src(dc, OP_fsubr, Zdn, Pg, Zdn, imm)
 
#define INSTR_CREATE_fsubr_sve_vector(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_fsubr, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_fmax_sve(dc, Zdn, Pg, imm)   instr_create_1dst_3src(dc, OP_fmax, Zdn, Pg, Zdn, imm)
 
#define INSTR_CREATE_fmax_sve_vector(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_fmax, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_fmaxnm_sve(dc, Zdn, Pg, imm)   instr_create_1dst_3src(dc, OP_fmaxnm, Zdn, Pg, Zdn, imm)
 
#define INSTR_CREATE_fmaxnm_sve_vector(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_fmaxnm, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_fmin_sve(dc, Zdn, Pg, imm)   instr_create_1dst_3src(dc, OP_fmin, Zdn, Pg, Zdn, imm)
 
#define INSTR_CREATE_fmin_sve_vector(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_fmin, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_fminnm_sve(dc, Zdn, Pg, imm)   instr_create_1dst_3src(dc, OP_fminnm, Zdn, Pg, Zdn, imm)
 
#define INSTR_CREATE_fminnm_sve_vector(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_fminnm, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_fmla_sve_vector(dc, Zda, Pg, Zn, Zm)   instr_create_1dst_4src(dc, OP_fmla, Zda, Zda, Pg, Zn, Zm)
 
#define INSTR_CREATE_fmla_sve_idx(dc, Zda, Zn, Zm, index)   instr_create_1dst_4src(dc, OP_fmla, Zda, Zda, Zn, Zm, index)
 
#define INSTR_CREATE_fmls_sve_vector(dc, Zda, Pg, Zn, Zm)   instr_create_1dst_4src(dc, OP_fmls, Zda, Zda, Pg, Zn, Zm)
 
#define INSTR_CREATE_fmls_sve_idx(dc, Zda, Zn, Zm, index)   instr_create_1dst_4src(dc, OP_fmls, Zda, Zda, Zn, Zm, index)
 
#define INSTR_CREATE_fmsb_sve(dc, Zdn, Pg, Zm, Za)   instr_create_1dst_4src(dc, OP_fmsb, Zdn, Zdn, Pg, Zm, Za)
 
#define INSTR_CREATE_fmul_sve(dc, Zdn, Pg, imm)   instr_create_1dst_3src(dc, OP_fmul, Zdn, Pg, Zdn, imm)
 
#define INSTR_CREATE_fmul_sve_pred_vector(dc, Zdn, Pg, Zm)   instr_create_1dst_3src(dc, OP_fmul, Zdn, Pg, Zdn, Zm)
 
#define INSTR_CREATE_fmul_sve_vector(dc, Zd, Zn, Zm)   instr_create_1dst_2src(dc, OP_fmul, Zd, Zn, Zm)
 
#define INSTR_CREATE_fmul_sve_idx(dc, Zd, Zn, Zm, index)   instr_create_1dst_3src(dc, OP_fmul, Zd, Zn, Zm, index)
 
Platform-independent macros
#define XINST_CREATE_debug_instr(dc)   INSTR_CREATE_brk((dc), OPND_CREATE_INT16(0))
 
#define XINST_CREATE_load(dc, r, m)
 
#define XINST_CREATE_load_1byte_zext4(dc, r, m)   INSTR_CREATE_ldrb(dc, r, m)
 
#define XINST_CREATE_load_1byte(dc, r, m)   INSTR_CREATE_ldrb(dc, r, m)
 
#define XINST_CREATE_load_2bytes(dc, r, m)   INSTR_CREATE_ldrh(dc, r, m)
 
#define XINST_CREATE_store(dc, m, r)
 
#define XINST_CREATE_store_1byte(dc, m, r)   INSTR_CREATE_strb(dc, m, opnd_create_reg(reg_resize_to_opsz(opnd_get_reg(r), OPSZ_4)))
 
#define XINST_CREATE_store_2bytes(dc, m, r)   INSTR_CREATE_strh(dc, m, opnd_create_reg(reg_resize_to_opsz(opnd_get_reg(r), OPSZ_4)))
 
#define XINST_CREATE_store_pair(dc, m, r1, r2)   INSTR_CREATE_stp(dc, m, r1, r2)
 
#define XINST_CREATE_load_pair(dc, r1, r2, m)   INSTR_CREATE_ldp(dc, r1, r2, m)
 
#define XINST_CREATE_move(dc, d, s)
 
#define XINST_CREATE_load_simd(dc, r, m)   INSTR_CREATE_ldr((dc), (r), (m))
 
#define XINST_CREATE_store_simd(dc, m, r)   INSTR_CREATE_str((dc), (m), (r))
 
#define XINST_CREATE_jump_reg(dc, r)   INSTR_CREATE_br((dc), (r))
 
#define XINST_CREATE_load_int(dc, r, i)
 
#define XINST_CREATE_return(dc)   INSTR_CREATE_ret(dc, opnd_create_reg(DR_REG_X30))
 
#define XINST_CREATE_jump(dc, t)   INSTR_CREATE_b((dc), (t))
 
#define XINST_CREATE_jump_short(dc, t)   INSTR_CREATE_b((dc), (t))
 
#define XINST_CREATE_call(dc, t)   INSTR_CREATE_bl(dc, t)
 
#define XINST_CREATE_jump_cond(dc, pred, t)   (INSTR_PRED(INSTR_CREATE_bcond((dc), (t)), (pred)))
 
#define XINST_CREATE_add(dc, d, s)   INSTR_CREATE_add(dc, d, d, s)
 
#define XINST_CREATE_add_2src(dc, d, s1, s2)   INSTR_CREATE_add(dc, d, s1, s2)
 
#define XINST_CREATE_add_sll(dc, d, s1, s2_toshift, shift_amount)
 
#define XINST_CREATE_add_s(dc, d, s)   INSTR_CREATE_adds(dc, d, d, s)
 
#define XINST_CREATE_sub(dc, d, s)   INSTR_CREATE_sub(dc, d, d, s)
 
#define XINST_CREATE_sub_s(dc, d, s)   INSTR_CREATE_subs(dc, d, d, s)
 
#define XINST_CREATE_and_s(dc, d, s)   INSTR_CREATE_ands(dc, d, d, s)
 
#define XINST_CREATE_cmp(dc, s1, s2)   INSTR_CREATE_cmp(dc, s1, s2)
 
#define XINST_CREATE_interrupt(dc, i)   INSTR_CREATE_svc(dc, (i))
 
#define XINST_CREATE_slr_s(dc, d, rm_or_imm)
 
#define XINST_CREATE_nop(dc)   INSTR_CREATE_nop(dc)
 
#define XINST_CREATE_call_reg(dc, r)   INSTR_CREATE_blr(dc, r)
 

Detailed Description

AArch64-specific instruction creation convenience macros.

Macro Definition Documentation

◆ INSTR_CREATE_abs_sve_pred

#define INSTR_CREATE_abs_sve_pred (   dc,
  Zd,
  Pg,
  Zn 
)    instr_create_1dst_2src(dc, OP_abs, Zd, Pg, Zn)

Creates an ABS instruction.

This macro is used to encode the forms:

*    ABS     <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe destination vector register, Z (Scalable)
PgThe governing predicate register, P (Predicate)
ZnThe source vector register, Z (Scalable)

◆ INSTR_CREATE_add_sve

#define INSTR_CREATE_add_sve (   dc,
  Zd,
  Zn,
  Zm 
)    instr_create_1dst_2src(dc, OP_add, Zd, Zn, Zm)

Creates a ADD instruction.

This macro is used to encode the forms:

*    ADD     <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe first destination vector register, Z (Scalable)
ZnThe first source vector register, Z (Scalable)
ZmThe second source vector register, Z (Scalable)

◆ INSTR_CREATE_add_sve_pred

#define INSTR_CREATE_add_sve_pred (   dc,
  Zdn,
  Pg,
  Zm 
)    instr_create_1dst_3src(dc, OP_add, Zdn, Pg, Zdn, Zm)

Creates a ADD instruction.

This macro is used to encode the forms:

*    ADD     <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and first destination vector register, Z (Scalable)
PgThe governing predicate register, P (Predicate)
ZmThe second source vector register, Z (Scalable)

◆ INSTR_CREATE_add_sve_shift

#define INSTR_CREATE_add_sve_shift (   dc,
  Zdn,
  imm,
  shift 
)    instr_create_1dst_4src(dc, OP_add, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift)

Creates a ADD instruction.

This macro is used to encode the forms:

*    ADD     <Zdn>.<Ts>, <Zdn>.<Ts>, #<imm>, <shift>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and first destination vector register, Z (Scalable)
immThe immediate imm
shiftThe immediate shiftOp for imm

◆ INSTR_CREATE_add_vector

#define INSTR_CREATE_add_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_add, Rd, Rm, Rn, width)

Creates a ADD vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_addhn2_vector

#define INSTR_CREATE_addhn2_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_addhn2, Rd, Rm, Rn, width)

Creates a ADDHN2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_addhn_vector

#define INSTR_CREATE_addhn_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_addhn, Rd, Rm, Rn, width)

Creates a ADDHN vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_addp_vector

#define INSTR_CREATE_addp_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_addp, Rd, Rm, Rn, width)

Creates a ADDP vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_and

#define INSTR_CREATE_and (   dc,
  rd,
  rn,
  rm_or_imm 
)
Value:
(opnd_is_immed(rm_or_imm) \
? instr_create_1dst_2src((dc), OP_and, (rd), (rn), (rm_or_imm)) \
: INSTR_CREATE_and_shift(dc, rd, rn, rm_or_imm, OPND_CREATE_LSL(), \

disabled_until_i4106_is_fixed Creates an AND instruction with one output and two inputs.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
rdThe output register.
rnThe first input register.
rm_or_immThe second input register or immediate.

◆ INSTR_CREATE_and_sve

#define INSTR_CREATE_and_sve (   dc,
  Zd,
  Zn,
  Zm 
)    instr_create_1dst_2src(dc, OP_and, Zd, Zn, Zm)

Creates an AND instruction.

This macro is used to encode the forms:

*    AND     <Zd>.D, <Zn>.D, <Zm>.D
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe destination vector register, Z (Scalable).
ZnThe first source vector register, Z (Scalable).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_and_sve_imm

#define INSTR_CREATE_and_sve_imm (   dc,
  Zdn,
  imm 
)    instr_create_1dst_2src(dc, OP_and, Zdn, Zdn, imm)

Creates an AND instruction.

This macro is used to encode the forms:

*    AND     <Zdn>.<T>, <Zdn>.<T>, #<imm>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
immThe immediate logicalImm. The 13 bit immediate defining a 64, 32, 16 or 8 bit mask of 2, 4, 8, 16, 32 or 64 bit fields.

◆ INSTR_CREATE_and_sve_pred

#define INSTR_CREATE_and_sve_pred (   dc,
  Zd,
  Pg,
  Zd_,
  Zm,
  width 
)    instr_create_1dst_4src(dc, OP_and, Zd, Pg, Zd_, Zm, width)

Creates an AND scalable vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe output SVE vector register.
PgPredicate register for predicated instruction, P0-P7.
Zd_The first input SVE vector register. Must match Zd.
ZmThe second input SVE vector register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_and_sve_pred_b

#define INSTR_CREATE_and_sve_pred_b (   dc,
  Pd,
  Pg,
  Pn,
  Pm 
)    instr_create_1dst_3src(dc, OP_and, Pd, Pg, Pn, Pm)

Creates an AND instruction.

This macro is used to encode the forms:

*    AND     <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate).
PgThe governing predicate register, P (Predicate).
PnThe first source predicate register, P (Predicate).
PmThe second source predicate register, P (Predicate).

◆ INSTR_CREATE_and_vector

#define INSTR_CREATE_and_vector (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_and, Rd, Rm, Rn)

Creates a AND vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_ands

#define INSTR_CREATE_ands (   dc,
  rd,
  rn,
  rm_or_imm 
)
Value:
(opnd_is_immed(rm_or_imm) \
? instr_create_1dst_2src((dc), OP_ands, (rd), (rn), (rm_or_imm)) \
: INSTR_CREATE_ands_shift(dc, rd, rn, rm_or_imm, OPND_CREATE_LSL(), \

disabled_until_i4106_is_fixed Creates an ANDS instruction with one output and two inputs.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
rdThe output register.
rnThe first input register.
rm_or_immThe second input register or immediate.

◆ INSTR_CREATE_ands_sve_pred

#define INSTR_CREATE_ands_sve_pred (   dc,
  Pd,
  Pg,
  Pn,
  Pm 
)    instr_create_1dst_3src(dc, OP_ands, Pd, Pg, Pn, Pm)

Creates an ANDS instruction.

This macro is used to encode the forms:

*    ANDS    <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate).
PgThe governing predicate register, P (Predicate).
PnThe first source predicate register, P (Predicate).
PmThe second source predicate register, P (Predicate).

◆ INSTR_CREATE_andv_sve_pred

#define INSTR_CREATE_andv_sve_pred (   dc,
  Vd,
  Pg,
  Zn 
)    instr_create_1dst_2src(dc, OP_andv, Vd, Pg, Zn)

Creates an ANDV instruction.

This macro is used to encode the forms:

*    ANDV    <V><d>, <Pg>, <Zn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits), B (byte, 8 bits) or D (doubleword, 64 bits).
PgThe governing predicate register, P (Predicate).
ZnThe source vector register, Z (Scalable).

◆ INSTR_CREATE_asr_sve

#define INSTR_CREATE_asr_sve (   dc,
  Zd,
  Zn,
  imm 
)    instr_create_1dst_2src(dc, OP_asr, Zd, Zn, imm)

Creates an ASR instruction.

This macro is used to encode the forms:

*    ASR     <Zd>.<Ts>, <Zn>.<Ts>, #<const>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe destination vector register, Z (Scalable).
ZnThe first source vector register, Z (Scalable).
immThe immediate imm, one indexed.

◆ INSTR_CREATE_asr_sve_pred

#define INSTR_CREATE_asr_sve_pred (   dc,
  Zdn,
  Pg,
  Zm 
)    instr_create_1dst_3src(dc, OP_asr, Zdn, Pg, Zdn, Zm)

Creates an ASR instruction.

This macro is used to encode the forms:

*    ASR     <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_asr_sve_pred_wide

#define INSTR_CREATE_asr_sve_pred_wide (   dc,
  Zdn,
  Pg,
  Zm 
)    instr_create_1dst_3src(dc, OP_asr, Zdn, Pg, Zdn, Zm)

Creates an ASR instruction.

This macro is used to encode the forms:

*    ASR     <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.D
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_asr_sve_wide

#define INSTR_CREATE_asr_sve_wide (   dc,
  Zd,
  Zn,
  Zm 
)    instr_create_1dst_2src(dc, OP_asr, Zd, Zn, Zm)

Creates an ASR instruction.

This macro is used to encode the forms:

*    ASR     <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.D
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe destination vector register, Z (Scalable).
ZnThe first source vector register, Z (Scalable).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_asrd_sve_pred

#define INSTR_CREATE_asrd_sve_pred (   dc,
  Zdn,
  Pg,
  imm 
)    instr_create_1dst_3src(dc, OP_asrd, Zdn, Pg, Zdn, imm)

Creates an ASRD instruction.

This macro is used to encode the forms:

*    ASRD    <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, #<const>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
immThe immediate imm, one indexed.

◆ INSTR_CREATE_asrr_sve_pred

#define INSTR_CREATE_asrr_sve_pred (   dc,
  Zdn,
  Pg,
  Zm 
)    instr_create_1dst_3src(dc, OP_asrr, Zdn, Pg, Zdn, Zm)

Creates an ASRR instruction.

This macro is used to encode the forms:

*    ASRR    <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_bcax

#define INSTR_CREATE_bcax (   dc,
  Rd,
  Rn,
  Rm,
  Ra 
)    instr_create_1dst_4src(dc, OP_bcax, Rd, Rn, Rm, Ra, OPND_CREATE_BYTE())

Creates a BCAX instruction.

This macro is used to encode the forms:

*    BCAX    <Bd>.16B, <Bn>.16B, <Bm>.16B, <Ba>.16B
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register, Q (quadword, 128 bits)
RnThe second source vector register, Q (quadword, 128 bits)
RmThe third source vector register, Q (quadword, 128 bits)
RaThe fourth source vector register, Q (quadword, 128 bits)

◆ INSTR_CREATE_bcond

#define INSTR_CREATE_bcond (   dc,
  pc 
)    instr_create_0dst_1src((dc), OP_bcond, (pc))

disabled_until_i4106_is_fixed This macro creates an instr_t for a conditional branch instruction. The condition can be set using INSTR_PRED macro.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
pcThe opnd_t target operand containing the program counter to jump to.

◆ INSTR_CREATE_bic_sve

#define INSTR_CREATE_bic_sve (   dc,
  Zd,
  Zn,
  Zm 
)    instr_create_1dst_2src(dc, OP_bic, Zd, Zn, Zm)

Creates a BIC instruction.

This macro is used to encode the forms:

*    BIC     <Zd>.D, <Zn>.D, <Zm>.D
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe destination vector register, Z (Scalable).
ZnThe first source vector register, Z (Scalable).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_bic_sve_imm

#define INSTR_CREATE_bic_sve_imm (   dc,
  Zdn,
  imm 
)    instr_create_1dst_2src(dc, OP_and, Zdn, Zdn, opnd_invert_immed_int(imm))

Creates a BIC instruction.

This macro is used to encode the forms:

*    BIC     <Zdn>.<T>, <Zdn>.<T>, #<imm>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
immThe immediate logicalImm. The 13 bit immediate defining a 64, 32, 16 or 8 bit mask of 2, 4, 8, 16, 32 or 64 bit fields.

◆ INSTR_CREATE_bic_sve_pred

#define INSTR_CREATE_bic_sve_pred (   dc,
  Zd,
  Pg,
  Zd_,
  Zm,
  width 
)    instr_create_1dst_4src(dc, OP_bic, Zd, Pg, Zd_, Zm, width)

Creates a BIC scalable vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe output SVE vector register.
PgPredicate register for predicated instruction, P0-P7.
Zd_The first input SVE vector register. Must match Zd.
ZmThe second input SVE vector register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_bic_sve_pred_b

#define INSTR_CREATE_bic_sve_pred_b (   dc,
  Pd,
  Pg,
  Pn,
  Pm 
)    instr_create_1dst_3src(dc, OP_bic, Pd, Pg, Pn, Pm)

Creates a BIC instruction.

This macro is used to encode the forms:

*    BIC     <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate).
PgThe governing predicate register, P (Predicate).
PnThe first source predicate register, P (Predicate).
PmThe second source predicate register, P (Predicate).

◆ INSTR_CREATE_bic_vector

#define INSTR_CREATE_bic_vector (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_bic, Rd, Rm, Rn)

Creates a BIC vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_bics_sve_pred

#define INSTR_CREATE_bics_sve_pred (   dc,
  Pd,
  Pg,
  Pn,
  Pm 
)    instr_create_1dst_3src(dc, OP_bics, Pd, Pg, Pn, Pm)

Creates a BICS instruction.

This macro is used to encode the forms:

*    BICS    <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate).
PgThe governing predicate register, P (Predicate).
PnThe first source predicate register, P (Predicate).
PmThe second source predicate register, P (Predicate).

◆ INSTR_CREATE_bif_vector

#define INSTR_CREATE_bif_vector (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_bif, Rd, Rm, Rn)

Creates a BIF vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_bit_vector

#define INSTR_CREATE_bit_vector (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_bit, Rd, Rm, Rn)

Creates a BIT vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_bl

#define INSTR_CREATE_bl (   dc,
  pc 
)    instr_create_1dst_1src((dc), OP_bl, opnd_create_reg(DR_REG_X30), (pc))

This macro creates an instr_t for a BL (branch and link) instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
pcThe opnd_t target operand containing the program counter to jump to.

◆ INSTR_CREATE_brka_sve_pred

#define INSTR_CREATE_brka_sve_pred (   dc,
  Pd,
  Pg,
  Pn 
)    instr_create_1dst_2src(dc, OP_brka, Pd, Pg, Pn)

Creates a BRKA instruction.

This macro is used to encode the forms:

*    BRKA    <Pd>.B, <Pg>/<ZM>, <Pn>.B
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate).
PgThe governing predicate register, P (Predicate).
PnThe source predicate register, P (Predicate).

◆ INSTR_CREATE_brkas_sve_pred

#define INSTR_CREATE_brkas_sve_pred (   dc,
  Pd,
  Pg,
  Pn 
)    instr_create_1dst_2src(dc, OP_brkas, Pd, Pg, Pn)

Creates a BRKAS instruction.

This macro is used to encode the forms:

*    BRKAS   <Pd>.B, <Pg>/Z, <Pn>.B
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate).
PgThe governing predicate register, P (Predicate).
PnThe source predicate register, P (Predicate).

◆ INSTR_CREATE_brkb_sve_pred

#define INSTR_CREATE_brkb_sve_pred (   dc,
  Pd,
  Pg,
  Pn 
)    instr_create_1dst_2src(dc, OP_brkb, Pd, Pg, Pn)

Creates a BRKB instruction.

This macro is used to encode the forms:

*    BRKB    <Pd>.B, <Pg>/<ZM>, <Pn>.B
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate).
PgThe governing predicate register, P (Predicate).
PnThe source predicate register, P (Predicate).

◆ INSTR_CREATE_brkbs_sve_pred

#define INSTR_CREATE_brkbs_sve_pred (   dc,
  Pd,
  Pg,
  Pn 
)    instr_create_1dst_2src(dc, OP_brkbs, Pd, Pg, Pn)

Creates a BRKBS instruction.

This macro is used to encode the forms:

*    BRKBS   <Pd>.B, <Pg>/Z, <Pn>.B
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate).
PgThe governing predicate register, P (Predicate).
PnThe source predicate register, P (Predicate).

◆ INSTR_CREATE_brkn_sve_pred

#define INSTR_CREATE_brkn_sve_pred (   dc,
  Pdm,
  Pg,
  Pn 
)    instr_create_1dst_3src(dc, OP_brkn, Pdm, Pg, Pn, Pdm)

Creates a BRKN instruction.

This macro is used to encode the forms:

*    BRKN    <Pdm>.B, <Pg>/Z, <Pn>.B, <Pdm>.B
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdmThe second source and destination predicate register, P (Predicate).
PgThe governing predicate register, P (Predicate).
PnThe first source predicate register, P (Predicate).

◆ INSTR_CREATE_brkns_sve_pred

#define INSTR_CREATE_brkns_sve_pred (   dc,
  Pdm,
  Pg,
  Pn 
)    instr_create_1dst_3src(dc, OP_brkns, Pdm, Pg, Pn, Pdm)

Creates a BRKNS instruction.

This macro is used to encode the forms:

*    BRKNS   <Pdm>.B, <Pg>/Z, <Pn>.B, <Pdm>.B
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdmThe second source and destination predicate register, P (Predicate).
PgThe governing predicate register, P (Predicate).
PnThe first source predicate register, P (Predicate).

◆ INSTR_CREATE_brkpa_sve_pred

#define INSTR_CREATE_brkpa_sve_pred (   dc,
  Pd,
  Pg,
  Pn,
  Pm 
)    instr_create_1dst_3src(dc, OP_brkpa, Pd, Pg, Pn, Pm)

Creates a BRKPA instruction.

This macro is used to encode the forms:

*    BRKPA   <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate).
PgThe governing predicate register, P (Predicate).
PnThe first source predicate register, P (Predicate).
PmThe second source predicate register, P (Predicate).

◆ INSTR_CREATE_brkpas_sve_pred

#define INSTR_CREATE_brkpas_sve_pred (   dc,
  Pd,
  Pg,
  Pn,
  Pm 
)    instr_create_1dst_3src(dc, OP_brkpas, Pd, Pg, Pn, Pm)

Creates a BRKPAS instruction.

This macro is used to encode the forms:

*    BRKPAS  <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate).
PgThe governing predicate register, P (Predicate).
PnThe first source predicate register, P (Predicate).
PmThe second source predicate register, P (Predicate).

◆ INSTR_CREATE_brkpb_sve_pred

#define INSTR_CREATE_brkpb_sve_pred (   dc,
  Pd,
  Pg,
  Pn,
  Pm 
)    instr_create_1dst_3src(dc, OP_brkpb, Pd, Pg, Pn, Pm)

Creates a BRKPB instruction.

This macro is used to encode the forms:

*    BRKPB   <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate).
PgThe governing predicate register, P (Predicate).
PnThe first source predicate register, P (Predicate).
PmThe second source predicate register, P (Predicate).

◆ INSTR_CREATE_brkpbs_sve_pred

#define INSTR_CREATE_brkpbs_sve_pred (   dc,
  Pd,
  Pg,
  Pn,
  Pm 
)    instr_create_1dst_3src(dc, OP_brkpbs, Pd, Pg, Pn, Pm)

Creates a BRKPBS instruction.

This macro is used to encode the forms:

*    BRKPBS  <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate).
PgThe governing predicate register, P (Predicate).
PnThe first source predicate register, P (Predicate).
PmThe second source predicate register, P (Predicate).

◆ INSTR_CREATE_bsl_vector

#define INSTR_CREATE_bsl_vector (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_bsl, Rd, Rm, Rn)

Creates a BSL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_ccmn

#define INSTR_CREATE_ccmn (   dc,
  Rn,
  Op,
  nzcv,
  cond 
)    (INSTR_PRED(instr_create_0dst_3src(dc, OP_ccmn, Rn, Op, nzcv), (cond)))

Creates a CCMN (Conditional Compare Negative) instruction. Sets the NZCV flags to the result of a comparison of its two source values if the named input condition is true, or to an immediate value if the input condition is false. The comparison is based on a negated second source value (Op) if an immediate, inverted if a register.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
condThe comparison condition specified by dr_pred_type_t, e.g. DR_PRED_EQ.
RnThe GPR source register.
OpEither a 5-bit immediate (use opnd_create_immed_uint() to create the operand, e.g. opnd_create_immed_uint(val, OPSZ_5b)) or a GPR source register.
nzcvThe 4 bit NZCV flags value used if the input condition is false. (use opnd_create_immed_uint() to create the operand, e.g. opnd_create_immed_uint(val, OPSZ_4b)).

◆ INSTR_CREATE_ccmp

#define INSTR_CREATE_ccmp (   dc,
  Rn,
  Op,
  nzcv,
  cond 
)    (INSTR_PRED(instr_create_0dst_3src(dc, OP_ccmp, Rn, Op, nzcv), (cond)))

Creates a CCMP (Conditional Compare) instruction. Sets the NZCV flags to the result of a comparison of its two source values if the named input condition is true, or to an immediate value if the input condition is false.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
condThe comparison condition specified by dr_pred_type_t, e.g. DR_PRED_EQ.
RnThe GPR source register.
OpEither a 5-bit immediate (use opnd_create_immed_uint() to create the operand, e.g. opnd_create_immed_uint(val, OPSZ_5b)) or a GPR source register.
nzcvThe 4 bit NZCV flags value used if the input condition is false. (use opnd_create_immed_uint() to create the operand, e.g. opnd_create_immed_uint(val, OPSZ_4b)).

◆ INSTR_CREATE_clasta_sve_scalar

#define INSTR_CREATE_clasta_sve_scalar (   dc,
  Rdn,
  Pg,
  Zm 
)    instr_create_1dst_3src(dc, OP_clasta, Rdn, Pg, Rdn, Zm)

Creates a CLASTA instruction.

This macro is used to encode the forms:

*    CLASTA  <R><dn>, <Pg>, <R><dn>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdnThe first source and destination register. Can be W (Word, 32 bits) or X (Extended, 64 bits).
PgThe governing predicate register, P (Predicate).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_clasta_sve_simd_fp

#define INSTR_CREATE_clasta_sve_simd_fp (   dc,
  Vdn,
  Pg,
  Zm 
)    instr_create_1dst_3src(dc, OP_clasta, Vdn, Pg, Vdn, Zm)

Creates a CLASTA instruction.

This macro is used to encode the forms:

*    CLASTA  <V><dn>, <Pg>, <V><dn>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdnThe first source and destination register. Can be D (doubleword, 64 bits), S (singleword, 32 bits), H (halfword, 16 bits) or B (byte, 8 bits).
PgThe governing predicate register, P (Predicate).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_clasta_sve_vector

#define INSTR_CREATE_clasta_sve_vector (   dc,
  Zdn,
  Pg,
  Zm 
)    instr_create_1dst_3src(dc, OP_clasta, Zdn, Pg, Zdn, Zm)

Creates a CLASTA instruction.

This macro is used to encode the forms:

*    CLASTA  <Zdn>.<Ts>, <Pg>, <Zdn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_clastb_sve_scalar

#define INSTR_CREATE_clastb_sve_scalar (   dc,
  Rdn,
  Pg,
  Zm 
)    instr_create_1dst_3src(dc, OP_clastb, Rdn, Pg, Rdn, Zm)

Creates a CLASTB instruction.

This macro is used to encode the forms:

*    CLASTB  <R><dn>, <Pg>, <R><dn>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdnThe first source and destination register. Can be W (Word, 32 bits) or X (Extended, 64 bits).
PgThe governing predicate register, P (Predicate).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_clastb_sve_simd_fp

#define INSTR_CREATE_clastb_sve_simd_fp (   dc,
  Vdn,
  Pg,
  Zm 
)    instr_create_1dst_3src(dc, OP_clastb, Vdn, Pg, Vdn, Zm)

Creates a CLASTB instruction.

This macro is used to encode the forms:

*    CLASTB  <V><dn>, <Pg>, <V><dn>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdnThe first source and destination register. Can be D (doubleword, 64 bits), S (singleword, 32 bits), H (halfword, 16 bits) or B (byte, 8 bits).
PgThe governing predicate register, P (Predicate).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_clastb_sve_vector

#define INSTR_CREATE_clastb_sve_vector (   dc,
  Zdn,
  Pg,
  Zm 
)    instr_create_1dst_3src(dc, OP_clastb, Zdn, Pg, Zdn, Zm)

Creates a CLASTB instruction.

This macro is used to encode the forms:

*    CLASTB  <Zdn>.<Ts>, <Pg>, <Zdn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_cls_sve_pred

#define INSTR_CREATE_cls_sve_pred (   dc,
  Zd,
  Pg,
  Zn 
)    instr_create_1dst_2src(dc, OP_cls, Zd, Pg, Zn)

Creates a CLS instruction.

This macro is used to encode the forms:

*    CLS     <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZnThe source vector register, Z (Scalable).

◆ INSTR_CREATE_clz_sve_pred

#define INSTR_CREATE_clz_sve_pred (   dc,
  Zd,
  Pg,
  Zn 
)    instr_create_1dst_2src(dc, OP_clz, Zd, Pg, Zn)

Creates a CLZ instruction.

This macro is used to encode the forms:

*    CLZ     <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZnThe source vector register, Z (Scalable).

◆ INSTR_CREATE_cmeq_vector

#define INSTR_CREATE_cmeq_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_cmeq, Rd, Rm, Rn, width)

Creates a CMEQ vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_cmge_vector

#define INSTR_CREATE_cmge_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_cmge, Rd, Rm, Rn, width)

Creates a CMGE vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_cmgt_vector

#define INSTR_CREATE_cmgt_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_cmgt, Rd, Rm, Rn, width)

Creates a CMGT vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_cmhi_vector

#define INSTR_CREATE_cmhi_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_cmhi, Rd, Rm, Rn, width)

Creates a CMHI vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_cmhs_vector

#define INSTR_CREATE_cmhs_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_cmhs, Rd, Rm, Rn, width)

Creates a CMHS vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_cmpeq_sve_pred

#define INSTR_CREATE_cmpeq_sve_pred (   dc,
  Pd,
  Pg,
  Zn,
  Zm 
)    instr_create_1dst_3src(dc, OP_cmpeq, Pd, Pg, Zn, Zm)

Creates a CMPEQ instruction.

This macro is used to encode the forms:

*    CMPEQ   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D
*    CMPEQ   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe first source vector register, Z (Scalable)
ZmThe second source vector register, Z (Scalable)

◆ INSTR_CREATE_cmpeq_sve_pred_simm

#define INSTR_CREATE_cmpeq_sve_pred_simm (   dc,
  Pd,
  Pg,
  Zn,
  simm 
)    instr_create_1dst_3src(dc, OP_cmpeq, Pd, Pg, Zn, simm)

Creates a CMPEQ instruction.

This macro is used to encode the forms:

*    CMPEQ   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe source vector register, Z (Scalable)
simmThe signed immediate imm

◆ INSTR_CREATE_cmpge_sve_pred

#define INSTR_CREATE_cmpge_sve_pred (   dc,
  Pd,
  Pg,
  Zn,
  Zm 
)    instr_create_1dst_3src(dc, OP_cmpge, Pd, Pg, Zn, Zm)

Creates a CMPGE instruction.

This macro is used to encode the forms:

*    CMPGE   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D
*    CMPGE   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe first source vector register, Z (Scalable)
ZmThe second source vector register, Z (Scalable)

◆ INSTR_CREATE_cmpge_sve_pred_simm

#define INSTR_CREATE_cmpge_sve_pred_simm (   dc,
  Pd,
  Pg,
  Zn,
  simm 
)    instr_create_1dst_3src(dc, OP_cmpge, Pd, Pg, Zn, simm)

Creates a CMPGE instruction.

This macro is used to encode the forms:

*    CMPGE   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe source vector register, Z (Scalable)
simmThe signed immediate imm

◆ INSTR_CREATE_cmpgt_sve_pred

#define INSTR_CREATE_cmpgt_sve_pred (   dc,
  Pd,
  Pg,
  Zn,
  Zm 
)    instr_create_1dst_3src(dc, OP_cmpgt, Pd, Pg, Zn, Zm)

Creates a CMPGT instruction.

This macro is used to encode the forms:

*    CMPGT   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D
*    CMPGT   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe first source vector register, Z (Scalable)
ZmThe second source vector register, Z (Scalable)

◆ INSTR_CREATE_cmpgt_sve_pred_simm

#define INSTR_CREATE_cmpgt_sve_pred_simm (   dc,
  Pd,
  Pg,
  Zn,
  simm 
)    instr_create_1dst_3src(dc, OP_cmpgt, Pd, Pg, Zn, simm)

Creates a CMPGT instruction.

This macro is used to encode the forms:

*    CMPGT   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe source vector register, Z (Scalable)
simmThe signed immediate imm

◆ INSTR_CREATE_cmphi_sve_pred

#define INSTR_CREATE_cmphi_sve_pred (   dc,
  Pd,
  Pg,
  Zn,
  Zm 
)    instr_create_1dst_3src(dc, OP_cmphi, Pd, Pg, Zn, Zm)

Creates a CMPHI instruction.

This macro is used to encode the forms:

*    CMPHI   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D
*    CMPHI   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe first source vector register, Z (Scalable)
ZmThe second source vector register, Z (Scalable)

◆ INSTR_CREATE_cmphi_sve_pred_imm

#define INSTR_CREATE_cmphi_sve_pred_imm (   dc,
  Pd,
  Pg,
  Zn,
  imm 
)    instr_create_1dst_3src(dc, OP_cmphi, Pd, Pg, Zn, imm)

Creates a CMPHI instruction.

This macro is used to encode the forms:

*    CMPHI   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe source vector register, Z (Scalable)
immThe immediate imm

◆ INSTR_CREATE_cmphs_sve_pred

#define INSTR_CREATE_cmphs_sve_pred (   dc,
  Pd,
  Pg,
  Zn,
  Zm 
)    instr_create_1dst_3src(dc, OP_cmphs, Pd, Pg, Zn, Zm)

Creates a CMPHS instruction.

This macro is used to encode the forms:

*    CMPHS   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D
*    CMPHS   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe first source vector register, Z (Scalable)
ZmThe second source vector register, Z (Scalable)

◆ INSTR_CREATE_cmphs_sve_pred_imm

#define INSTR_CREATE_cmphs_sve_pred_imm (   dc,
  Pd,
  Pg,
  Zn,
  imm 
)    instr_create_1dst_3src(dc, OP_cmphs, Pd, Pg, Zn, imm)

Creates a CMPHS instruction.

This macro is used to encode the forms:

*    CMPHS   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe source vector register, Z (Scalable)
immThe immediate imm

◆ INSTR_CREATE_cmple_sve_pred

#define INSTR_CREATE_cmple_sve_pred (   dc,
  Pd,
  Pg,
  Zn,
  Zm 
)    instr_create_1dst_3src(dc, OP_cmple, Pd, Pg, Zn, Zm)

Creates a CMPLE instruction.

This macro is used to encode the forms:

*    CMPLE   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe first source vector register, Z (Scalable)
ZmThe second source vector register, Z (Scalable)

◆ INSTR_CREATE_cmple_sve_pred_simm

#define INSTR_CREATE_cmple_sve_pred_simm (   dc,
  Pd,
  Pg,
  Zn,
  simm 
)    instr_create_1dst_3src(dc, OP_cmple, Pd, Pg, Zn, simm)

Creates a CMPLE instruction.

This macro is used to encode the forms:

*    CMPLE   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe source vector register, Z (Scalable)
simmThe signed immediate imm

◆ INSTR_CREATE_cmplo_sve_pred

#define INSTR_CREATE_cmplo_sve_pred (   dc,
  Pd,
  Pg,
  Zn,
  Zm 
)    instr_create_1dst_3src(dc, OP_cmplo, Pd, Pg, Zn, Zm)

Creates a CMPLO instruction.

This macro is used to encode the forms:

*    CMPLO   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe first source vector register, Z (Scalable)
ZmThe second source vector register, Z (Scalable)

◆ INSTR_CREATE_cmplo_sve_pred_imm

#define INSTR_CREATE_cmplo_sve_pred_imm (   dc,
  Pd,
  Pg,
  Zn,
  imm 
)    instr_create_1dst_3src(dc, OP_cmplo, Pd, Pg, Zn, imm)

Creates a CMPLO instruction.

This macro is used to encode the forms:

*    CMPLO   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe source vector register, Z (Scalable)
immThe immediate imm

◆ INSTR_CREATE_cmpls_sve_pred

#define INSTR_CREATE_cmpls_sve_pred (   dc,
  Pd,
  Pg,
  Zn,
  Zm 
)    instr_create_1dst_3src(dc, OP_cmpls, Pd, Pg, Zn, Zm)

Creates a CMPLS instruction.

This macro is used to encode the forms:

*    CMPLS   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe first source vector register, Z (Scalable)
ZmThe second source vector register, Z (Scalable)

◆ INSTR_CREATE_cmpls_sve_pred_imm

#define INSTR_CREATE_cmpls_sve_pred_imm (   dc,
  Pd,
  Pg,
  Zn,
  imm 
)    instr_create_1dst_3src(dc, OP_cmpls, Pd, Pg, Zn, imm)

Creates a CMPLS instruction.

This macro is used to encode the forms:

*    CMPLS   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe source vector register, Z (Scalable)
immThe immediate imm

◆ INSTR_CREATE_cmplt_sve_pred

#define INSTR_CREATE_cmplt_sve_pred (   dc,
  Pd,
  Pg,
  Zn,
  Zm 
)    instr_create_1dst_3src(dc, OP_cmplt, Pd, Pg, Zn, Zm)

Creates a CMPLT instruction.

This macro is used to encode the forms:

*    CMPLT   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe first source vector register, Z (Scalable)
ZmThe second source vector register, Z (Scalable)

◆ INSTR_CREATE_cmplt_sve_pred_simm

#define INSTR_CREATE_cmplt_sve_pred_simm (   dc,
  Pd,
  Pg,
  Zn,
  simm 
)    instr_create_1dst_3src(dc, OP_cmplt, Pd, Pg, Zn, simm)

Creates a CMPLT instruction.

This macro is used to encode the forms:

*    CMPLT   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe source vector register, Z (Scalable)
simmThe signed immediate imm

◆ INSTR_CREATE_cmpne_sve_pred

#define INSTR_CREATE_cmpne_sve_pred (   dc,
  Pd,
  Pg,
  Zn,
  Zm 
)    instr_create_1dst_3src(dc, OP_cmpne, Pd, Pg, Zn, Zm)

Creates a CMPNE instruction.

This macro is used to encode the forms:

*    CMPNE   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D
*    CMPNE   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe first source vector register, Z (Scalable)
ZmThe second source vector register, Z (Scalable)

◆ INSTR_CREATE_cmpne_sve_pred_simm

#define INSTR_CREATE_cmpne_sve_pred_simm (   dc,
  Pd,
  Pg,
  Zn,
  simm 
)    instr_create_1dst_3src(dc, OP_cmpne, Pd, Pg, Zn, simm)

Creates a CMPNE instruction.

This macro is used to encode the forms:

*    CMPNE   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe source vector register, Z (Scalable)
simmThe signed immediate imm

◆ INSTR_CREATE_cmtst_vector

#define INSTR_CREATE_cmtst_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_cmtst, Rd, Rm, Rn, width)

Creates a CMTST vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_cnot_sve_pred

#define INSTR_CREATE_cnot_sve_pred (   dc,
  Zd,
  Pg,
  Zn 
)    instr_create_1dst_2src(dc, OP_cnot, Zd, Pg, Zn)

Creates a CNOT instruction.

This macro is used to encode the forms:

*    CNOT    <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe destination vector register, Z (Scalable)
PgThe governing predicate register, P (Predicate)
ZnThe source vector register, Z (Scalable)

◆ INSTR_CREATE_cnt_sve_pred [1/2]

#define INSTR_CREATE_cnt_sve_pred (   dc,
  Zd,
  Pg,
  Zn 
)    instr_create_1dst_2src(dc, OP_cnt, Zd, Pg, Zn)

Creates a CNT instruction.

This macro is used to encode the forms:

*    CNT     <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZnThe source vector register, Z (Scalable).

◆ INSTR_CREATE_cnt_sve_pred [2/2]

#define INSTR_CREATE_cnt_sve_pred (   dc,
  Zd,
  Pg,
  Zn 
)    instr_create_1dst_2src(dc, OP_cnt, Zd, Pg, Zn)

Creates a CNT instruction.

This macro is used to encode the forms:

*    CNT     <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZnThe source vector register, Z (Scalable).

◆ INSTR_CREATE_cntb

#define INSTR_CREATE_cntb (   dc,
  Rd,
  pattern,
  imm 
)    instr_create_1dst_3src(dc, OP_cntb, Rd, pattern, OPND_CREATE_MUL(), imm)

Creates a CNTB instruction.

This macro is used to encode the forms:

*    CNTB    <Xd>{, <pattern>{, MUL #<imm>}}
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register, X (Extended, 64 bits).
patternThe predicate constraint, see dr_pred_constr_type_t.
immThe imm used as the predicate constraint multiplier.

◆ INSTR_CREATE_cntd

#define INSTR_CREATE_cntd (   dc,
  Rd,
  pattern,
  imm 
)    instr_create_1dst_3src(dc, OP_cntd, Rd, pattern, OPND_CREATE_MUL(), imm)

Creates a CNTD instruction.

This macro is used to encode the forms:

*    CNTD    <Xd>{, <pattern>{, MUL #<imm>}}
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register, X (Extended, 64 bits).
patternThe predicate constraint, see dr_pred_constr_type_t.
immThe imm used as the predicate constraint multiplier.

◆ INSTR_CREATE_cnth

#define INSTR_CREATE_cnth (   dc,
  Rd,
  pattern,
  imm 
)    instr_create_1dst_3src(dc, OP_cnth, Rd, pattern, OPND_CREATE_MUL(), imm)

Creates a CNTH instruction.

This macro is used to encode the forms:

*    CNTH    <Xd>{, <pattern>{, MUL #<imm>}}
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register, X (Extended, 64 bits).
patternThe predicate constraint, see dr_pred_constr_type_t.
immThe imm used as the predicate constraint multiplier.

◆ INSTR_CREATE_cntp_sve_pred

#define INSTR_CREATE_cntp_sve_pred (   dc,
  Rd,
  Pg,
  Pn 
)    instr_create_1dst_2src(dc, OP_cntp, Rd, Pg, Pn)

Creates a CNTP instruction.

This macro is used to encode the forms:

*    CNTP    <Xd>, <Pg>, <Pn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register, X (Extended, 64 bits).
PgThe governing predicate register, P (Predicate).
PnThe source predicate register, P (Predicate).

◆ INSTR_CREATE_cntw

#define INSTR_CREATE_cntw (   dc,
  Rd,
  pattern,
  imm 
)    instr_create_1dst_3src(dc, OP_cntw, Rd, pattern, OPND_CREATE_MUL(), imm)

Creates a CNTW instruction.

This macro is used to encode the forms:

*    CNTW    <Xd>{, <pattern>{, MUL #<imm>}}
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe destination register, X (Extended, 64 bits).
patternThe predicate constraint, see dr_pred_constr_type_t.
immThe imm used as the predicate constraint multiplier.

◆ INSTR_CREATE_compact_sve

#define INSTR_CREATE_compact_sve (   dc,
  Zd,
  Pg,
  Zn 
)    instr_create_1dst_2src(dc, OP_compact, Zd, Pg, Zn)

Creates a COMPACT instruction.

This macro is used to encode the forms:

*    COMPACT <Zd>.<Ts>, <Pg>, <Zn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZnThe source vector register, Z (Scalable).

◆ INSTR_CREATE_cpy_sve_pred

#define INSTR_CREATE_cpy_sve_pred (   dc,
  Zd,
  Pg,
  Rn_or_Vn 
)    instr_create_1dst_2src(dc, OP_cpy, Zd, Pg, Rn_or_Vn)

Creates a CPY instruction.

This macro is used to encode the forms:

*    CPY     <Zd>.<T>, <Pg>/M, <R><n|SP>
*    CPY     <Zd>.<T>, <Pg>/M, <V><n>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe first destination vector register, Z (Scalable)
PgThe governing predicate register, P (Predicate)
Rn_or_VnThe source register. Can be a general purpose register W (Word, 32 bits) or X (Extended, 64 bits), or a vector register B (Byte, 8 bits), H (Halfword, 16 bits), S (Singleword, 32 bits), or D (Doubleword, 64 bits).

◆ INSTR_CREATE_cpy_sve_shift_pred

#define INSTR_CREATE_cpy_sve_shift_pred (   dc,
  Zd,
  Pg,
  simm,
  shift 
)    instr_create_1dst_4src(dc, OP_cpy, Zd, Pg, simm, OPND_CREATE_LSL(), shift)

Creates a CPY instruction.

This macro is used to encode the forms:

*    CPY     <Zd>.<Ts>, <Pg>/Z, #<simm>, <shift>
*    CPY     <Zd>.<Ts>, <Pg>/M, #<simm>, <shift>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe first destination vector register, Z (Scalable)
PgThe governing predicate register, P (Predicate)
simmThe signed immediate imm
shiftThe immediate shiftOp for simm

◆ INSTR_CREATE_ctermeq

#define INSTR_CREATE_ctermeq (   dc,
  Rn,
  Rm 
)    instr_create_0dst_2src(dc, OP_ctermeq, Rn, Rm)

Creates a CTERMEQ instruction.

This macro is used to encode the forms:

*    CTERMEQ <R><n>, <R><m>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RnThe first source register. Can be X (Extended, 64 bits) or W (Word, 32 bits).
RmThe second source register. Can be X (Extended, 64 bits) or W (Word, 32 bits).

◆ INSTR_CREATE_ctermne

#define INSTR_CREATE_ctermne (   dc,
  Rn,
  Rm 
)    instr_create_0dst_2src(dc, OP_ctermne, Rn, Rm)

Creates a CTERMNE instruction.

This macro is used to encode the forms:

*    CTERMNE <R><n>, <R><m>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RnThe first source register. Can be X (Extended, 64 bits) or W (Word, 32 bits).
RmThe second source register. Can be X (Extended, 64 bits) or W (Word, 32 bits).

◆ INSTR_CREATE_decb

#define INSTR_CREATE_decb (   dc,
  Rdn,
  pattern,
  imm 
)    instr_create_1dst_4src(dc, OP_decb, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)

Creates a DECB instruction.

This macro is used to encode the forms:

*    DECB    <Xdn>{, <pattern>{, MUL #<imm>}}
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdnThe GPR register to be decremented, X (Extended, 64 bits).
patternThe predicate constraint, see dr_pred_constr_type_t.
immThe imm used as the predicate constraint multiplier.

◆ INSTR_CREATE_decd

#define INSTR_CREATE_decd (   dc,
  Rdn,
  pattern,
  imm 
)    instr_create_1dst_4src(dc, OP_decd, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)

Creates a DECD instruction.

This macro is used to encode the forms:

*    DECD    <Xdn>{, <pattern>{, MUL #<imm>}}
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdnThe GPR register to be decremented, X (Extended, 64 bits).
patternThe predicate constraint, see dr_pred_constr_type_t.
immThe imm used as the predicate constraint multiplier.

◆ INSTR_CREATE_decd_sve

#define INSTR_CREATE_decd_sve (   dc,
  Zdn,
  pattern,
  imm 
)    instr_create_1dst_4src(dc, OP_decd, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm)

Creates a DECD instruction.

This macro is used to encode the forms:

*    DECD    <Zdn>.D{, <pattern>{, MUL #<imm>}}
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe vector register to be decremented, Z (Scalable).
patternThe predicate constraint, see dr_pred_constr_type_t.
immThe imm used as the predicate constraint multiplier.

◆ INSTR_CREATE_dech

#define INSTR_CREATE_dech (   dc,
  Rdn,
  pattern,
  imm 
)    instr_create_1dst_4src(dc, OP_dech, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)

Creates a DECH instruction.

This macro is used to encode the forms:

*    DECH    <Xdn>{, <pattern>{, MUL #<imm>}}
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdnThe GPR register to be decremented, X (Extended, 64 bits).
patternThe predicate constraint, see dr_pred_constr_type_t.
immThe imm used as the predicate constraint multiplier.

◆ INSTR_CREATE_dech_sve

#define INSTR_CREATE_dech_sve (   dc,
  Zdn,
  pattern,
  imm 
)    instr_create_1dst_4src(dc, OP_dech, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm)

Creates a DECH instruction.

This macro is used to encode the forms:

*    DECH    <Zdn>.H{, <pattern>{, MUL #<imm>}}
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe vector register to be decremented, Z (Scalable).
patternThe predicate constraint, see dr_pred_constr_type_t.
immThe imm used as the predicate constraint multiplier.

◆ INSTR_CREATE_decp_sve

#define INSTR_CREATE_decp_sve (   dc,
  Rdn,
  Pm 
)    instr_create_1dst_2src(dc, OP_decp, Rdn, Pm, Rdn)

Creates a DECP instruction.

This macro is used to encode the forms:

*    DECP    <Xdn>, <Pm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdnThe second source and destination register, X (Extended, 64 bits).
PmThe first source predicate register, P (Predicate).

◆ INSTR_CREATE_decp_sve_vector

#define INSTR_CREATE_decp_sve_vector (   dc,
  Zdn,
  Pm 
)    instr_create_1dst_2src(dc, OP_decp, Zdn, Pm, Zdn)

Creates a DECP instruction.

This macro is used to encode the forms:

*    DECP    <Zdn>.<Ts>, <Pm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe second source and destination vector register, Z (Scalable).
PmThe first source predicate register, P (Predicate).

◆ INSTR_CREATE_decw

#define INSTR_CREATE_decw (   dc,
  Rdn,
  pattern,
  imm 
)    instr_create_1dst_4src(dc, OP_decw, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm)

Creates a DECW instruction.

This macro is used to encode the forms:

*    DECW    <Xdn>{, <pattern>{, MUL #<imm>}}
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdnThe GPR register to be decremented, X (Extended, 64 bits).
patternThe predicate constraint, see dr_pred_constr_type_t.
immThe imm used as the predicate constraint multiplier.

◆ INSTR_CREATE_decw_sve

#define INSTR_CREATE_decw_sve (   dc,
  Zdn,
  pattern,
  imm 
)    instr_create_1dst_4src(dc, OP_decw, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm)

Creates a DECW instruction.

This macro is used to encode the forms:

*    DECW    <Zdn>.S{, <pattern>{, MUL #<imm>}}
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe vector register to be decremented, Z (Scalable).
patternThe predicate constraint, see dr_pred_constr_type_t.
immThe imm used as the predicate constraint multiplier.

◆ INSTR_CREATE_dup_sve_idx

#define INSTR_CREATE_dup_sve_idx (   dc,
  Zd,
  Zn,
  index 
)    instr_create_1dst_2src(dc, OP_dup, Zd, Zn, index)

Creates a DUP instruction.

This macro is used to encode the forms:

*    DUP     <Zd>.<Ts>, <Zn>.<Ts>[<index>]
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe destination vector register, Z (Scalable).
ZnThe source vector register, Z (Scalable).
indexImmediate index of source vector. The operand size must match the encoded field size, which depends on the element size of Zd and Zn; OPSZ_6b for byte, OPSZ_5b for halfword, OPSZ_4b for singleword, OPSZ_3b for doubleword, and OPSZ_2b for quadword.

◆ INSTR_CREATE_dup_sve_scalar

#define INSTR_CREATE_dup_sve_scalar (   dc,
  Zd,
  Rn 
)    instr_create_1dst_1src(dc, OP_dup, Zd, Rn)

Creates a DUP instruction.

This macro is used to encode the forms:

*    DUP     <Zd>.<Ts>, <R><n|SP>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe destination vector register, Z (Scalable).
RnThe source vector register. Can be X (Extended, 64 bits) or W (Word, 32 bits).

◆ INSTR_CREATE_dup_sve_shift

#define INSTR_CREATE_dup_sve_shift (   dc,
  Zd,
  simm,
  shift 
)    instr_create_1dst_3src(dc, OP_dup, Zd, simm, OPND_CREATE_LSL(), shift)

Creates a DUP instruction.

This macro is used to encode the forms:

*    DUP     <Zd>.<Ts>, #<simm>, <shift>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe destination vector register, Z (Scalable).
simmThe signed immediate imm.
shiftLeft shift to apply to the immediate, defaulting to LSL #0. Can be 0 or 8

◆ INSTR_CREATE_dupm_sve

#define INSTR_CREATE_dupm_sve (   dc,
  Zd,
  imm 
)    instr_create_1dst_1src(dc, OP_dupm, Zd, imm)

Creates a DUPM instruction.

This macro is used to encode the forms:

*    DUPM    <Zd>.<Ts>, #<const>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe destination vector register, Z (Scalable).
immThe immediate logicalImm. The 13 bit immediate defining a 64, 32, 16 or 8 bit mask of 2, 4, 8, 16, 32 or 64 bit fields.

◆ INSTR_CREATE_eon_sve_imm

#define INSTR_CREATE_eon_sve_imm (   dc,
  Zdn,
  imm 
)    instr_create_1dst_2src(dc, OP_eor, Zdn, Zdn, opnd_invert_immed_int(imm))

Creates an EON instruction.

This macro is used to encode the forms:

*    EON     <Zdn>.<Ts>, <Zdn>.<Ts>, #<imm>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
immThe immediate logicalImm. The 13 bit immediate defining a 64, 32, 16 or 8 bit mask of 2, 4, 8, 16, 32 or 64 bit fields.

◆ INSTR_CREATE_eor3

#define INSTR_CREATE_eor3 (   dc,
  Rd,
  Rn,
  Rm,
  Ra 
)    instr_create_1dst_4src(dc, OP_eor3, Rd, Rn, Rm, Ra, OPND_CREATE_BYTE())

Creates a EOR3 instruction.

This macro is used to encode the forms:

*    EOR3    <Bd>.16B, <Bn>.16B, <Bm>.16B, <Ba>.16B
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register, Q (quadword, 128 bits)
RnThe second source vector register, Q (quadword, 128 bits)
RmThe third source vector register, Q (quadword, 128 bits)
RaThe fourth source vector register, Q (quadword, 128 bits)

◆ INSTR_CREATE_eor_sve

#define INSTR_CREATE_eor_sve (   dc,
  Zd,
  Zn,
  Zm 
)    instr_create_1dst_2src(dc, OP_eor, Zd, Zn, Zm)

Creates an EOR instruction.

This macro is used to encode the forms:

*    EOR     <Zd>.D, <Zn>.D, <Zm>.D
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe destination vector register, Z (Scalable).
ZnThe first source vector register, Z (Scalable).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_eor_sve_imm

#define INSTR_CREATE_eor_sve_imm (   dc,
  Zdn,
  imm 
)    instr_create_1dst_2src(dc, OP_eor, Zdn, Zdn, imm)

Creates an EOR instruction.

This macro is used to encode the forms:

*    EOR     <Zdn>.<T>, <Zdn>.<T>, #<imm>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
immThe immediate logicalImm. The 13 bit immediate defining a 64, 32, 16 or 8 bit mask of 2, 4, 8, 16, 32 or 64 bit fields.

◆ INSTR_CREATE_eor_sve_pred

#define INSTR_CREATE_eor_sve_pred (   dc,
  Zd,
  Pg,
  Zd_,
  Zm,
  width 
)    instr_create_1dst_4src(dc, OP_eor, Zd, Pg, Zd_, Zm, width)

Creates an EOR scalable vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe output SVE vector register.
PgPredicate register for predicated instruction, P0-P7.
Zd_The first input SVE vector register. Must match Zd.
ZmThe second input SVE vector register.
widthThe vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_eor_sve_pred_b

#define INSTR_CREATE_eor_sve_pred_b (   dc,
  Pd,
  Pg,
  Pn,
  Pm 
)    instr_create_1dst_3src(dc, OP_eor, Pd, Pg, Pn, Pm)

Creates an EOR instruction.

This macro is used to encode the forms:

*    EOR     <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate).
PgThe governing predicate register, P (Predicate).
PnThe first source predicate register, P (Predicate).
PmThe second source predicate register, P (Predicate).

◆ INSTR_CREATE_eor_vector

#define INSTR_CREATE_eor_vector (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_eor, Rd, Rm, Rn)

Creates a EOR vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_eors_sve_pred

#define INSTR_CREATE_eors_sve_pred (   dc,
  Pd,
  Pg,
  Pn,
  Pm 
)    instr_create_1dst_3src(dc, OP_eors, Pd, Pg, Pn, Pm)

Creates an EORS instruction.

This macro is used to encode the forms:

*    EORS    <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate).
PgThe governing predicate register, P (Predicate).
PnThe first source predicate register, P (Predicate).
PmThe second source predicate register, P (Predicate).

◆ INSTR_CREATE_eorv_sve_pred

#define INSTR_CREATE_eorv_sve_pred (   dc,
  Vd,
  Pg,
  Zn 
)    instr_create_1dst_2src(dc, OP_eorv, Vd, Pg, Zn)

Creates an EORV instruction.

This macro is used to encode the forms:

*    EORV    <V><d>, <Pg>, <Zn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits), B (byte, 8 bits) or D (doubleword, 64 bits).
PgThe governing predicate register, P (Predicate).
ZnThe source vector register, Z (Scalable).

◆ INSTR_CREATE_esb

#define INSTR_CREATE_esb (   dc)    instr_create_0dst_0src(dc, OP_esb)

Creates a ESB instruction.

This macro is used to encode the forms:

*    ESB
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.

◆ INSTR_CREATE_ext_sve

#define INSTR_CREATE_ext_sve (   dc,
  Zdn,
  Zm,
  imm 
)    instr_create_1dst_3src(dc, OP_ext, Zdn, Zdn, Zm, imm)

Creates an EXT instruction (destructive).

This macro is used to encode the forms:

*    EXT     <Zdn>.B, <Zdn>.B, <Zm>.B, #<imm>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
ZmThe second source vector register, Z (Scalable).
immThe immediate imm.

◆ INSTR_CREATE_fabd_sve

#define INSTR_CREATE_fabd_sve (   dc,
  Zdn,
  Pg,
  Zm 
)    instr_create_1dst_3src(dc, OP_fabd, Zdn, Pg, Zdn, Zm)

Creates a FABD instruction.

This macro is used to encode the forms:

*    FABD    <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_fabd_vector

#define INSTR_CREATE_fabd_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_fabd, Rd, Rm, Rn, width)

Creates a FABD vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fabs_scalar

#define INSTR_CREATE_fabs_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fabs, Rd, Rm)

Creates a FABS floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.

◆ INSTR_CREATE_fabs_sve

#define INSTR_CREATE_fabs_sve (   dc,
  Zd,
  Pg,
  Zn 
)    instr_create_1dst_2src(dc, OP_fabs, Zd, Pg, Zn)

Creates a FABS instruction.

This macro is used to encode the forms:

*    FABS    <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZnThe source vector register, Z (Scalable).

◆ INSTR_CREATE_facge

#define INSTR_CREATE_facge (   dc,
  Rd,
  Rn,
  Rm 
)    instr_create_1dst_2src(dc, OP_facge, Rd, Rn, Rm)

Creates a FACGE instruction.

This macro is used to encode the forms:

*    FACGE   <Hd>, <Hn>, <Hm>
*    FACGE   <V><d>, <V><n>, <V><m>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RmThe third source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)

◆ INSTR_CREATE_facge_sve_pred

#define INSTR_CREATE_facge_sve_pred (   dc,
  Pd,
  Pg,
  Zn,
  Zm 
)    instr_create_1dst_3src(dc, OP_facge, Pd, Pg, Zn, Zm)

Creates a FACGE instruction.

This macro is used to encode the forms:

*    FACGE   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe first source vector register, Z (Scalable)
ZmThe second source vector register, Z (Scalable)

◆ INSTR_CREATE_facge_vector

#define INSTR_CREATE_facge_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_3src(dc, OP_facge, Rd, Rn, Rm, Rm_elsz)

Creates a FACGE vector instruction.

This macro is used to encode the forms:

*    FACGE   <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts>
*    FACGE   <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_facgt

#define INSTR_CREATE_facgt (   dc,
  Rd,
  Rn,
  Rm 
)    instr_create_1dst_2src(dc, OP_facgt, Rd, Rn, Rm)

Creates a FACGT instruction.

This macro is used to encode the forms:

*    FACGT   <Hd>, <Hn>, <Hm>
*    FACGT   <V><d>, <V><n>, <V><m>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RmThe third source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)

◆ INSTR_CREATE_facgt_sve_pred

#define INSTR_CREATE_facgt_sve_pred (   dc,
  Pd,
  Pg,
  Zn,
  Zm 
)    instr_create_1dst_3src(dc, OP_facgt, Pd, Pg, Zn, Zm)

Creates a FACGT instruction.

This macro is used to encode the forms:

*    FACGT   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe first source vector register, Z (Scalable)
ZmThe second source vector register, Z (Scalable)

◆ INSTR_CREATE_facgt_vector

#define INSTR_CREATE_facgt_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_3src(dc, OP_facgt, Rd, Rn, Rm, Rm_elsz)

Creates a FACGT vector instruction.

This macro is used to encode the forms:

*    FACGT   <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts>
*    FACGT   <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fadd_scalar

#define INSTR_CREATE_fadd_scalar (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_fadd, Rd, Rm, Rn)

Creates a FADD floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_fadd_sve

#define INSTR_CREATE_fadd_sve (   dc,
  Zdn,
  Pg,
  imm 
)    instr_create_1dst_3src(dc, OP_fadd, Zdn, Pg, Zdn, imm)

Creates a FADD instruction.

This macro is used to encode the forms:

*    FADD    <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <imm>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
immFloating point constant, either 0.5 or 1.0.

◆ INSTR_CREATE_fadd_sve_pred

#define INSTR_CREATE_fadd_sve_pred (   dc,
  Zdn,
  Pg,
  Zm 
)    instr_create_1dst_3src(dc, OP_fadd, Zdn, Pg, Zdn, Zm)

Creates a FADD instruction.

This macro is used to encode the forms:

*    FADD    <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_fadd_sve_vector

#define INSTR_CREATE_fadd_sve_vector (   dc,
  Zd,
  Zn,
  Zm 
)    instr_create_1dst_2src(dc, OP_fadd, Zd, Zn, Zm)

Creates a FADD instruction.

This macro is used to encode the forms:

*    FADD    <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe destination vector register, Z (Scalable).
ZnThe first source vector register, Z (Scalable).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_fadd_vector

#define INSTR_CREATE_fadd_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_fadd, Rd, Rm, Rn, width)

Creates a FADD vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fadda_sve_pred

#define INSTR_CREATE_fadda_sve_pred (   dc,
  Vdn,
  Pg,
  Zm 
)    instr_create_1dst_3src(dc, OP_fadda, Vdn, Pg, Vdn, Zm)

Creates a FADDA instruction.

This macro is used to encode the forms:

*    FADDA   <V><dn>, <Pg>, <V><dn>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdnThe first source and destination register. Can be S (singleword, 32 bits), H (halfword, 16 bits) or D (doubleword, 64 bits).
PgThe governing predicate register, P (Predicate).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_faddp_scalar

#define INSTR_CREATE_faddp_scalar (   dc,
  Rd,
  Rn,
  Rn_elsz 
)    instr_create_1dst_2src(dc, OP_faddp, Rd, Rn, Rn_elsz)

Creates a FADDP instruction.

This macro is used to encode the forms:

*    FADDP   <Hd>, <Hn>.2H
*    FADDP   <V><d>, <Sn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rn_elszThe element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_faddp_vector

#define INSTR_CREATE_faddp_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_3src(dc, OP_faddp, Rd, Rn, Rm, Rm_elsz)

Creates a FADDP instruction.

This macro is used to encode the forms:

*    FADDP   <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts>
*    FADDP   <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_faddv_sve_pred

#define INSTR_CREATE_faddv_sve_pred (   dc,
  Vd,
  Pg,
  Zn 
)    instr_create_1dst_2src(dc, OP_faddv, Vd, Pg, Zn)

Creates a FADDV instruction.

This macro is used to encode the forms:

*    FADDV   <V><d>, <Pg>, <Zn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination register. Can be S (singleword, 32 bits), H (halfword, 16 bits) or D (doubleword, 64 bits).
PgThe governing predicate register, P (Predicate).
ZnThe source vector register, Z (Scalable).

◆ INSTR_CREATE_fccmp

#define INSTR_CREATE_fccmp (   dc,
  Rn,
  Rm,
  nzcv,
  condition_code 
)    INSTR_PRED(instr_create_0dst_3src(dc, OP_fccmp, Rn, Rm, nzcv), (condition_code))

Creates a FCCMP instruction.

This macro is used to encode the forms:

*    FCCMP   <Dn>, <Dm>, #<imm>, <cond>
*    FCCMP   <Hn>, <Hm>, #<imm>, <cond>
*    FCCMP   <Sn>, <Sm>, #<imm>, <cond>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RnThe first source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)
RmThe second source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)
nzcvThe 4 bit NZCV flags value used if the input condition is false. (use opnd_create_immed_uint() to create the operand, e.g. opnd_create_immed_uint(val, OPSZ_4b)).
condition_codeThe comparison condition specified by dr_pred_type_t, e.g. DR_PRED_EQ.

◆ INSTR_CREATE_fccmpe

#define INSTR_CREATE_fccmpe (   dc,
  Rn,
  Rm,
  nzcv,
  condition_code 
)    INSTR_PRED(instr_create_0dst_3src(dc, OP_fccmpe, Rn, Rm, nzcv), (condition_code))

Creates a FCCMPE instruction.

This macro is used to encode the forms:

*    FCCMPE   <Dn>, <Dm>, #<imm>, <cond>
*    FCCMPE   <Hn>, <Hm>, #<imm>, <cond>
*    FCCMPE   <Sn>, <Sm>, #<imm>, <cond>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RnThe first source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)
RmThe second source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)
nzcvThe 4 bit NZCV flags value used if the input condition is false. (use opnd_create_immed_uint() to create the operand, e.g. opnd_create_immed_uint(val, OPSZ_4b)).
condition_codeThe comparison condition specified by dr_pred_type_t, e.g. DR_PRED_EQ.

◆ INSTR_CREATE_fcmeq

#define INSTR_CREATE_fcmeq (   dc,
  Rd,
  Rn,
  Rm 
)    instr_create_1dst_2src(dc, OP_fcmeq, Rd, Rn, Rm)

Creates a FCMEQ instruction.

This macro is used to encode the forms:

*    FCMEQ   <Hd>, <Hn>, <Hm>
*    FCMEQ   <V><d>, <V><n>, <V><m>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RmThe third source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)

◆ INSTR_CREATE_fcmeq_sve_pred

#define INSTR_CREATE_fcmeq_sve_pred (   dc,
  Pd,
  Pg,
  Zn,
  Zm 
)    instr_create_1dst_3src(dc, OP_fcmeq, Pd, Pg, Zn, Zm)

Creates a FCMEQ instruction.

This macro is used to encode the forms:

*    FCMEQ   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe first source vector register, Z (Scalable)
ZmThe second source vector register, Z (Scalable)

◆ INSTR_CREATE_fcmeq_sve_zero_pred

#define INSTR_CREATE_fcmeq_sve_zero_pred (   dc,
  Pd,
  Pg,
  Zn 
)    instr_create_1dst_3src(dc, OP_fcmeq, Pd, Pg, Zn, opnd_create_immed_float(0.0))

Creates a FCMEQ instruction.

This macro is used to encode the forms:

*    FCMEQ   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #0.0
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe first source vector register, Z (Scalable)

◆ INSTR_CREATE_fcmeq_vector

#define INSTR_CREATE_fcmeq_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_3src(dc, OP_fcmeq, Rd, Rn, Rm, Rm_elsz)

Creates a FCMEQ instruction.

This macro is used to encode the forms:

*    FCMEQ   <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts>
*    FCMEQ   <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fcmeq_vector_zero

#define INSTR_CREATE_fcmeq_vector_zero (   dc,
  Rd,
  Rn,
  Rn_elsz 
)    instr_create_1dst_3src(dc, OP_fcmeq, Rd, Rn, opnd_create_immed_float(0), Rn_elsz)

Creates a FCMEQ instruction.

This macro is used to encode the forms:

*    FCMEQ   <Hd>.<Ts>, <Hn>.<Ts>, #0
*    FCMEQ   <Dd>.<Ts>, <Dn>.<Ts>, #0
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rn_elszThe element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fcmeq_zero

#define INSTR_CREATE_fcmeq_zero (   dc,
  Rd,
  Rn 
)    instr_create_1dst_2src(dc, OP_fcmeq, Rd, Rn, opnd_create_immed_float(0))

Creates a FCMEQ instruction.

This macro is used to encode the forms:

*    FCMEQ   <Hd>, <Hn>, #0
*    FCMEQ   <V><d>, <V><n>, #0
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)

◆ INSTR_CREATE_fcmge_sve_pred

#define INSTR_CREATE_fcmge_sve_pred (   dc,
  Pd,
  Pg,
  Zn,
  Zm 
)    instr_create_1dst_3src(dc, OP_fcmge, Pd, Pg, Zn, Zm)

Creates a FCMGE instruction.

This macro is used to encode the forms:

*    FCMGE   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe first source vector register, Z (Scalable)
ZmThe second source vector register, Z (Scalable)

◆ INSTR_CREATE_fcmge_sve_zero_pred

#define INSTR_CREATE_fcmge_sve_zero_pred (   dc,
  Pd,
  Pg,
  Zn 
)    instr_create_1dst_3src(dc, OP_fcmge, Pd, Pg, Zn, opnd_create_immed_float(0.0))

Creates a FCMGE instruction.

This macro is used to encode the forms:

*    FCMGE   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #0.0
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe first source vector register, Z (Scalable)

◆ INSTR_CREATE_fcmge_vector

#define INSTR_CREATE_fcmge_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_fcmge, Rd, Rm, Rn, width)

Creates a FCMGE vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fcmgt

#define INSTR_CREATE_fcmgt (   dc,
  Rd,
  Rn,
  Rm 
)    instr_create_1dst_2src(dc, OP_fcmgt, Rd, Rn, Rm)

Creates a FCMGT instruction.

This macro is used to encode the forms:

*    FCMGT   <Hd>, <Hn>, <Hm>
*    FCMGT   <V><d>, <V><n>, <V><m>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RmThe third source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)

◆ INSTR_CREATE_fcmgt_sve_pred

#define INSTR_CREATE_fcmgt_sve_pred (   dc,
  Pd,
  Pg,
  Zn,
  Zm 
)    instr_create_1dst_3src(dc, OP_fcmgt, Pd, Pg, Zn, Zm)

Creates a FCMGT instruction.

This macro is used to encode the forms:

*    FCMGT   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe first source vector register, Z (Scalable)
ZmThe second source vector register, Z (Scalable)

◆ INSTR_CREATE_fcmgt_sve_zero_pred

#define INSTR_CREATE_fcmgt_sve_zero_pred (   dc,
  Pd,
  Pg,
  Zn 
)    instr_create_1dst_3src(dc, OP_fcmgt, Pd, Pg, Zn, opnd_create_immed_float(0.0))

Creates a FCMGT instruction.

This macro is used to encode the forms:

*    FCMGT   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #0.0
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe first source vector register, Z (Scalable)

◆ INSTR_CREATE_fcmgt_vector

#define INSTR_CREATE_fcmgt_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_3src(dc, OP_fcmgt, Rd, Rn, Rm, Rm_elsz)

Creates a FCMGT instruction.

This macro is used to encode the forms:

*    FCMGT   <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts>
*    FCMGT   <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fcmgt_vector_zero

#define INSTR_CREATE_fcmgt_vector_zero (   dc,
  Rd,
  Rn,
  Rn_elsz 
)    instr_create_1dst_3src(dc, OP_fcmgt, Rd, Rn, opnd_create_immed_float(0.0), Rn_elsz)

Creates a FCMGT instruction.

This macro is used to encode the forms:

*    FCMGT   <Hd>.<Ts>, <Hn>.<Ts>, #0
*    FCMGT   <Dd>.<Ts>, <Dn>.<Ts>, #0
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rn_elszThe element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fcmgt_zero

#define INSTR_CREATE_fcmgt_zero (   dc,
  Rd,
  Rn 
)    instr_create_1dst_2src(dc, OP_fcmgt, Rd, Rn, opnd_create_immed_float(0.0))

Creates a FCMGT instruction.

This macro is used to encode the forms:

*    FCMGT   <Hd>, <Hn>, #0
*    FCMGT   <V><d>, <V><n>, #0
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)

◆ INSTR_CREATE_fcmle_sve_pred

#define INSTR_CREATE_fcmle_sve_pred (   dc,
  Pd,
  Pg,
  Zm,
  Zn 
)    instr_create_1dst_3src(dc, OP_fcmle, Pd, Pg, Zm, Zn)

Creates a FCMLE instruction.

This macro is used to encode the forms:

*    FCMLE   <Pd>.<Ts>, <Pg>/Z, <Zm>.<Ts>, <Zn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZmThe first source vector register, Z (Scalable)
ZnThe second source vector register, Z (Scalable)

◆ INSTR_CREATE_fcmle_sve_zero_pred

#define INSTR_CREATE_fcmle_sve_zero_pred (   dc,
  Pd,
  Pg,
  Zn 
)    instr_create_1dst_3src(dc, OP_fcmle, Pd, Pg, Zn, opnd_create_immed_float(0.0))

Creates a FCMLE instruction.

This macro is used to encode the forms:

*    FCMLE   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #0.0
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe first source vector register, Z (Scalable)

◆ INSTR_CREATE_fcmle_vector_zero

#define INSTR_CREATE_fcmle_vector_zero (   dc,
  Rd,
  Rn,
  Rn_elsz 
)    instr_create_1dst_3src(dc, OP_fcmle, Rd, Rn, opnd_create_immed_float(0.0), Rn_elsz)

Creates a FCMLE instruction.

This macro is used to encode the forms:

*    FCMLE   <Hd>.<Ts>, <Hn>.<Ts>, #0
*    FCMLE   <Dd>.<Ts>, <Dn>.<Ts>, #0
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rn_elszThe element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fcmle_zero

#define INSTR_CREATE_fcmle_zero (   dc,
  Rd,
  Rn 
)    instr_create_1dst_2src(dc, OP_fcmle, Rd, Rn, opnd_create_immed_float(0.0))

Creates a FCMLE instruction.

This macro is used to encode the forms:

*    FCMLE   <Hd>, <Hn>, #0
*    FCMLE   <V><d>, <V><n>, #0
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)

◆ INSTR_CREATE_fcmlt_sve_pred

#define INSTR_CREATE_fcmlt_sve_pred (   dc,
  Pd,
  Pg,
  Zm,
  Zn 
)    instr_create_1dst_3src(dc, OP_fcmlt, Pd, Pg, Zm, Zn)

Creates a FCMLT instruction.

This macro is used to encode the forms:

*    FCMLT   <Pd>.<Ts>, <Pg>/Z, <Zm>.<Ts>, <Zn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZmThe first source vector register, Z (Scalable)
ZnThe second source vector register, Z (Scalable)

◆ INSTR_CREATE_fcmlt_sve_zero_pred

#define INSTR_CREATE_fcmlt_sve_zero_pred (   dc,
  Pd,
  Pg,
  Zn 
)    instr_create_1dst_3src(dc, OP_fcmlt, Pd, Pg, Zn, opnd_create_immed_float(0.0))

Creates a FCMLT instruction.

This macro is used to encode the forms:

*    FCMLT   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #0.0
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe first source vector register, Z (Scalable)

◆ INSTR_CREATE_fcmlt_vector_zero

#define INSTR_CREATE_fcmlt_vector_zero (   dc,
  Rd,
  Rn,
  Rn_elsz 
)    instr_create_1dst_3src(dc, OP_fcmlt, Rd, Rn, opnd_create_immed_float(0.0), Rn_elsz)

Creates a FCMLT instruction.

This macro is used to encode the forms:

*    FCMLT   <Hd>.<Ts>, <Hn>.<Ts>, #0
*    FCMLT   <Dd>.<Ts>, <Dn>.<Ts>, #0
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rn_elszThe element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fcmlt_zero

#define INSTR_CREATE_fcmlt_zero (   dc,
  Rd,
  Rn 
)    instr_create_1dst_2src(dc, OP_fcmlt, Rd, Rn, opnd_create_immed_float(0.0))

Creates a FCMLT instruction.

This macro is used to encode the forms:

*    FCMLT   <Hd>, <Hn>, #0
*    FCMLT   <V><d>, <V><n>, #0
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)

◆ INSTR_CREATE_fcmne_sve_pred

#define INSTR_CREATE_fcmne_sve_pred (   dc,
  Pd,
  Pg,
  Zn,
  Zm 
)    instr_create_1dst_3src(dc, OP_fcmne, Pd, Pg, Zn, Zm)

Creates a FCMNE instruction.

This macro is used to encode the forms:

*    FCMNE   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe first source vector register, Z (Scalable)
ZmThe second source vector register, Z (Scalable)

◆ INSTR_CREATE_fcmne_sve_zero_pred

#define INSTR_CREATE_fcmne_sve_zero_pred (   dc,
  Pd,
  Pg,
  Zn 
)    instr_create_1dst_3src(dc, OP_fcmne, Pd, Pg, Zn, opnd_create_immed_float(0.0))

Creates a FCMNE instruction.

This macro is used to encode the forms:

*    FCMNE   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #0.0
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe first source vector register, Z (Scalable)

◆ INSTR_CREATE_fcmp

#define INSTR_CREATE_fcmp (   dc,
  Rn,
  Rm 
)    instr_create_0dst_2src(dc, OP_fcmp, Rn, Rm)

Creates a FCMP instruction.

This macro is used to encode the forms:

*    FCMP    <Dn>, <Dm>
*    FCMP    <Hn>, <Hm>
*    FCMP    <Sn>, <Sm>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RnThe first source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)
RmThe second source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)

◆ INSTR_CREATE_fcmp_zero

#define INSTR_CREATE_fcmp_zero (   dc,
  Rn 
)    instr_create_0dst_2src(dc, OP_fcmp, Rn, opnd_create_immed_float(0.0))

Creates a FCMP instruction.

This macro is used to encode the forms:

*    FCMP    <Dn>, #0.0
*    FCMP    <Hn>, #0.0
*    FCMP    <Sn>, #0.0
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RnThe first source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)

◆ INSTR_CREATE_fcmpe

#define INSTR_CREATE_fcmpe (   dc,
  Rn,
  Rm 
)    instr_create_0dst_2src(dc, OP_fcmpe, Rn, Rm)

Creates a FCMPE instruction.

This macro is used to encode the forms:

*    FCMPE   <Dn>, <Dm>
*    FCMPE   <Hn>, <Hm>
*    FCMPE   <Sn>, <Sm>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RnThe first source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)
RmThe second source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)

◆ INSTR_CREATE_fcmpe_zero

#define INSTR_CREATE_fcmpe_zero (   dc,
  Rn 
)    instr_create_0dst_2src(dc, OP_fcmpe, Rn, opnd_create_immed_float(0.0))

Creates a FCMPE instruction.

This macro is used to encode the forms:

*    FCMPE   <Dn>, #0.0
*    FCMPE   <Hn>, #0.0
*    FCMPE   <Sn>, #0.0
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RnThe first source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)

◆ INSTR_CREATE_fcmuo_sve_pred

#define INSTR_CREATE_fcmuo_sve_pred (   dc,
  Pd,
  Pg,
  Zn,
  Zm 
)    instr_create_1dst_3src(dc, OP_fcmuo, Pd, Pg, Zn, Zm)

Creates a FCMUO instruction.

This macro is used to encode the forms:

*    FCMUO   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
PdThe destination predicate register, P (Predicate)
PgThe governing predicate register, P (Predicate)
ZnThe first source vector register, Z (Scalable)
ZmThe second source vector register, Z (Scalable)

◆ INSTR_CREATE_fcsel

#define INSTR_CREATE_fcsel (   dc,
  Rd,
  Rn,
  Rm,
  condition_code 
)    INSTR_PRED(instr_create_1dst_2src(dc, OP_fcsel, Rd, Rn, Rm), (condition_code))

Creates a FCSEL instruction.

This macro is used to encode the forms:

*    FCSEL   <Dd>, <Dn>, <Dm>, <cond>
*    FCSEL   <Hd>, <Hn>, <Hm>, <cond>
*    FCSEL   <Sd>, <Sn>, <Sm>, <cond>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)
RnThe second source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)
RmThe third source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)
condition_codeThe comparison condition specified by dr_pred_type_t, e.g. DR_PRED_EQ.

◆ INSTR_CREATE_fcvt_scalar

#define INSTR_CREATE_fcvt_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fcvt, Rd, Rm)

Creates an FCVT floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point or integer output register.
RmFloating-point input register.

◆ INSTR_CREATE_fcvt_sve_pred

#define INSTR_CREATE_fcvt_sve_pred (   dc,
  Zd,
  Pg,
  Zn 
)    instr_create_1dst_2src(dc, OP_fcvt, Zd, Pg, Zn)

Creates a FCVT instruction.

This macro is used to encode the forms:

*    FCVT    <Zd>.H, <Pg>/M, <Zn>.D
*    FCVT    <Zd>.S, <Pg>/M, <Zn>.D
*    FCVT    <Zd>.D, <Pg>/M, <Zn>.H
*    FCVT    <Zd>.S, <Pg>/M, <Zn>.H
*    FCVT    <Zd>.D, <Pg>/M, <Zn>.S
*    FCVT    <Zd>.H, <Pg>/M, <Zn>.S
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZnThe source vector register, Z (Scalable).

◆ INSTR_CREATE_fcvtas_scalar

#define INSTR_CREATE_fcvtas_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fcvtas, Rd, Rm)

Creates an FCVTAS floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point or integer output register.
RmFloating-point input register.

◆ INSTR_CREATE_fcvtas_vector

#define INSTR_CREATE_fcvtas_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_fcvtas, Rd, Rm, width)

Creates an FCVTAS vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe input vector register.
widthImmediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fcvtau_scalar

#define INSTR_CREATE_fcvtau_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fcvtau, Rd, Rm)

Creates an FCVTAU floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point or integer output register.
RmFloating-point input register.

◆ INSTR_CREATE_fcvtau_vector

#define INSTR_CREATE_fcvtau_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_fcvtau, Rd, Rm, width)

Creates an FCVTAU vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe input vector register.
widthImmediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fcvtms_scalar

#define INSTR_CREATE_fcvtms_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fcvtms, Rd, Rm)

Creates an FCVTMS floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point or integer output register.
RmFloating-point input register.

◆ INSTR_CREATE_fcvtms_vector

#define INSTR_CREATE_fcvtms_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_fcvtms, Rd, Rm, width)

Creates an FCVTMS vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe input vector register.
widthImmediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fcvtmu_scalar

#define INSTR_CREATE_fcvtmu_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fcvtmu, Rd, Rm)

Creates an FCVTMU floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point or integer output register.
RmFloating-point input register.

◆ INSTR_CREATE_fcvtmu_vector

#define INSTR_CREATE_fcvtmu_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_fcvtmu, Rd, Rm, width)

Creates an FCVTMU vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe input vector register.
widthImmediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fcvtns_scalar

#define INSTR_CREATE_fcvtns_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fcvtns, Rd, Rm)

Creates an FCVTNS floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point or integer output register.
RmFloating-point input register.

◆ INSTR_CREATE_fcvtns_vector

#define INSTR_CREATE_fcvtns_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_fcvtns, Rd, Rm, width)

Creates an FCVTNS vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
widthImmediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fcvtnu_scalar

#define INSTR_CREATE_fcvtnu_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fcvtnu, Rd, Rm)

Creates an FCVTNU floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point or integer output register.
RmFloating-point input register.

◆ INSTR_CREATE_fcvtnu_vector

#define INSTR_CREATE_fcvtnu_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_fcvtnu, Rd, Rm, width)

Creates an FCVTNU vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
widthImmediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fcvtps_scalar

#define INSTR_CREATE_fcvtps_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fcvtps, Rd, Rm)

Creates an FCVTPS floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point or integer output register.
RmFloating-point input register.

◆ INSTR_CREATE_fcvtps_vector

#define INSTR_CREATE_fcvtps_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_fcvtps, Rd, Rm, width)

Creates an FCVTPS vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
widthImmediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fcvtpu_scalar

#define INSTR_CREATE_fcvtpu_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fcvtpu, Rd, Rm)

Creates an FCVTPU floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point or integer output register.
RmFloating-point input register.

◆ INSTR_CREATE_fcvtpu_vector

#define INSTR_CREATE_fcvtpu_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_fcvtpu, Rd, Rm, width)

Creates an FCVTPU vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
widthImmediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fcvtzs_scalar

#define INSTR_CREATE_fcvtzs_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fcvtzs, Rd, Rm)

Creates an FCVTZS floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point or integer output register.
RmFloating-point input register.

◆ INSTR_CREATE_fcvtzs_scalar_fixed

#define INSTR_CREATE_fcvtzs_scalar_fixed (   dc,
  Rd,
  Rm,
  fbits 
)    instr_create_1dst_2src(dc, OP_fcvtzs, Rd, Rm, fbits)

Creates an FCVTZS scalar floating-point to fixed-point convert instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point or integer output register.
RmFloating-point input register.
fbitsThe number of bits after the binary point in the fixed-point destination.

◆ INSTR_CREATE_fcvtzs_sve_pred

#define INSTR_CREATE_fcvtzs_sve_pred (   dc,
  Zd,
  Pg,
  Zn 
)    instr_create_1dst_2src(dc, OP_fcvtzs, Zd, Pg, Zn)

Creates a FCVTZS instruction.

This macro is used to encode the forms:

*    FCVTZS  <Zd>.S, <Pg>/M, <Zn>.D
*    FCVTZS  <Zd>.D, <Pg>/M, <Zn>.D
*    FCVTZS  <Zd>.H, <Pg>/M, <Zn>.H
*    FCVTZS  <Zd>.S, <Pg>/M, <Zn>.H
*    FCVTZS  <Zd>.D, <Pg>/M, <Zn>.H
*    FCVTZS  <Zd>.S, <Pg>/M, <Zn>.S
*    FCVTZS  <Zd>.D, <Pg>/M, <Zn>.S
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZnThe source vector register, Z (Scalable).

◆ INSTR_CREATE_fcvtzs_vector

#define INSTR_CREATE_fcvtzs_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_fcvtzs, Rd, Rm, width)

Creates an FCVTZS vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
widthImmediate int of the vector element width. Must be OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fcvtzu_scalar

#define INSTR_CREATE_fcvtzu_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fcvtzu, Rd, Rm)

Creates an FCVTZU floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point or integer output register.
RmFloating-point input register.

◆ INSTR_CREATE_fcvtzu_scalar_fixed

#define INSTR_CREATE_fcvtzu_scalar_fixed (   dc,
  Rd,
  Rm,
  fbits 
)    instr_create_1dst_2src(dc, OP_fcvtzu, Rd, Rm, fbits)

Creates an FCVTZU scalar floating-point to fixed-point convert instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdFloating-point or integer output register.
RmFloating-point input register.
fbitsThe number of bits after the binary point in the fixed-point destination.

◆ INSTR_CREATE_fcvtzu_sve_pred

#define INSTR_CREATE_fcvtzu_sve_pred (   dc,
  Zd,
  Pg,
  Zn 
)    instr_create_1dst_2src(dc, OP_fcvtzu, Zd, Pg, Zn)

Creates a FCVTZU instruction.

This macro is used to encode the forms:

*    FCVTZU  <Zd>.S, <Pg>/M, <Zn>.D
*    FCVTZU  <Zd>.D, <Pg>/M, <Zn>.D
*    FCVTZU  <Zd>.H, <Pg>/M, <Zn>.H
*    FCVTZU  <Zd>.S, <Pg>/M, <Zn>.H
*    FCVTZU  <Zd>.D, <Pg>/M, <Zn>.H
*    FCVTZU  <Zd>.S, <Pg>/M, <Zn>.S
*    FCVTZU  <Zd>.D, <Pg>/M, <Zn>.S
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZnThe source vector register, Z (Scalable).

◆ INSTR_CREATE_fcvtzu_vector

#define INSTR_CREATE_fcvtzu_vector (   dc,
  Rd,
  Rm,
  width 
)    instr_create_1dst_2src(dc, OP_fcvtzu, Rd, Rm, width)

Creates an FCVTZU vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
widthImmediate int of the vector element width. Must be OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fcvtzu_vector_fixed

#define INSTR_CREATE_fcvtzu_vector_fixed (   dc,
  Rd,
  Rm,
  width,
  fbits 
)    instr_create_1dst_3src(dc, OP_fcvtzu, Rd, Rm, width, fbits)

Creates an FCVTZU vector floating-point to fixed-point convert instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe input register.
widthThe vector element width. Use either OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
fbitsThe number of bits after the binary point in the fixed-point destination element.

◆ INSTR_CREATE_fdiv_scalar

#define INSTR_CREATE_fdiv_scalar (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_fdiv, Rd, Rm, Rn)

Creates a FDIV floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_fdiv_sve

#define INSTR_CREATE_fdiv_sve (   dc,
  Zdn,
  Pg,
  Zm 
)    instr_create_1dst_3src(dc, OP_fdiv, Zdn, Pg, Zdn, Zm)

Creates a FDIV instruction.

This macro is used to encode the forms:

*    FDIV    <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_fdiv_vector

#define INSTR_CREATE_fdiv_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_fdiv, Rd, Rm, Rn, width)

Creates a FDIV vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fdivr_sve

#define INSTR_CREATE_fdivr_sve (   dc,
  Zdn,
  Pg,
  Zm 
)    instr_create_1dst_3src(dc, OP_fdivr, Zdn, Pg, Zdn, Zm)

Creates a FDIVR instruction.

This macro is used to encode the forms:

*    FDIVR   <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_fdup_sve

#define INSTR_CREATE_fdup_sve (   dc,
  Zd,
  imm 
)    instr_create_1dst_1src(dc, OP_fdup, Zd, imm)

Creates a FDUP instruction.

This macro is used to encode the forms:

*    FDUP    <Zd>.<Ts>, #<imm>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe destination vector register, Z (Scalable).
immThe floating-point immediate value to be copied.

◆ INSTR_CREATE_fexpa_sve

#define INSTR_CREATE_fexpa_sve (   dc,
  Zd,
  Zn 
)    instr_create_1dst_1src(dc, OP_fexpa, Zd, Zn)

Creates a FEXPA instruction.

This macro is used to encode the forms:

*    FEXPA   <Zd>.<Ts>, <Zn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe destination vector register, Z (Scalable)
ZnThe source vector register, Z (Scalable)

◆ INSTR_CREATE_fmad_sve

#define INSTR_CREATE_fmad_sve (   dc,
  Zdn,
  Pg,
  Zm,
  Za 
)    instr_create_1dst_4src(dc, OP_fmad, Zdn, Zdn, Pg, Zm, Za)

Creates a FMAD instruction.

This macro is used to encode the forms:

*    FMAD    <Zdn>.<Ts>, <Pg>/M, <Zm>.<Ts>, <Za>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZmThe second source vector register, Z (Scalable).
ZaThe third source vector register, Z (Scalable).

◆ INSTR_CREATE_fmadd_scalar

#define INSTR_CREATE_fmadd_scalar (   dc,
  Rd,
  Rm,
  Rn,
  Ra 
)    instr_create_1dst_3src(dc, OP_fmadd, Rd, Rm, Rn, Ra)

Creates a FMADD floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
RaThe third input register.

◆ INSTR_CREATE_fmax_scalar

#define INSTR_CREATE_fmax_scalar (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_fmax, Rd, Rm, Rn)

Creates a FMAX floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_fmax_sve

#define INSTR_CREATE_fmax_sve (   dc,
  Zdn,
  Pg,
  imm 
)    instr_create_1dst_3src(dc, OP_fmax, Zdn, Pg, Zdn, imm)

Creates a FMAX instruction.

This macro is used to encode the forms:

*    FMAX    <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <const>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
immFloating point constant, either 0.0 or 1.0.

◆ INSTR_CREATE_fmax_sve_vector

#define INSTR_CREATE_fmax_sve_vector (   dc,
  Zdn,
  Pg,
  Zm 
)    instr_create_1dst_3src(dc, OP_fmax, Zdn, Pg, Zdn, Zm)

Creates a FMAX instruction.

This macro is used to encode the forms:

*    FMAX    <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_fmax_vector

#define INSTR_CREATE_fmax_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_fmax, Rd, Rm, Rn, width)

Creates a FMAX vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fmaxnm_scalar

#define INSTR_CREATE_fmaxnm_scalar (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_fmaxnm, Rd, Rm, Rn)

Creates a FMAXNM floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_fmaxnm_sve

#define INSTR_CREATE_fmaxnm_sve (   dc,
  Zdn,
  Pg,
  imm 
)    instr_create_1dst_3src(dc, OP_fmaxnm, Zdn, Pg, Zdn, imm)

Creates a FMAXNM instruction.

This macro is used to encode the forms:

*    FMAXNM  <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <const>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
immFloating point constant, either 0.0 or 1.0.

◆ INSTR_CREATE_fmaxnm_sve_vector

#define INSTR_CREATE_fmaxnm_sve_vector (   dc,
  Zdn,
  Pg,
  Zm 
)    instr_create_1dst_3src(dc, OP_fmaxnm, Zdn, Pg, Zdn, Zm)

Creates a FMAXNM instruction.

This macro is used to encode the forms:

*    FMAXNM  <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_fmaxnm_vector

#define INSTR_CREATE_fmaxnm_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_fmaxnm, Rd, Rm, Rn, width)

Creates a FMAXNM vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fmaxnmp_scalar

#define INSTR_CREATE_fmaxnmp_scalar (   dc,
  Rd,
  Rn,
  Rn_elsz 
)    instr_create_1dst_2src(dc, OP_fmaxnmp, Rd, Rn, Rn_elsz)

Creates a FMAXNMP instruction.

This macro is used to encode the forms:

*    FMAXNMP <Hd>, <Hn>.2H
*    FMAXNMP <V><d>, <Sn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rn_elszThe element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fmaxnmp_vector

#define INSTR_CREATE_fmaxnmp_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_3src(dc, OP_fmaxnmp, Rd, Rn, Rm, Rm_elsz)

Creates a FMAXNMP instruction.

This macro is used to encode the forms:

*    FMAXNMP <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts>
*    FMAXNMP <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fmaxnmv_sve_pred

#define INSTR_CREATE_fmaxnmv_sve_pred (   dc,
  Vd,
  Pg,
  Zn 
)    instr_create_1dst_2src(dc, OP_fmaxnmv, Vd, Pg, Zn)

Creates a FMAXNMV instruction.

This macro is used to encode the forms:

*    FMAXNMV <V><d>, <Pg>, <Zn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination register. Can be S (singleword, 32 bits), H (halfword, 16 bits) or D (doubleword, 64 bits).
PgThe governing predicate register, P (Predicate).
ZnThe source vector register, Z (Scalable).

◆ INSTR_CREATE_fmaxp_scalar

#define INSTR_CREATE_fmaxp_scalar (   dc,
  Rd,
  Rn,
  Rn_elsz 
)    instr_create_1dst_2src(dc, OP_fmaxp, Rd, Rn, Rn_elsz)

Creates a FMAXP instruction.

This macro is used to encode the forms:

*    FMAXP   <Hd>, <Hn>.2H
*    FMAXP   <V><d>, <Sn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rn_elszThe element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fmaxp_vector

#define INSTR_CREATE_fmaxp_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_3src(dc, OP_fmaxp, Rd, Rn, Rm, Rm_elsz)

Creates a FMAXP instruction.

This macro is used to encode the forms:

*    FMAXP   <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts>
*    FMAXP   <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fmaxv_sve_pred

#define INSTR_CREATE_fmaxv_sve_pred (   dc,
  Vd,
  Pg,
  Zn 
)    instr_create_1dst_2src(dc, OP_fmaxv, Vd, Pg, Zn)

Creates a FMAXV instruction.

This macro is used to encode the forms:

*    FMAXV   <V><d>, <Pg>, <Zn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination register. Can be S (singleword, 32 bits), H (halfword, 16 bits) or D (doubleword, 64 bits).
PgThe governing predicate register, P (Predicate).
ZnThe source vector register, Z (Scalable).

◆ INSTR_CREATE_fmin_scalar

#define INSTR_CREATE_fmin_scalar (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_fmin, Rd, Rm, Rn)

Creates a FMIN floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_fmin_sve

#define INSTR_CREATE_fmin_sve (   dc,
  Zdn,
  Pg,
  imm 
)    instr_create_1dst_3src(dc, OP_fmin, Zdn, Pg, Zdn, imm)

Creates a FMIN instruction.

This macro is used to encode the forms:

*    FMIN    <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <const>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
immFloating point constant, either 0.0 or 1.0.

◆ INSTR_CREATE_fmin_sve_vector

#define INSTR_CREATE_fmin_sve_vector (   dc,
  Zdn,
  Pg,
  Zm 
)    instr_create_1dst_3src(dc, OP_fmin, Zdn, Pg, Zdn, Zm)

Creates a FMIN instruction.

This macro is used to encode the forms:

*    FMIN    <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_fmin_vector

#define INSTR_CREATE_fmin_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_fmin, Rd, Rm, Rn, width)

Creates a FMIN vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fminnm_scalar

#define INSTR_CREATE_fminnm_scalar (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_fminnm, Rd, Rm, Rn)

Creates a FMINNM floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_fminnm_sve

#define INSTR_CREATE_fminnm_sve (   dc,
  Zdn,
  Pg,
  imm 
)    instr_create_1dst_3src(dc, OP_fminnm, Zdn, Pg, Zdn, imm)

Creates a FMINNM instruction.

This macro is used to encode the forms:

*    FMINNM  <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <const>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
immFloating point constant, either 0.0 or 1.0.

◆ INSTR_CREATE_fminnm_sve_vector

#define INSTR_CREATE_fminnm_sve_vector (   dc,
  Zdn,
  Pg,
  Zm 
)    instr_create_1dst_3src(dc, OP_fminnm, Zdn, Pg, Zdn, Zm)

Creates a FMINNM instruction.

This macro is used to encode the forms:

*    FMINNM  <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_fminnm_vector

#define INSTR_CREATE_fminnm_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_fminnm, Rd, Rm, Rn, width)

Creates a FMINNM vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fminnmp_scalar

#define INSTR_CREATE_fminnmp_scalar (   dc,
  Rd,
  Rn,
  Rn_elsz 
)    instr_create_1dst_2src(dc, OP_fminnmp, Rd, Rn, Rn_elsz)

Creates a FMINNMP instruction.

This macro is used to encode the forms:

*    FMINNMP <Hd>, <Hn>.2H
*    FMINNMP <V><d>, <Sn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rn_elszThe element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fminnmp_vector

#define INSTR_CREATE_fminnmp_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_3src(dc, OP_fminnmp, Rd, Rn, Rm, Rm_elsz)

Creates a FMINNMP instruction.

This macro is used to encode the forms:

*    FMINNMP <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts>
*    FMINNMP <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fminnmv_sve_pred

#define INSTR_CREATE_fminnmv_sve_pred (   dc,
  Vd,
  Pg,
  Zn 
)    instr_create_1dst_2src(dc, OP_fminnmv, Vd, Pg, Zn)

Creates a FMINNMV instruction.

This macro is used to encode the forms:

*    FMINNMV <V><d>, <Pg>, <Zn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination register. Can be S (singleword, 32 bits), H (halfword, 16 bits) or D (doubleword, 64 bits).
PgThe governing predicate register, P (Predicate).
ZnThe source vector register, Z (Scalable).

◆ INSTR_CREATE_fminnmv_vector

#define INSTR_CREATE_fminnmv_vector (   dc,
  Rd,
  Rn,
  Rn_elsz 
)    instr_create_1dst_2src(dc, OP_fminnmv, Rd, Rn, Rn_elsz)

Creates a FMINNMV instruction.

This macro is used to encode the forms:

*    FMINNMV <Hd>, <Hn>.<Ts>
*    FMINNMV <Sd>, <Sn>.4S
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits) or S (singleword, 32 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rn_elszThe element size for Rn. Can be OPND_CREATE_HALF() or OPND_CREATE_SINGLE()

◆ INSTR_CREATE_fminp_scalar

#define INSTR_CREATE_fminp_scalar (   dc,
  Rd,
  Rn,
  Rn_elsz 
)    instr_create_1dst_2src(dc, OP_fminp, Rd, Rn, Rn_elsz)

Creates a FMINP instruction.

This macro is used to encode the forms:

*    FMINP   <Hd>, <Hn>.2H
*    FMINP   <V><d>, <Sn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rn_elszThe element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fminp_vector

#define INSTR_CREATE_fminp_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_3src(dc, OP_fminp, Rd, Rn, Rm, Rm_elsz)

Creates a FMINP instruction.

This macro is used to encode the forms:

*    FMINP   <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts>
*    FMINP   <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fminv_sve_pred

#define INSTR_CREATE_fminv_sve_pred (   dc,
  Vd,
  Pg,
  Zn 
)    instr_create_1dst_2src(dc, OP_fminv, Vd, Pg, Zn)

Creates a FMINV instruction.

This macro is used to encode the forms:

*    FMINV   <V><d>, <Pg>, <Zn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
VdThe destination register. Can be S (singleword, 32 bits), H (halfword, 16 bits) or D (doubleword, 64 bits).
PgThe governing predicate register, P (Predicate).
ZnThe source vector register, Z (Scalable).

◆ INSTR_CREATE_fmla_sve_idx

#define INSTR_CREATE_fmla_sve_idx (   dc,
  Zda,
  Zn,
  Zm,
  index 
)    instr_create_1dst_4src(dc, OP_fmla, Zda, Zda, Zn, Zm, index)

Creates a FMLA instruction.

This macro is used to encode the forms:

*    FMLA    <Zda>.H, <Zn>.H, <Zm>.H[<index>]
*    FMLA    <Zda>.S, <Zn>.S, <Zm>.S[<index>]
*    FMLA    <Zda>.D, <Zn>.D, <Zm>.D[<index>]
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdaThe third source and destination vector register, Z (Scalable).
ZnThe first source vector register, Z (Scalable).
ZmThe second source vector register, Z (Scalable).
indexSecond source index constant.

◆ INSTR_CREATE_fmla_sve_vector

#define INSTR_CREATE_fmla_sve_vector (   dc,
  Zda,
  Pg,
  Zn,
  Zm 
)    instr_create_1dst_4src(dc, OP_fmla, Zda, Zda, Pg, Zn, Zm)

Creates a FMLA instruction.

This macro is used to encode the forms:

*    FMLA    <Zda>.<Ts>, <Pg>/M, <Zn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdaThe third source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZnThe first source vector register, Z (Scalable).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_fmla_vector

#define INSTR_CREATE_fmla_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_4src(dc, OP_fmla, Rd, Rd, Rn, Rm, Rm_elsz)

Creates a FMLA instruction.

This macro is used to encode the forms:

*    FMLA    <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts>
*    FMLA    <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first source and destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fmla_vector_idx

#define INSTR_CREATE_fmla_vector_idx (   dc,
  Rd,
  Rn,
  Rm,
  index,
  Rm_elsz 
)    instr_create_1dst_5src(dc, OP_fmla, Rd, Rd, Rn, Rm, index, Rm_elsz)

Creates a FMLA instruction.

This macro is used to encode the forms:

*    FMLA    <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.H[<index>]
*    FMLA    <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Tb>[<index>]
*    FMLA    <Hd>, <Hn>, <Hm>.H[<index>]
*    FMLA    <V><d>, <V><n>, <Sm>.<Ts>[<index>]
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first source and destination vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be Q (quadword, 128 bits)
indexThe immediate index for Rm
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fmlal2_vector

#define INSTR_CREATE_fmlal2_vector (   dc,
  Rd,
  Rn,
  Rm 
)    instr_create_1dst_4src(dc, OP_fmlal2, Rd, Rd, Rn, Rm, OPND_CREATE_HALF())

Creates a FMLAL2 instruction.

This macro is used to encode the forms:

*    FMLAL2  <Sd>.<Ts>, <Hn>.<Tb>, <Hm>.<Tb>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first source and destination vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register, S (singleword, 32 bits) or D (doubleword, 64 bits)
RmThe third source vector register, S (singleword, 32 bits) or D (doubleword, 64 bits)

◆ INSTR_CREATE_fmlal2_vector_idx

#define INSTR_CREATE_fmlal2_vector_idx (   dc,
  Rd,
  Rn,
  Rm,
  index 
)    instr_create_1dst_5src(dc, OP_fmlal2, Rd, Rd, Rn, Rm, index, OPND_CREATE_HALF())

Creates a FMLAL2 instruction.

This macro is used to encode the forms:

*    FMLAL2  <Sd>.<Ts>, <Hn>.<Tb>, <Hm>.H[<index>]
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first source and destination vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register, S (singleword, 32 bits) or D (doubleword, 64 bits)
RmThe third source vector register, Q (quadword, 128 bits)
indexThe immediate index for Rm

◆ INSTR_CREATE_fmlal_vector

#define INSTR_CREATE_fmlal_vector (   dc,
  Rd,
  Rn,
  Rm 
)    instr_create_1dst_4src(dc, OP_fmlal, Rd, Rd, Rn, Rm, OPND_CREATE_HALF())

Creates a FMLAL instruction.

This macro is used to encode the forms:

*    FMLAL   <Sd>.<Ts>, <Hn>.<Tb>, <Hm>.<Tb>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first source and destination vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register, S (singleword, 32 bits) or D (doubleword, 64 bits)
RmThe third source vector register, S (singleword, 32 bits) or D (doubleword, 64 bits)

◆ INSTR_CREATE_fmlal_vector_idx

#define INSTR_CREATE_fmlal_vector_idx (   dc,
  Rd,
  Rn,
  Rm,
  index 
)    instr_create_1dst_5src(dc, OP_fmlal, Rd, Rd, Rn, Rm, index, OPND_CREATE_HALF())

Creates a FMLAL instruction.

This macro is used to encode the forms:

*    FMLAL   <Sd>.<Ts>, <Hn>.<Tb>, <Hm>.H[<index>]
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first source and destination vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register, S (singleword, 32 bits) or D (doubleword, 64 bits)
RmThe third source vector register, Q (quadword, 128 bits)
indexThe immediate index for Rm

◆ INSTR_CREATE_fmls_sve_idx

#define INSTR_CREATE_fmls_sve_idx (   dc,
  Zda,
  Zn,
  Zm,
  index 
)    instr_create_1dst_4src(dc, OP_fmls, Zda, Zda, Zn, Zm, index)

Creates a FMLS instruction.

This macro is used to encode the forms:

*    FMLS    <Zda>.H, <Zn>.H, <Zm>.H[<index>]
*    FMLS    <Zda>.S, <Zn>.S, <Zm>.S[<index>]
*    FMLS    <Zda>.D, <Zn>.D, <Zm>.D[<index>]
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdaThe third source and destination vector register, Z (Scalable).
ZnThe first source vector register, Z (Scalable).
ZmThe second source vector register, Z (Scalable).
indexSecond source index constant.

◆ INSTR_CREATE_fmls_sve_vector

#define INSTR_CREATE_fmls_sve_vector (   dc,
  Zda,
  Pg,
  Zn,
  Zm 
)    instr_create_1dst_4src(dc, OP_fmls, Zda, Zda, Pg, Zn, Zm)

Creates a FMLS instruction.

This macro is used to encode the forms:

*    FMLS    <Zda>.<Ts>, <Pg>/M, <Zn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdaThe third source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZnThe first source vector register, Z (Scalable).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_fmls_vector

#define INSTR_CREATE_fmls_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_4src(dc, OP_fmls, Rd, Rd, Rn, Rm, Rm_elsz)

Creates a FMLS instruction.

This macro is used to encode the forms:

*    FMLS    <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts>
*    FMLS    <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first source and destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fmls_vector_idx

#define INSTR_CREATE_fmls_vector_idx (   dc,
  Rd,
  Rn,
  Rm,
  index,
  Rm_elsz 
)    instr_create_1dst_5src(dc, OP_fmls, Rd, Rd, Rn, Rm, index, Rm_elsz)

Creates a FMLS instruction.

This macro is used to encode the forms:

*    FMLS    <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.H[<index>]
*    FMLS    <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Tb>[<index>]
*    FMLS    <Hd>, <Hn>, <Hm>.H[<index>]
*    FMLS    <V><d>, <V><n>, <Sm>.<Ts>[<index>]
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first source and destination vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be Q (quadword, 128 bits)
indexThe immediate index for Rm
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fmlsl2_vector

#define INSTR_CREATE_fmlsl2_vector (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_4src(dc, OP_fmlsl2, Rd, Rd, Rm, Rn, OPND_CREATE_HALF())

Creates a FMLSL2 vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register. The instruction also reads this register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_fmlsl2_vector_idx

#define INSTR_CREATE_fmlsl2_vector_idx (   dc,
  Rd,
  Rm,
  Rn,
  index 
)    instr_create_1dst_5src(dc, OP_fmlsl2, Rd, Rd, Rm, Rn, index, OPND_CREATE_HALF())

Creates a FMLSL2 indexed vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register. The instruction also reads this register.
RmThe first input register.
RnThe second input register.
indexThe first input register's vector element index.

◆ INSTR_CREATE_fmlsl_vector

#define INSTR_CREATE_fmlsl_vector (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_4src(dc, OP_fmlsl, Rd, Rd, Rm, Rn, OPND_CREATE_HALF())

Creates a FMLSL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register. The instruction also reads this register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_fmlsl_vector_idx

#define INSTR_CREATE_fmlsl_vector_idx (   dc,
  Rd,
  Rm,
  Rn,
  index 
)    instr_create_1dst_5src(dc, OP_fmlsl, Rd, Rd, Rm, Rn, index, OPND_CREATE_HALF())

Creates a FMLSL indexed vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register. The instruction also reads this register.
RmThe first input register.
RnThe second input register.
indexThe first input register's vector element index.

◆ INSTR_CREATE_fmov_general

#define INSTR_CREATE_fmov_general (   dc,
  Rd,
  Rn 
)    instr_create_1dst_1src(dc, OP_fmov, Rd, Rn)

disabled_until_i4106_is_fixed Creates an FMOV instruction to move between GPRs and floating point registers. This macro is used to encode the forms:

*    FMOV    <Wd>, <Hn>
*    FMOV    <Wd>, <Sn>
*    FMOV    <Xd>, <Dn>
*    FMOV    <Xd>, <Hn>
*    FMOV    <Dd>, <Xn>
*    FMOV    <Hd>, <Wn>
*    FMOV    <Hd>, <Xn>
*    FMOV    <Sd>, <Wn>
*    FMOV    <Dd>, <Dn>
*    FMOV    <Hd>, <Hn>
*    FMOV    <Sd>, <Sn>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RnThe first input register.

◆ INSTR_CREATE_fmov_scalar

#define INSTR_CREATE_fmov_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fmov, Rd, Rm)

Creates an FMOV floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.

◆ INSTR_CREATE_fmov_scalar_imm

#define INSTR_CREATE_fmov_scalar_imm (   dc,
  Rd,
 
)    instr_create_1dst_1src(dc, OP_fmov, Rd, f)

Creates an FMOV immediate to scalar floating point move instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output scalar register.
fThe source immediate floating point opnd.

◆ INSTR_CREATE_fmov_upper_vec

#define INSTR_CREATE_fmov_upper_vec (   dc,
  Rd,
  Rn 
)
Value:

Creates an FMOV instruction to move between GPRs and floating point registers.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RnThe first input vector register.

◆ INSTR_CREATE_fmov_vector_imm

#define INSTR_CREATE_fmov_vector_imm (   dc,
  Rd,
  f,
  width 
)    instr_create_1dst_2src(dc, OP_fmov, Rd, f, width)

Creates an FMOV immediate to vector floating point move instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output vector register.
fThe source immediate floating point opnd.
widthThe output vector element width. Use either OPND_CREATE_HALF() or OPND_CREATE_SINGLE().

◆ INSTR_CREATE_fmsb_sve

#define INSTR_CREATE_fmsb_sve (   dc,
  Zdn,
  Pg,
  Zm,
  Za 
)    instr_create_1dst_4src(dc, OP_fmsb, Zdn, Zdn, Pg, Zm, Za)

Creates a FMSB instruction.

This macro is used to encode the forms:

*    FMSB    <Zdn>.<Ts>, <Pg>/M, <Zm>.<Ts>, <Za>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZmThe second source vector register, Z (Scalable).
ZaThe third source vector register, Z (Scalable).

◆ INSTR_CREATE_fmsub_scalar

#define INSTR_CREATE_fmsub_scalar (   dc,
  Rd,
  Rm,
  Rn,
  Ra 
)    instr_create_1dst_3src(dc, OP_fmsub, Rd, Rm, Rn, Ra)

Creates a FMSUB floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
RaThe third input register.

◆ INSTR_CREATE_fmul_scalar

#define INSTR_CREATE_fmul_scalar (   dc,
  Rd,
  Rm,
  Rn 
)    instr_create_1dst_2src(dc, OP_fmul, Rd, Rm, Rn)

Creates a FMUL floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.

◆ INSTR_CREATE_fmul_sve

#define INSTR_CREATE_fmul_sve (   dc,
  Zdn,
  Pg,
  imm 
)    instr_create_1dst_3src(dc, OP_fmul, Zdn, Pg, Zdn, imm)

Creates a FMUL instruction.

This macro is used to encode the forms:

*    FMUL    <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <imm>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
immFloating point constant, either 0.5 or 2.0.

◆ INSTR_CREATE_fmul_sve_idx

#define INSTR_CREATE_fmul_sve_idx (   dc,
  Zd,
  Zn,
  Zm,
  index 
)    instr_create_1dst_3src(dc, OP_fmul, Zd, Zn, Zm, index)

Creates a FMUL instruction.

This macro is used to encode the forms:

*    FMUL    <Zd>.H, <Zn>.H, <Zm>.H[<index>]
*    FMUL    <Zd>.S, <Zn>.S, <Zm>.S[<index>]
*    FMUL    <Zd>.D, <Zn>.D, <Zm>.D[<index>]
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe destination vector register, Z (Scalable).
ZnThe first source vector register, Z (Scalable).
ZmThe second source vector register, Z (Scalable).
indexSecond source index constant.

◆ INSTR_CREATE_fmul_sve_pred_vector

#define INSTR_CREATE_fmul_sve_pred_vector (   dc,
  Zdn,
  Pg,
  Zm 
)    instr_create_1dst_3src(dc, OP_fmul, Zdn, Pg, Zdn, Zm)

Creates a FMUL instruction.

This macro is used to encode the forms:

*    FMUL    <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_fmul_sve_vector

#define INSTR_CREATE_fmul_sve_vector (   dc,
  Zd,
  Zn,
  Zm 
)    instr_create_1dst_2src(dc, OP_fmul, Zd, Zn, Zm)

Creates a FMUL instruction.

This macro is used to encode the forms:

*    FMUL    <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe destination vector register, Z (Scalable).
ZnThe first source vector register, Z (Scalable).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_fmul_vector

#define INSTR_CREATE_fmul_vector (   dc,
  Rd,
  Rm,
  Rn,
  width 
)    instr_create_1dst_3src(dc, OP_fmul, Rd, Rm, Rn, width)

Creates a FMUL vector instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
widthThe vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().

◆ INSTR_CREATE_fmulx

#define INSTR_CREATE_fmulx (   dc,
  Rd,
  Rn,
  Rm 
)    instr_create_1dst_2src(dc, OP_fmulx, Rd, Rn, Rm)

Creates a FMULX instruction.

This macro is used to encode the forms:

*    FMULX   <Hd>, <Hn>, <Hm>
*    FMULX   <V><d>, <V><n>, <V><m>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RnThe second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
RmThe third source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)

◆ INSTR_CREATE_fmulx_sve

#define INSTR_CREATE_fmulx_sve (   dc,
  Zdn,
  Pg,
  Zm 
)    instr_create_1dst_3src(dc, OP_fmulx, Zdn, Pg, Zdn, Zm)

Creates a FMULX instruction.

This macro is used to encode the forms:

*    FMULX   <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe first source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZmThe second source vector register, Z (Scalable).

◆ INSTR_CREATE_fmulx_vector

#define INSTR_CREATE_fmulx_vector (   dc,
  Rd,
  Rn,
  Rm,
  Rm_elsz 
)    instr_create_1dst_3src(dc, OP_fmulx, Rd, Rn, Rm, Rm_elsz)

Creates a FMULX instruction.

This macro is used to encode the forms:

*    FMULX   <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts>
*    FMULX   <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits)
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fmulx_vector_idx

#define INSTR_CREATE_fmulx_vector_idx (   dc,
  Rd,
  Rn,
  Rm,
  index,
  Rm_elsz 
)    instr_create_1dst_4src(dc, OP_fmulx, Rd, Rn, Rm, index, Rm_elsz)

Creates a FMULX instruction.

This macro is used to encode the forms:

*    FMULX   <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.H[<index>]
*    FMULX   <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Tb>[<index>]
*    FMULX   <Hd>, <Hn>, <Hm>.H[<index>]
*    FMULX   <V><d>, <V><n>, <Sm>.<Ts>[<index>]
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe first destination vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits)
RnThe second source vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits)
RmThe third source vector register, Q (quadword, 128 bits)
indexThe immediate index for Rm
Rm_elszThe element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()

◆ INSTR_CREATE_fneg_scalar

#define INSTR_CREATE_fneg_scalar (   dc,
  Rd,
  Rm 
)    instr_create_1dst_1src(dc, OP_fneg, Rd, Rm)

Creates a FNEG floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.

◆ INSTR_CREATE_fneg_sve

#define INSTR_CREATE_fneg_sve (   dc,
  Zd,
  Pg,
  Zn 
)    instr_create_1dst_2src(dc, OP_fneg, Zd, Pg, Zn)

Creates a FNEG instruction.

This macro is used to encode the forms:

*    FNEG    <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdThe destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZnThe source vector register, Z (Scalable).

◆ INSTR_CREATE_fnmad_sve

#define INSTR_CREATE_fnmad_sve (   dc,
  Zdn,
  Pg,
  Zm,
  Za 
)    instr_create_1dst_4src(dc, OP_fnmad, Zdn, Zdn, Pg, Zm, Za)

Creates a FNMAD instruction.

This macro is used to encode the forms:

*    FNMAD   <Zdn>.<Ts>, <Pg>/M, <Zm>.<Ts>, <Za>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdnThe source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZmThe second source vector register, Z (Scalable).
ZaThe third source vector register, Z (Scalable).

◆ INSTR_CREATE_fnmadd_scalar

#define INSTR_CREATE_fnmadd_scalar (   dc,
  Rd,
  Rm,
  Rn,
  Ra 
)    instr_create_1dst_3src(dc, OP_fnmadd, Rd, Rm, Rn, Ra)

Creates a FNMADD floating point instruction.

Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
RdThe output register.
RmThe first input register.
RnThe second input register.
RaThe third input register.

◆ INSTR_CREATE_fnmla_sve

#define INSTR_CREATE_fnmla_sve (   dc,
  Zda,
  Pg,
  Zn,
  Zm 
)    instr_create_1dst_4src(dc, OP_fnmla, Zda, Zda, Pg, Zn, Zm)

Creates a FNMLA instruction.

This macro is used to encode the forms:

*    FNMLA   <Zda>.<Ts>, <Pg>/M, <Zn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdaThe source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZnThe second source vector register, Z (Scalable).
ZmThe third source vector register, Z (Scalable).

◆ INSTR_CREATE_fnmls_sve

#define INSTR_CREATE_fnmls_sve (   dc,
  Zda,
  Pg,
  Zn,
  Zm 
)    instr_create_1dst_4src(dc, OP_fnmls, Zda, Zda, Pg, Zn, Zm)

Creates a FNMLS instruction.

This macro is used to encode the forms:

*    FNMLS   <Zda>.<Ts>, <Pg>/M, <Zn>.<Ts>, <Zm>.<Ts>
* 
Parameters
dcThe void * dcontext used to allocate memory for the instr_t.
ZdaThe source and destination vector register, Z (Scalable).
PgThe governing predicate register, P (Predicate).
ZnThe second source vector register, Z (Scalable).
ZmThe third source vector register, Z (Scalable).

◆ INSTR_CREATE_fnmsub_scalar

#define INSTR_CREATE_fnmsub_scalar (   dc,
  Rd,
  Rm,
  Rn,
  Ra 
)    instr_create_1dst_3src(dc, OP_fnmsub, Rd, Rm, Rn, Ra)

Creates a FNMSUB floating point instruction.

Parameters
dc</