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DynamoRIO
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dr_ir_macros_aarch64.h File Reference
AArch64-specific instruction creation convenience macros. More...
Macros | |
| #define | VECTOR_ELEM_WIDTH_BYTE 0 |
| #define | VECTOR_ELEM_WIDTH_HALF 1 |
| #define | VECTOR_ELEM_WIDTH_SINGLE 2 |
| #define | VECTOR_ELEM_WIDTH_DOUBLE 3 |
| #define | VECTOR_ELEM_WIDTH_QUAD 4 |
| #define | OPND_CREATE_BYTE() OPND_CREATE_INT8(VECTOR_ELEM_WIDTH_BYTE) |
| #define | OPND_CREATE_HALF() OPND_CREATE_INT8(VECTOR_ELEM_WIDTH_HALF) |
| #define | OPND_CREATE_SINGLE() OPND_CREATE_INT8(VECTOR_ELEM_WIDTH_SINGLE) |
| #define | OPND_CREATE_DOUBLE() OPND_CREATE_INT8(VECTOR_ELEM_WIDTH_DOUBLE) |
| #define | OPND_CREATE_ABSMEM(addr, size) opnd_create_rel_addr(addr, size) |
| #define | OPND_CREATE_INT(val) OPND_CREATE_INTPTR(val) |
| #define | OPND_CREATE_ZR(reg) opnd_create_reg(opnd_get_size(reg) == OPSZ_4 ? DR_REG_WZR : DR_REG_XZR) |
| #define | OPND_CREATE_LSL() opnd_add_flags(OPND_CREATE_INT(DR_SHIFT_LSL), DR_OPND_IS_SHIFT) |
| #define | OPND_CREATE_LSR() opnd_add_flags(OPND_CREATE_INT(DR_SHIFT_LSR), DR_OPND_IS_SHIFT) |
| #define | OPND_CREATE_ASR() opnd_add_flags(OPND_CREATE_INT(DR_SHIFT_ASR), DR_OPND_IS_SHIFT) |
| #define | OPND_CREATE_ROR() opnd_add_flags(OPND_CREATE_INT(DR_SHIFT_ROR), DR_OPND_IS_SHIFT) |
| #define | OPND_CREATE_MUL() opnd_add_flags(OPND_CREATE_INT(DR_SHIFT_MUL), DR_OPND_IS_SHIFT) |
| #define | INSTR_CREATE_and(dc, rd, rn, rm_or_imm) |
| #define | INSTR_CREATE_orr(dc, rd, rn, rm_or_imm) |
| #define | INSTR_CREATE_ands(dc, rd, rn, rm_or_imm) |
| #define | INSTR_CREATE_bcond(dc, pc) instr_create_0dst_1src((dc), OP_bcond, (pc)) |
| #define | INSTR_CREATE_bl(dc, pc) instr_create_1dst_1src((dc), OP_bl, opnd_create_reg(DR_REG_X30), (pc)) |
| #define | INSTR_CREATE_ccmp(dc, Rn, Op, nzcv, cond) instr_create_0dst_4src(dc, OP_ccmp, Rn, Op, nzcv, cond) |
| #define | INSTR_CREATE_ccmn(dc, Rn, Op, nzcv, cond) instr_create_0dst_4src(dc, OP_ccmn, Rn, Op, nzcv, cond) |
| #define | INSTR_CREATE_fmov_general(dc, Rd, Rn) instr_create_1dst_1src(dc, OP_fmov, Rd, Rn) |
| #define | INSTR_CREATE_fmov_upper_vec(dc, Rd, Rn) |
| #define | INSTR_CREATE_shadd_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_shadd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sqadd_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sqadd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_srhadd_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_srhadd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_shsub_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_shsub, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sqsub_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sqsub, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_cmgt_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_cmgt, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_cmge_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_cmge, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sshl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sshl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sqshl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sqshl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_srshl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_srshl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sqrshl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sqrshl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_smax_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_smax, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_smin_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_smin, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sabd_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sabd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_saba_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_saba, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_add_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_add, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sve_add_vector(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_add, Rd, Rm, Rn) |
| #define | INSTR_CREATE_cmtst_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_cmtst, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_mla_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_4src(dc, OP_mla, Rd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_mul_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_mul, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_smaxp_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_smaxp, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sminp_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sminp, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sqdmulh_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sqdmulh, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_addp_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_addp, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_fmaxnm_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_fmaxnm, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_fmla_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_4src(dc, OP_fmla, Rd, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_fmla_vector_idx(dc, Rd, Rn, Rm, index, Rm_elsz) instr_create_1dst_5src(dc, OP_fmla, Rd, Rd, Rn, Rm, index, Rm_elsz) |
| #define | INSTR_CREATE_fadd_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_fadd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_fmulx_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_fmulx, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_fmulx_vector_idx(dc, Rd, Rn, Rm, index, Rm_elsz) instr_create_1dst_4src(dc, OP_fmulx, Rd, Rn, Rm, index, Rm_elsz) |
| #define | INSTR_CREATE_fmulx(dc, Rd, Rn, Rm) instr_create_1dst_2src(dc, OP_fmulx, Rd, Rn, Rm) |
| #define | INSTR_CREATE_fcmeq_vector_zero(dc, Rd, Rn, Rn_elsz) instr_create_1dst_3src(dc, OP_fcmeq, Rd, Rn, opnd_create_immed_float(0), Rn_elsz) |
| #define | INSTR_CREATE_fcmeq_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_fcmeq, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_fcmeq_zero(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_fcmeq, Rd, Rn, opnd_create_immed_float(0)) |
| #define | INSTR_CREATE_fcmeq(dc, Rd, Rn, Rm) instr_create_1dst_2src(dc, OP_fcmeq, Rd, Rn, Rm) |
| #define | INSTR_CREATE_fmlal_vector(dc, Rd, Rn, Rm) instr_create_1dst_4src(dc, OP_fmlal, Rd, Rd, Rn, Rm, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_fmlal_vector_idx(dc, Rd, Rn, Rm, index) instr_create_1dst_5src(dc, OP_fmlal, Rd, Rd, Rn, Rm, index, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_fmax_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_fmax, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_frecpe_vector(dc, Rd, Rn, Rn_elsz) instr_create_1dst_2src(dc, OP_frecpe, Rd, Rn, Rn_elsz) |
| #define | INSTR_CREATE_frecpe(dc, Rd, Rn) instr_create_1dst_1src(dc, OP_frecpe, Rd, Rn) |
| #define | INSTR_CREATE_frecps_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_frecps, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_frecps(dc, Rd, Rn, Rm) instr_create_1dst_2src(dc, OP_frecps, Rd, Rn, Rm) |
| #define | INSTR_CREATE_frsqrte_vector(dc, Rd, Rn, Rn_elsz) instr_create_1dst_2src(dc, OP_frsqrte, Rd, Rn, Rn_elsz) |
| #define | INSTR_CREATE_frsqrte(dc, Rd, Rn) instr_create_1dst_1src(dc, OP_frsqrte, Rd, Rn) |
| #define | INSTR_CREATE_and_vector(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_and, Rd, Rm, Rn) |
| #define | INSTR_CREATE_bic_vector(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_bic, Rd, Rm, Rn) |
| #define | INSTR_CREATE_fminnm_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_fminnm, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_fmls_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_4src(dc, OP_fmls, Rd, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_fmls_vector_idx(dc, Rd, Rn, Rm, index, Rm_elsz) instr_create_1dst_5src(dc, OP_fmls, Rd, Rd, Rn, Rm, index, Rm_elsz) |
| #define | INSTR_CREATE_fsub_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_fsub, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_fmlsl_vector(dc, Rd, Rm, Rn) instr_create_1dst_4src(dc, OP_fmlsl, Rd, Rd, Rm, Rn, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_fmlsl_vector_idx(dc, Rd, Rm, Rn, index) instr_create_1dst_5src(dc, OP_fmlsl, Rd, Rd, Rm, Rn, index, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_fmin_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_fmin, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_frsqrts_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_frsqrts, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_frsqrts(dc, Rd, Rn, Rm) instr_create_1dst_2src(dc, OP_frsqrts, Rd, Rn, Rm) |
| #define | INSTR_CREATE_orr_vector(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_orr, Rd, Rm, Rn) |
| #define | INSTR_CREATE_orn_vector(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_orn, Rd, Rm, Rn) |
| #define | INSTR_CREATE_uhadd_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uhadd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uqadd_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uqadd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_urhadd_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_urhadd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uhsub_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uhsub, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uqsub_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uqsub, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_cmhi_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_cmhi, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_cmhs_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_cmhs, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_ushl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_ushl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uqshl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uqshl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_urshl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_urshl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uqrshl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uqrshl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_umax_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_umax, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_umin_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_umin, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uabd_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uabd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uaba_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uaba, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sub_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sub, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_cmeq_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_cmeq, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_mls_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_4src(dc, OP_mls, Rd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_pmul_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_pmul, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_umaxp_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_umaxp, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uminp_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uminp, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sqrdmulh_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sqrdmulh, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sqrdmlsh_scalar(dc, Rd, Rm, Rn) instr_create_1dst_3src(dc, OP_sqrdmlsh, Rd, Rd, Rm, Rn) |
| #define | INSTR_CREATE_sqrdmlsh_scalar_idx(dc, Rd, Rm, Rn, index, elsz) instr_create_1dst_5src(dc, OP_sqrdmlsh, Rd, Rd, Rm, Rn, index, elsz) |
| #define | INSTR_CREATE_sqrdmlsh_vector(dc, Rd, Rm, Rn, elsz) instr_create_1dst_4src(dc, OP_sqrdmlsh, Rd, Rd, Rm, Rn, elsz) |
| #define | INSTR_CREATE_sqrdmlsh_vector_idx(dc, Rd, Rm, Rn, index, elsz) instr_create_1dst_5src(dc, OP_sqrdmlsh, Rd, Rd, Rm, Rn, index, elsz) |
| #define | INSTR_CREATE_fmlal2_vector(dc, Rd, Rn, Rm) instr_create_1dst_4src(dc, OP_fmlal2, Rd, Rd, Rn, Rm, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_fmlal2_vector_idx(dc, Rd, Rn, Rm, index) instr_create_1dst_5src(dc, OP_fmlal2, Rd, Rd, Rn, Rm, index, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_faddp_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_faddp, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_faddp_scalar(dc, Rd, Rn, Rn_elsz) instr_create_1dst_2src(dc, OP_faddp, Rd, Rn, Rn_elsz) |
| #define | INSTR_CREATE_fmul_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_fmul, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_fcmge_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_fcmge, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_fmaxnmp_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_fmaxnmp, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_fmaxnmp_scalar(dc, Rd, Rn, Rn_elsz) instr_create_1dst_2src(dc, OP_fmaxnmp, Rd, Rn, Rn_elsz) |
| #define | INSTR_CREATE_fmaxp_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_fmaxp, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_fmaxp_scalar(dc, Rd, Rn, Rn_elsz) instr_create_1dst_2src(dc, OP_fmaxp, Rd, Rn, Rn_elsz) |
| #define | INSTR_CREATE_facge_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_facge, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_facge(dc, Rd, Rn, Rm) instr_create_1dst_2src(dc, OP_facge, Rd, Rn, Rm) |
| #define | INSTR_CREATE_fcmle_vector_zero(dc, Rd, Rn, Rn_elsz) instr_create_1dst_3src(dc, OP_fcmle, Rd, Rn, opnd_create_immed_float(0.0), Rn_elsz) |
| #define | INSTR_CREATE_fcmle_zero(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_fcmle, Rd, Rn, opnd_create_immed_float(0.0)) |
| #define | INSTR_CREATE_fcmlt_vector_zero(dc, Rd, Rn, Rn_elsz) instr_create_1dst_3src(dc, OP_fcmlt, Rd, Rn, opnd_create_immed_float(0.0), Rn_elsz) |
| #define | INSTR_CREATE_fcmlt_zero(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_fcmlt, Rd, Rn, opnd_create_immed_float(0.0)) |
| #define | INSTR_CREATE_fdiv_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_fdiv, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_eor_vector(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_eor, Rd, Rm, Rn) |
| #define | INSTR_CREATE_bsl_vector(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_bsl, Rd, Rm, Rn) |
| #define | INSTR_CREATE_fminnmp_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_fminnmp, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_fminnmp_scalar(dc, Rd, Rn, Rn_elsz) instr_create_1dst_2src(dc, OP_fminnmp, Rd, Rn, Rn_elsz) |
| #define | INSTR_CREATE_fminnmv_vector(dc, Rd, Rn, Rn_elsz) instr_create_1dst_2src(dc, OP_fminnmv, Rd, Rn, Rn_elsz) |
| #define | INSTR_CREATE_fmlsl2_vector(dc, Rd, Rm, Rn) instr_create_1dst_4src(dc, OP_fmlsl2, Rd, Rd, Rm, Rn, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_fmlsl2_vector_idx(dc, Rd, Rm, Rn, index) instr_create_1dst_5src(dc, OP_fmlsl2, Rd, Rd, Rm, Rn, index, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_fabd_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_fabd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_facgt_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_facgt, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_facgt(dc, Rd, Rn, Rm) instr_create_1dst_2src(dc, OP_facgt, Rd, Rn, Rm) |
| #define | INSTR_CREATE_fcmgt_vector_zero(dc, Rd, Rn, Rn_elsz) instr_create_1dst_3src(dc, OP_fcmgt, Rd, Rn, opnd_create_immed_float(0.0), Rn_elsz) |
| #define | INSTR_CREATE_fcmgt_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_fcmgt, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_fcmgt_zero(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_fcmgt, Rd, Rn, opnd_create_immed_float(0.0)) |
| #define | INSTR_CREATE_fcmgt(dc, Rd, Rn, Rm) instr_create_1dst_2src(dc, OP_fcmgt, Rd, Rn, Rm) |
| #define | INSTR_CREATE_fminp_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_fminp, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_fminp_scalar(dc, Rd, Rn, Rn_elsz) instr_create_1dst_2src(dc, OP_fminp, Rd, Rn, Rn_elsz) |
| #define | INSTR_CREATE_bit_vector(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_bit, Rd, Rm, Rn) |
| #define | INSTR_CREATE_bif_vector(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_bif, Rd, Rm, Rn) |
| #define | INSTR_CREATE_fcvtas_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_fcvtas, Rd, Rm, width) |
| #define | INSTR_CREATE_fcvtau_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_fcvtau, Rd, Rm, width) |
| #define | INSTR_CREATE_fcvtms_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_fcvtms, Rd, Rm, width) |
| #define | INSTR_CREATE_fcvtmu_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_fcvtmu, Rd, Rm, width) |
| #define | INSTR_CREATE_fcvtns_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_fcvtns, Rd, Rm, width) |
| #define | INSTR_CREATE_fcvtnu_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_fcvtnu, Rd, Rm, width) |
| #define | INSTR_CREATE_fcvtps_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_fcvtps, Rd, Rm, width) |
| #define | INSTR_CREATE_fcvtpu_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_fcvtpu, Rd, Rm, width) |
| #define | INSTR_CREATE_fcvtzs_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_fcvtzs, Rd, Rm, width) |
| #define | INSTR_CREATE_fcvtzu_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_fcvtzu, Rd, Rm, width) |
| #define | INSTR_CREATE_fcvtzu_vector_fixed(dc, Rd, Rm, width, fbits) instr_create_1dst_3src(dc, OP_fcvtzu, Rd, Rm, width, fbits) |
| #define | INSTR_CREATE_sli_vector(dc, Rd, Rn, width, shift) instr_create_1dst_3src(dc, OP_sli, Rd, Rn, width, shift) |
| #define | INSTR_CREATE_uqshrn_vector(dc, Rd, Rn, width, shift) instr_create_1dst_3src(dc, OP_uqshrn, Rd, Rn, width, shift) |
| #define | INSTR_CREATE_ucvtf_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_ucvtf, Rd, Rm, width) |
| #define | INSTR_CREATE_ucvtf_vector_fixed(dc, Rd, Rm, width, fbits) instr_create_1dst_3src(dc, OP_ucvtf, Rd, Rm, width, fbits) |
| #define | INSTR_CREATE_scvtf_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_scvtf, Rd, Rm, width) |
| #define | INSTR_CREATE_scvtf_vector_fixed(dc, Rd, Rm, width, fbits) instr_create_1dst_3src(dc, OP_scvtf, Rd, Rm, width, fbits) |
| #define | INSTR_CREATE_sha512h(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_4src(dc, OP_sha512h, Rd, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_sha512h2(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_4src(dc, OP_sha512h2, Rd, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_sha512su0(dc, Rd, Rn, Rn_elsz) instr_create_1dst_3src(dc, OP_sha512su0, Rd, Rd, Rn, Rn_elsz) |
| #define | INSTR_CREATE_sha512su1(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_4src(dc, OP_sha512su1, Rd, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_rax1(dc, Rd, Rn, Rm) instr_create_1dst_3src(dc, OP_rax1, Rd, Rn, Rm, OPND_CREATE_DOUBLE()) |
| #define | INSTR_CREATE_xar(dc, Rd, Rn, Rm, imm6) instr_create_1dst_4src(dc, OP_xar, Rd, Rn, Rm, imm6, OPND_CREATE_DOUBLE()) |
| #define | INSTR_CREATE_ldr_imm(dc, Rt, Xn, Rn, imm) instr_create_2dst_3src(dc, OP_ldr, Rt, Xn, Rn, Xn, imm) |
| #define | INSTR_CREATE_str_imm(dc, Rt, Xt, Xn, imm) instr_create_2dst_3src(dc, OP_str, Rt, Xn, Xt, Xn, imm) |
| #define | INSTR_CREATE_fmov_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fmov, Rd, Rm) |
| #define | INSTR_CREATE_fabs_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fabs, Rd, Rm) |
| #define | INSTR_CREATE_fneg_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fneg, Rd, Rm) |
| #define | INSTR_CREATE_fsqrt_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fsqrt, Rd, Rm) |
| #define | INSTR_CREATE_fsqrt_vector(dc, Rd, Rn, Rn_elsz) instr_create_1dst_2src(dc, OP_fsqrt, Rd, Rn, Rn_elsz) |
| #define | INSTR_CREATE_fcvt_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fcvt, Rd, Rm) |
| #define | INSTR_CREATE_fcvtas_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fcvtas, Rd, Rm) |
| #define | INSTR_CREATE_fcvtau_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fcvtau, Rd, Rm) |
| #define | INSTR_CREATE_fcvtms_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fcvtms, Rd, Rm) |
| #define | INSTR_CREATE_fcvtmu_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fcvtmu, Rd, Rm) |
| #define | INSTR_CREATE_fcvtns_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fcvtns, Rd, Rm) |
| #define | INSTR_CREATE_fcvtnu_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fcvtnu, Rd, Rm) |
| #define | INSTR_CREATE_fcvtps_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fcvtps, Rd, Rm) |
| #define | INSTR_CREATE_fcvtpu_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fcvtpu, Rd, Rm) |
| #define | INSTR_CREATE_fcvtzs_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fcvtzs, Rd, Rm) |
| #define | INSTR_CREATE_fcvtzs_scalar_fixed(dc, Rd, Rm, fbits) instr_create_1dst_2src(dc, OP_fcvtzs, Rd, Rm, fbits) |
| #define | INSTR_CREATE_fcvtzu_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_fcvtzu, Rd, Rm) |
| #define | INSTR_CREATE_fcvtzu_scalar_fixed(dc, Rd, Rm, fbits) instr_create_1dst_2src(dc, OP_fcvtzu, Rd, Rm, fbits) |
| #define | INSTR_CREATE_ucvtf_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_ucvtf, Rd, Rm) |
| #define | INSTR_CREATE_ucvtf_scalar_fixed(dc, Rd, Rm, fbits) instr_create_1dst_2src(dc, OP_ucvtf, Rd, Rm, fbits) |
| #define | INSTR_CREATE_scvtf_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_scvtf, Rd, Rm) |
| #define | INSTR_CREATE_scvtf_scalar_fixed(dc, Rd, Rm, fbits) instr_create_1dst_2src(dc, OP_scvtf, Rd, Rm, fbits) |
| #define | INSTR_CREATE_frintn_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_frintn, Rd, Rm) |
| #define | INSTR_CREATE_frintn_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_frintn, Rd, Rm, width) |
| #define | INSTR_CREATE_frintp_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_frintp, Rd, Rm) |
| #define | INSTR_CREATE_frintp_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_frintp, Rd, Rm, width) |
| #define | INSTR_CREATE_frintm_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_frintm, Rd, Rm) |
| #define | INSTR_CREATE_frintm_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_frintm, Rd, Rm, width) |
| #define | INSTR_CREATE_frintz_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_frintz, Rd, Rm) |
| #define | INSTR_CREATE_frintz_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_frintz, Rd, Rm, width) |
| #define | INSTR_CREATE_frinta_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_frinta, Rd, Rm) |
| #define | INSTR_CREATE_frinta_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_frinta, Rd, Rm, width) |
| #define | INSTR_CREATE_frintx_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_frintx, Rd, Rm) |
| #define | INSTR_CREATE_frintx_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_frintx, Rd, Rm, width) |
| #define | INSTR_CREATE_frinti_scalar(dc, Rd, Rm) instr_create_1dst_1src(dc, OP_frinti, Rd, Rm) |
| #define | INSTR_CREATE_frinti_vector(dc, Rd, Rm, width) instr_create_1dst_2src(dc, OP_frinti, Rd, Rm, width) |
| #define | INSTR_CREATE_ldpsw(dc, Xt1, Xt2, Xn, Xr, imm) instr_create_3dst_3src(dc, OP_ldpsw, Xt1, Xt2, Xn, Xr, Xn, imm) |
| #define | INSTR_CREATE_ldpsw_2(dc, Xt1, Xt2, Xn) instr_create_2dst_1src(dc, OP_ldpsw, Xt1, Xt2, Xn) |
| #define | INSTR_CREATE_fmul_scalar(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_fmul, Rd, Rm, Rn) |
| #define | INSTR_CREATE_fdiv_scalar(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_fdiv, Rd, Rm, Rn) |
| #define | INSTR_CREATE_fadd_scalar(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_fadd, Rd, Rm, Rn) |
| #define | INSTR_CREATE_fsub_scalar(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_fsub, Rd, Rm, Rn) |
| #define | INSTR_CREATE_fmax_scalar(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_fmax, Rd, Rm, Rn) |
| #define | INSTR_CREATE_fmin_scalar(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_fmin, Rd, Rm, Rn) |
| #define | INSTR_CREATE_fmaxnm_scalar(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_fmaxnm, Rd, Rm, Rn) |
| #define | INSTR_CREATE_fminnm_scalar(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_fminnm, Rd, Rm, Rn) |
| #define | INSTR_CREATE_fnmul_scalar(dc, Rd, Rm, Rn) instr_create_1dst_2src(dc, OP_fnmul, Rd, Rm, Rn) |
| #define | INSTR_CREATE_fmadd_scalar(dc, Rd, Rm, Rn, Ra) instr_create_1dst_3src(dc, OP_fmadd, Rd, Rm, Rn, Ra) |
| #define | INSTR_CREATE_fmsub_scalar(dc, Rd, Rm, Rn, Ra) instr_create_1dst_3src(dc, OP_fmsub, Rd, Rm, Rn, Ra) |
| #define | INSTR_CREATE_fnmadd_scalar(dc, Rd, Rm, Rn, Ra) instr_create_1dst_3src(dc, OP_fnmadd, Rd, Rm, Rn, Ra) |
| #define | INSTR_CREATE_fnmsub_scalar(dc, Rd, Rm, Rn, Ra) instr_create_1dst_3src(dc, OP_fnmsub, Rd, Rm, Rn, Ra) |
| #define | INSTR_CREATE_ld2_multi_2(dc, Vt1, Vt2, Xn, disp, offset, elsz) instr_create_3dst_4src(dc, OP_ld2, Vt1, Vt2, Xn, disp, Xn, offset, elsz) |
| #define | INSTR_CREATE_ld2(dc, Vt1, Vt2, Xn, index, elsz) instr_create_2dst_3src(dc, OP_ld2, Vt1, Vt2, Xn, index, elsz) |
| #define | INSTR_CREATE_ld2_2(dc, Vt1, Vt2, Xn, Xnd, index, offset, elsz) instr_create_3dst_5src(dc, OP_ld2, Vt1, Vt2, Xn, Xnd, index, Xn, offset, elsz) |
| #define | INSTR_CREATE_ld2r(dc, Vt1, Vt2, Xn, elsz) instr_create_2dst_2src(dc, OP_ld2r, Vt1, Vt2, Xn, elsz) |
| #define | INSTR_CREATE_ld2r_2(dc, Vt1, Vt2, Xn, Xnd, Xm, elsz) instr_create_3dst_4src(dc, OP_ld2r, Vt1, Vt2, Xn, Xnd, Xn, Xm, elsz) |
| #define | INSTR_CREATE_ld3_multi(dc, Vt1, Vt2, Vt3, Xn, elsz) instr_create_3dst_2src(dc, OP_ld3, Vt1, Vt2, Vt3, Xn, elsz) |
| #define | INSTR_CREATE_ld3_multi_2(dc, Vt1, Vt2, Vt3, Xn, Xnd, Xm, elsz) instr_create_4dst_4src(dc, OP_ld3, Vt1, Vt2, Vt3, Xn, Xnd, Xn, Xm, elsz) |
| #define | INSTR_CREATE_ld3(dc, Vt1, Vt2, Vt3, Xn, index, elsz) instr_create_3dst_3src(dc, OP_ld3, Vt1, Vt2, Vt3, Xn, index, elsz) |
| #define | INSTR_CREATE_ld3_2(dc, Vt1, Vt2, Vt3, Xn, Xnd, index, offset, elsz) instr_create_4dst_5src(dc, OP_ld3, Vt1, Vt2, Vt3, Xn, Xnd, index, Xn, offset, elsz) |
| #define | INSTR_CREATE_ld3r(dc, Vt1, Vt2, Vt3, Xn, elsz) instr_create_3dst_2src(dc, OP_ld3r, Vt1, Vt2, Vt3, Xn, elsz) |
| #define | INSTR_CREATE_ld3r_2(dc, Vt1, Vt2, Vt3, Xn, Xnd, offset, elsz) instr_create_4dst_4src(dc, OP_ld3r, Vt1, Vt2, Vt3, Xn, Xnd, Xn, offset, elsz) |
| #define | INSTR_CREATE_ld4_multi(dc, Vt1, Vt2, Vt3, Vt4, Xn, elsz) instr_create_4dst_2src(dc, OP_ld4, Vt1, Vt2, Vt3, Vt4, Xn, elsz) |
| #define | INSTR_CREATE_ld4_multi_2(dc, Vt1, Vt2, Vt3, Vt4, Xn, Xnd, offset, elsz) instr_create_5dst_4src(dc, OP_ld4, Vt1, Vt2, Vt3, Vt4, Xn, Xnd, Xn, offset, elsz) |
| #define | INSTR_CREATE_ld4(dc, Vt1, Vt2, Vt3, Vt4, Xn, index, elsz) instr_create_4dst_3src(dc, OP_ld4, Vt1, Vt2, Vt3, Vt4, Xn, index, elsz) |
| #define | INSTR_CREATE_ld4_2(dc, Vt1, Vt2, Vt3, Vt4, Xn, Xnd, index, offset, elsz) |
| #define | INSTR_CREATE_ld4r(dc, Vt1, Vt2, Vt3, Vt4, Xn, elsz) instr_create_4dst_2src(dc, OP_ld4r, Vt1, Vt2, Vt3, Vt4, Xn, elsz) |
| #define | INSTR_CREATE_ld4r_2(dc, Vt1, Vt2, Vt3, Vt4, Xn, Xnd, offset, elsz) instr_create_5dst_4src(dc, OP_ld4r, Vt1, Vt2, Vt3, Vt4, Xn, Xnd, Xn, offset, elsz) |
| #define | INSTR_CREATE_ld1_multi_1(dc, q, r, s) instr_create_1dst_2src(dc, OP_ld1, q, r, s) |
| #define | INSTR_CREATE_st1_multi_1(dc, r, q, s) instr_create_1dst_2src(dc, OP_st1, r, q, s) |
| #define | INSTR_CREATE_saddl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_saddl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_saddl2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_saddl2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_saddw_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_saddw, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_saddw2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_saddw2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_ssubl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_ssubl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_ssubl2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_ssubl2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_ssubw_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_ssubw, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_ssubw2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_ssubw2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_addhn_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_addhn, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_addhn2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_addhn2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sabal_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sabal, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sabal2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sabal2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_subhn_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_subhn, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_subhn2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_subhn2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sabdl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sabdl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sabdl2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sabdl2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_smlal_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_smlal, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_smlal2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_smlal2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sqdmlal_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sqdmlal, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sqdmlal2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sqdmlal2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_smlsl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_smlsl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_smlsl2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_smlsl2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sqdmlsl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sqdmlsl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sqdmlsl2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sqdmlsl2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_smull_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_smull, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_smull2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_smull2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sqdmull_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sqdmull, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_sqdmull2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_sqdmull2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_pmull_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_pmull, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_pmull2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_pmull2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uaddl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uaddl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uaddl2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uaddl2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uaddw_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uaddw, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uaddw2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uaddw2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_usubl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_usubl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_usubl2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_usubl2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_usubw_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_usubw, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_usubw2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_usubw2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_raddhn_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_raddhn, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_raddhn2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_raddhn2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uabal_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uabal, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uabal2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uabal2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_rsubhn_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_rsubhn, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_rsubhn2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_rsubhn2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uabdl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uabdl, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_uabdl2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_uabdl2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_umlal_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_4src(dc, OP_umlal, Rd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_umlal2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_4src(dc, OP_umlal2, Rd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_umlsl_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_4src(dc, OP_umlsl, Rd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_umlsl2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_4src(dc, OP_umlsl2, Rd, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_umull_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_umull, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_umull2_vector(dc, Rd, Rm, Rn, width) instr_create_1dst_3src(dc, OP_umull2, Rd, Rm, Rn, width) |
| #define | INSTR_CREATE_fmov_vector_imm(dc, Rd, f, width) instr_create_1dst_2src(dc, OP_fmov, Rd, f, width) |
| #define | INSTR_CREATE_fmov_scalar_imm(dc, Rd, f) instr_create_1dst_1src(dc, OP_fmov, Rd, f) |
| #define | INSTR_CREATE_ldlar(dc, Rt, Rn) instr_create_1dst_1src(dc, OP_ldlar, Rt, Rn) |
| #define | INSTR_CREATE_ldlarb(dc, Rt, Rn) instr_create_1dst_1src(dc, OP_ldlarb, Rt, Rn) |
| #define | INSTR_CREATE_ldlarh(dc, Rt, Rn) instr_create_1dst_1src(dc, OP_ldlarh, Rt, Rn) |
| #define | INSTR_CREATE_stllr(dc, Rt, Rn) instr_create_1dst_1src(dc, OP_stllr, Rt, Rn) |
| #define | INSTR_CREATE_stllrb(dc, Rt, Rn) instr_create_1dst_1src(dc, OP_stllrb, Rt, Rn) |
| #define | INSTR_CREATE_stllrh(dc, Rt, Rn) instr_create_1dst_1src(dc, OP_stllrh, Rt, Rn) |
| #define | INSTR_CREATE_ldapr(dc, Rt, mem) instr_create_1dst_1src((dc), OP_ldapr, (Rt), (mem)) |
| #define | INSTR_CREATE_ldaprb(dc, Rt, mem) instr_create_1dst_1src((dc), OP_ldaprb, (Rt), (mem)) |
| #define | INSTR_CREATE_ldaprh(dc, Rt, mem) instr_create_1dst_1src((dc), OP_ldaprh, (Rt), (mem)) |
| #define | INSTR_CREATE_sm3partw1_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_sm3partw1, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_sm3partw2_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_sm3partw2, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_sm3ss1_vector(dc, Rd, Rn, Rm, Ra, Ra_elsz) instr_create_1dst_4src(dc, OP_sm3ss1, Rd, Rn, Rm, Ra, Ra_elsz) |
| #define | INSTR_CREATE_sm3tt1a_vector_indexed(dc, Rd, Rn, Rm, imm2, Rm_elsz) instr_create_1dst_4src(dc, OP_sm3tt1a, Rd, Rn, Rm, imm2, Rm_elsz) |
| #define | INSTR_CREATE_sm3tt1b_vector_indexed(dc, Rd, Rn, Rm, imm2, Rm_elsz) instr_create_1dst_4src(dc, OP_sm3tt1b, Rd, Rn, Rm, imm2, Rm_elsz) |
| #define | INSTR_CREATE_sm3tt2a_vector_indexed(dc, Rd, Rn, Rm, imm2, Rm_elsz) instr_create_1dst_4src(dc, OP_sm3tt2a, Rd, Rn, Rm, imm2, Rm_elsz) |
| #define | INSTR_CREATE_sm3tt2b_vector_indexed(dc, Rd, Rn, Rm, imm2, Rm_elsz) instr_create_1dst_4src(dc, OP_sm3tt2b, Rd, Rn, Rm, imm2, Rm_elsz) |
| #define | INSTR_CREATE_sm4e_vector(dc, Rd, Rn, Rn_elsz) instr_create_1dst_2src(dc, OP_sm4e, Rd, Rn, Rn_elsz) |
| #define | INSTR_CREATE_sm4ekey_vector(dc, Rd, Rn, Rm, Rm_elsz) instr_create_1dst_3src(dc, OP_sm4ekey, Rd, Rn, Rm, Rm_elsz) |
| #define | INSTR_CREATE_bcax(dc, Rd, Rn, Rm, Ra) instr_create_1dst_4src(dc, OP_bcax, Rd, Rn, Rm, Ra, OPND_CREATE_BYTE()) |
| #define | INSTR_CREATE_eor3(dc, Rd, Rn, Rm, Ra) instr_create_1dst_4src(dc, OP_eor3, Rd, Rn, Rm, Ra, OPND_CREATE_BYTE()) |
| #define | INSTR_CREATE_esb(dc) instr_create_0dst_0src(dc, OP_esb) |
| #define | INSTR_CREATE_psb_csync(dc) instr_create_0dst_0src(dc, OP_psb) |
| #define | INSTR_CREATE_fccmp(dc, Rn, Rm, nzcv, cond) instr_create_0dst_4src(dc, OP_fccmp, Rn, Rm, nzcv, cond) |
| #define | INSTR_CREATE_fccmpe(dc, Rn, Rm, nzcv, cond) instr_create_0dst_4src(dc, OP_fccmpe, Rn, Rm, nzcv, cond) |
| #define | INSTR_CREATE_fcsel(dc, Rd, Rn, Rm, cond) instr_create_1dst_3src(dc, OP_fcsel, Rd, Rn, Rm, cond) |
| #define | INSTR_CREATE_fcmp_zero(dc, Rn) instr_create_0dst_2src(dc, OP_fcmp, Rn, opnd_create_immed_float(0.0)) |
| #define | INSTR_CREATE_fcmp(dc, Rn, Rm) instr_create_0dst_2src(dc, OP_fcmp, Rn, Rm) |
| #define | INSTR_CREATE_fcmpe_zero(dc, Rn) instr_create_0dst_2src(dc, OP_fcmpe, Rn, opnd_create_immed_float(0.0)) |
| #define | INSTR_CREATE_fcmpe(dc, Rn, Rm) instr_create_0dst_2src(dc, OP_fcmpe, Rn, Rm) |
| #define | INSTR_CREATE_sdot_vector(dc, Rd, Rn, Rm) instr_create_1dst_4src(dc, OP_sdot, Rd, Rd, Rn, Rm, OPND_CREATE_BYTE()) |
| #define | INSTR_CREATE_sdot_vector_indexed(dc, Rd, Rn, Rm, index) instr_create_1dst_5src(dc, OP_sdot, Rd, Rd, Rn, Rm, index, OPND_CREATE_BYTE()) |
| #define | INSTR_CREATE_udot_vector(dc, Rd, Rn, Rm) instr_create_1dst_4src(dc, OP_udot, Rd, Rd, Rn, Rm, OPND_CREATE_BYTE()) |
| #define | INSTR_CREATE_udot_vector_indexed(dc, Rd, Rn, Rm, index) instr_create_1dst_5src(dc, OP_udot, Rd, Rd, Rn, Rm, index, OPND_CREATE_BYTE()) |
| #define | INSTR_CREATE_bfcvt(dc, Rd, Rn) instr_create_1dst_1src(dc, OP_bfcvt, Rd, Rn) |
| #define | INSTR_CREATE_bfcvtn2_vector(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_bfcvtn2, Rd, Rn, OPND_CREATE_SINGLE()) |
| #define | INSTR_CREATE_bfcvtn_vector(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_bfcvtn, Rd, Rn, OPND_CREATE_SINGLE()) |
| #define | INSTR_CREATE_bfdot_vector(dc, Rd, Rn, Rm) instr_create_1dst_4src(dc, OP_bfdot, Rd, Rd, Rn, Rm, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_bfdot_vector_idx(dc, Rd, Rn, Rm, index) instr_create_1dst_5src(dc, OP_bfdot, Rd, Rd, Rn, Rm, index, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_bfmlalb_vector(dc, Rd, Rn, Rm) instr_create_1dst_4src(dc, OP_bfmlalb, Rd, Rd, Rn, Rm, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_bfmlalb_vector_idx(dc, Rd, Rn, Rm, index) instr_create_1dst_5src(dc, OP_bfmlalb, Rd, Rd, Rn, Rm, index, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_bfmlalt_vector(dc, Rd, Rn, Rm) instr_create_1dst_4src(dc, OP_bfmlalt, Rd, Rd, Rn, Rm, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_bfmlalt_vector_idx(dc, Rd, Rn, Rm, index) instr_create_1dst_5src(dc, OP_bfmlalt, Rd, Rd, Rn, Rm, index, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_bfmmla_vector(dc, Rd, Rn, Rm) instr_create_1dst_4src(dc, OP_bfmmla, Rd, Rd, Rn, Rm, OPND_CREATE_HALF()) |
| #define | INSTR_CREATE_smmla_vector(dc, Rd, Rn, Rm) instr_create_1dst_4src(dc, OP_smmla, Rd, Rd, Rn, Rm, OPND_CREATE_BYTE()) |
| #define | INSTR_CREATE_sudot_vector_idx(dc, Rd, Rn, Rm, index) instr_create_1dst_5src(dc, OP_sudot, Rd, Rd, Rn, Rm, index, OPND_CREATE_BYTE()) |
| #define | INSTR_CREATE_ummla_vector(dc, Rd, Rn, Rm) instr_create_1dst_4src(dc, OP_ummla, Rd, Rd, Rn, Rm, OPND_CREATE_BYTE()) |
| #define | INSTR_CREATE_usmmla_vector(dc, Rd, Rn, Rm) instr_create_1dst_4src(dc, OP_usmmla, Rd, Rd, Rn, Rm, OPND_CREATE_BYTE()) |
| #define | INSTR_CREATE_usdot_vector(dc, Rd, Rn, Rm) instr_create_1dst_4src(dc, OP_usdot, Rd, Rd, Rn, Rm, OPND_CREATE_BYTE()) |
| #define | INSTR_CREATE_usdot_vector_idx(dc, Rd, Rn, Rm, index) instr_create_1dst_5src(dc, OP_usdot, Rd, Rd, Rn, Rm, index, OPND_CREATE_BYTE()) |
| #define | INSTR_CREATE_fcadd_vector(dc, Rd, Rn, Rm, rot, Rm_elsz) instr_create_1dst_5src(dc, OP_fcadd, Rd, Rd, Rn, Rm, rot, Rm_elsz) |
| #define | INSTR_CREATE_fcmla_vector(dc, Rd, Rn, Rm, rot, Rm_elsz) instr_create_1dst_5src(dc, OP_fcmla, Rd, Rd, Rn, Rm, rot, Rm_elsz) |
| #define | INSTR_CREATE_fcmla_vector_idx(dc, Rd, Rn, Rm, index, rot, Rm_elsz) instr_create_1dst_6src(dc, OP_fcmla, Rd, Rd, Rn, Rm, index, rot, Rm_elsz) |
| #define | INSTR_CREATE_orr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_orr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_eor_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_eor, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_and_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_and, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_bic_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_bic, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_movprfx_vector(dc, Zd, Zn) instr_create_1dst_1src(dc, OP_movprfx, Zd, Zn) |
| #define | INSTR_CREATE_movprfx_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_movprfx, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sqadd_sve_shift(dc, Zdn, imm, shift) instr_create_1dst_4src(dc, OP_sqadd, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift) |
| #define | INSTR_CREATE_sqadd_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_sqadd, Zd, Zn, Zm) |
| #define | INSTR_CREATE_sqsub_sve_shift(dc, Zdn, imm, shift) instr_create_1dst_4src(dc, OP_sqsub, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift) |
| #define | INSTR_CREATE_sqsub_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_sqsub, Zd, Zn, Zm) |
| #define | INSTR_CREATE_sub_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_sub, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sub_sve_shift(dc, Zdn, imm, shift) instr_create_1dst_4src(dc, OP_sub, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift) |
| #define | INSTR_CREATE_sub_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_sub, Zd, Zn, Zm) |
| #define | INSTR_CREATE_subr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_subr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_subr_sve_shift(dc, Zdn, imm, shift) instr_create_1dst_4src(dc, OP_subr, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift) |
| #define | INSTR_CREATE_uqadd_sve_shift(dc, Zdn, imm, shift) instr_create_1dst_4src(dc, OP_uqadd, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift) |
| #define | INSTR_CREATE_uqadd_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_uqadd, Zd, Zn, Zm) |
| #define | INSTR_CREATE_uqsub_sve_shift(dc, Zdn, imm, shift) instr_create_1dst_4src(dc, OP_uqsub, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift) |
| #define | INSTR_CREATE_uqsub_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_uqsub, Zd, Zn, Zm) |
| #define | INSTR_CREATE_add_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_add, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_add_sve_shift(dc, Zdn, imm, shift) instr_create_1dst_4src(dc, OP_add, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift) |
| #define | INSTR_CREATE_add_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_add, Zd, Zn, Zm) |
| #define | INSTR_CREATE_cpy_sve_shift_pred(dc, Zd, Pg, simm, shift) |
| #define | INSTR_CREATE_cpy_sve_pred(dc, Zd, Pg, Rn_or_Vn) INSTR_PRED(instr_create_1dst_2src(dc, OP_cpy, Zd, Pg, Rn_or_Vn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ptest_sve_pred(dc, Pg, Pn) INSTR_PRED(instr_create_0dst_2src(dc, OP_ptest, Pg, Pn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_mad_sve_pred(dc, Zdn, Pg, Zm, Za) INSTR_PRED(instr_create_1dst_4src(dc, OP_mad, Zdn, Zdn, Pg, Zm, Za), DR_PRED_MASKED) |
| #define | INSTR_CREATE_mla_sve_pred(dc, Zda, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_4src(dc, OP_mla, Zda, Zda, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_mls_sve_pred(dc, Zda, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_4src(dc, OP_mls, Zda, Zda, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_msb_sve_pred(dc, Zdn, Pg, Zm, Za) INSTR_PRED(instr_create_1dst_4src(dc, OP_msb, Zdn, Zdn, Pg, Zm, Za), DR_PRED_MASKED) |
| #define | INSTR_CREATE_mul_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_mul, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_mul_sve_imm(dc, Zdn, simm) instr_create_1dst_2src(dc, OP_mul, Zdn, Zdn, simm) |
| #define | INSTR_CREATE_smulh_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_smulh, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_umulh_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_umulh, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fexpa_sve(dc, Zd, Zn) instr_create_1dst_1src(dc, OP_fexpa, Zd, Zn) |
| #define | INSTR_CREATE_ftmad_sve(dc, Zdn, Zm, imm) instr_create_1dst_3src(dc, OP_ftmad, Zdn, Zdn, Zm, imm) |
| #define | INSTR_CREATE_ftsmul_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_ftsmul, Zd, Zn, Zm) |
| #define | INSTR_CREATE_ftssel_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_ftssel, Zd, Zn, Zm) |
| #define | INSTR_CREATE_abs_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_abs, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cnot_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_cnot, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_neg_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_neg, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sabd_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_sabd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_smax_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_smax, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_smax_sve(dc, Zdn, simm) instr_create_1dst_2src(dc, OP_smax, Zdn, Zdn, simm) |
| #define | INSTR_CREATE_smin_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_smin, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_smin_sve(dc, Zdn, simm) instr_create_1dst_2src(dc, OP_smin, Zdn, Zdn, simm) |
| #define | INSTR_CREATE_uabd_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_uabd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_facge_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_facge, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_facgt_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_facgt, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sdiv_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_sdiv, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sdivr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_sdivr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_udiv_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_udiv, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_udivr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_udivr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_umax_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_umax, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_umax_sve(dc, Zdn, imm) instr_create_1dst_2src(dc, OP_umax, Zdn, Zdn, imm) |
| #define | INSTR_CREATE_umin_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_umin, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_umin_sve(dc, Zdn, imm) instr_create_1dst_2src(dc, OP_umin, Zdn, Zdn, imm) |
| #define | INSTR_CREATE_sxtb_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_sxtb, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sxth_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_sxth, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sxtw_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_sxtw, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uxtb_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_uxtb, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uxth_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_uxth, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uxtw_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_uxtw, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcmeq_sve_zero_pred(dc, Pd, Pg, Zn) |
| #define | INSTR_CREATE_fcmeq_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmeq, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcmge_sve_zero_pred(dc, Pd, Pg, Zn) |
| #define | INSTR_CREATE_fcmge_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmge, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcmgt_sve_zero_pred(dc, Pd, Pg, Zn) |
| #define | INSTR_CREATE_fcmgt_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmgt, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcmle_sve_zero_pred(dc, Pd, Pg, Zn) |
| #define | INSTR_CREATE_fcmlt_sve_zero_pred(dc, Pd, Pg, Zn) |
| #define | INSTR_CREATE_fcmne_sve_zero_pred(dc, Pd, Pg, Zn) |
| #define | INSTR_CREATE_fcmne_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmne, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcmuo_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmuo, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcmle_sve_pred(dc, Pd, Pg, Zm, Zn) INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmle, Pd, Pg, Zm, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcmlt_sve_pred(dc, Pd, Pg, Zm, Zn) INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmlt, Pd, Pg, Zm, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmpeq_sve_pred_simm(dc, Pd, Pg, Zn, simm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpeq, Pd, Pg, Zn, simm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmpeq_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpeq, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmpge_sve_pred_simm(dc, Pd, Pg, Zn, simm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpge, Pd, Pg, Zn, simm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmpge_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpge, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmpgt_sve_pred_simm(dc, Pd, Pg, Zn, simm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpgt, Pd, Pg, Zn, simm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmpgt_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpgt, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmphi_sve_pred_imm(dc, Pd, Pg, Zn, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphi, Pd, Pg, Zn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmphi_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphi, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmphs_sve_pred_imm(dc, Pd, Pg, Zn, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphs, Pd, Pg, Zn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmphs_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphs, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmple_sve_pred_simm(dc, Pd, Pg, Zn, simm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmple, Pd, Pg, Zn, simm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmple_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmple, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmplo_sve_pred_imm(dc, Pd, Pg, Zn, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplo, Pd, Pg, Zn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmplo_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplo, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmpls_sve_pred_imm(dc, Pd, Pg, Zn, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpls, Pd, Pg, Zn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmpls_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpls, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmplt_sve_pred_simm(dc, Pd, Pg, Zn, simm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplt, Pd, Pg, Zn, simm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmplt_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplt, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmpne_sve_pred_simm(dc, Pd, Pg, Zn, simm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpne, Pd, Pg, Zn, simm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cmpne_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpne, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_setffr_sve(dc) instr_create_0dst_0src(dc, OP_setffr) |
| #define | INSTR_CREATE_rdffr_sve(dc, Pd) instr_create_1dst_0src(dc, OP_rdffr, Pd) |
| #define | INSTR_CREATE_rdffr_sve_pred(dc, Pd, Pg) INSTR_PRED(instr_create_1dst_1src(dc, OP_rdffr, Pd, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_rdffrs_sve_pred(dc, Pd, Pg) INSTR_PRED(instr_create_1dst_1src(dc, OP_rdffrs, Pd, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_wrffr_sve(dc, Pn) instr_create_0dst_1src(dc, OP_wrffr, Pn) |
| #define | INSTR_CREATE_cntp_sve_pred(dc, Rd, Pg, Pn) INSTR_PRED(instr_create_1dst_2src(dc, OP_cntp, Rd, Pg, Pn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_decp_sve(dc, Rdn, Pm) instr_create_1dst_2src(dc, OP_decp, Rdn, Rdn, Pm) |
| #define | INSTR_CREATE_decp_sve_vector(dc, Zdn, Pm) instr_create_1dst_2src(dc, OP_decp, Zdn, Zdn, Pm) |
| #define | INSTR_CREATE_incp_sve(dc, Rdn, Pm) instr_create_1dst_2src(dc, OP_incp, Rdn, Rdn, Pm) |
| #define | INSTR_CREATE_incp_sve_vector(dc, Zdn, Pm) instr_create_1dst_2src(dc, OP_incp, Zdn, Zdn, Pm) |
| #define | INSTR_CREATE_sqdecp_sve(dc, Rdn, Pm) instr_create_1dst_2src(dc, OP_sqdecp, Rdn, Rdn, Pm) |
| #define | INSTR_CREATE_sqdecp_sve_wide(dc, Rdn, Pm) |
| #define | INSTR_CREATE_sqdecp_sve_vector(dc, Zdn, Pm) instr_create_1dst_2src(dc, OP_sqdecp, Zdn, Zdn, Pm) |
| #define | INSTR_CREATE_sqincp_sve(dc, Rdn, Pm) instr_create_1dst_2src(dc, OP_sqincp, Rdn, Rdn, Pm) |
| #define | INSTR_CREATE_sqincp_sve_wide(dc, Rdn, Pm) |
| #define | INSTR_CREATE_sqincp_sve_vector(dc, Zdn, Pm) instr_create_1dst_2src(dc, OP_sqincp, Zdn, Zdn, Pm) |
| #define | INSTR_CREATE_uqdecp_sve(dc, Rdn, Pm) instr_create_1dst_2src(dc, OP_uqdecp, Rdn, Rdn, Pm) |
| #define | INSTR_CREATE_uqdecp_sve_vector(dc, Zdn, Pm) instr_create_1dst_2src(dc, OP_uqdecp, Zdn, Zdn, Pm) |
| #define | INSTR_CREATE_uqincp_sve(dc, Rdn, Pm) instr_create_1dst_2src(dc, OP_uqincp, Rdn, Rdn, Pm) |
| #define | INSTR_CREATE_uqincp_sve_vector(dc, Zdn, Pm) instr_create_1dst_2src(dc, OP_uqincp, Zdn, Zdn, Pm) |
| #define | INSTR_CREATE_and_sve_imm(dc, Zdn, imm) instr_create_1dst_2src(dc, OP_and, Zdn, Zdn, imm) |
| #define | INSTR_CREATE_bic_sve_imm(dc, Zdn, imm) instr_create_1dst_2src(dc, OP_and, Zdn, Zdn, opnd_invert_immed_int(imm)) |
| #define | INSTR_CREATE_eor_sve_imm(dc, Zdn, imm) instr_create_1dst_2src(dc, OP_eor, Zdn, Zdn, imm) |
| #define | INSTR_CREATE_orr_sve_imm(dc, Zdn, imm) instr_create_1dst_2src(dc, OP_orr, Zdn, Zdn, imm) |
| #define | INSTR_CREATE_orn_sve_imm(dc, Zdn, imm) instr_create_1dst_2src(dc, OP_orr, Zdn, Zdn, opnd_invert_immed_int(imm)) |
| #define | INSTR_CREATE_and_sve_pred_b(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_and, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_and_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_and, Zd, Zn, Zm) |
| #define | INSTR_CREATE_ands_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_ands, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_bic_sve_pred_b(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_bic, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_bic_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_bic, Zd, Zn, Zm) |
| #define | INSTR_CREATE_bics_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_bics, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_eor_sve_pred_b(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_eor, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_not_sve_pred_b(dc, Pd, Pg, Pn) |
| #define | INSTR_CREATE_eor_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_eor, Zd, Zn, Zm) |
| #define | INSTR_CREATE_eors_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_eors, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_nand_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_nand, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_nands_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_nands, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_nor_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_nor, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_nors_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_nors, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_not_sve_pred_vec(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_not, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_orn_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_orn, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_orns_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_orns, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_orr_sve_pred_b(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_orr, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_orr_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_orr, Zd, Zn, Zm) |
| #define | INSTR_CREATE_orrs_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_orrs, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_clasta_sve_scalar(dc, Rdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_clasta, Rdn, Pg, Rdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_clasta_sve_simd_fp(dc, Vdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_clasta, Vdn, Pg, Vdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_clasta_sve_vector(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_clasta, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_clastb_sve_scalar(dc, Rdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_clastb, Rdn, Pg, Rdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_clastb_sve_simd_fp(dc, Vdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_clastb, Vdn, Pg, Vdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_clastb_sve_vector(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_clastb, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_lasta_sve_scalar(dc, Rd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_lasta, Rd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_lasta_sve_simd_fp(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_lasta, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_lastb_sve_scalar(dc, Rd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_lastb, Rd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_lastb_sve_simd_fp(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_lastb, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cnt_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_cnt, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cntb(dc, Rd, pattern, imm) instr_create_1dst_3src(dc, OP_cntb, Rd, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_cntd(dc, Rd, pattern, imm) instr_create_1dst_3src(dc, OP_cntd, Rd, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_cnth(dc, Rd, pattern, imm) instr_create_1dst_3src(dc, OP_cnth, Rd, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_cntw(dc, Rd, pattern, imm) instr_create_1dst_3src(dc, OP_cntw, Rd, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_decb(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_decb, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_decd(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_decd, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_decd_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_decd, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_dech(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_dech, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_dech_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_dech, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_decw(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_decw, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_decw_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_decw, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_incb(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_incb, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_incd(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_incd, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_incd_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_incd, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_inch(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_inch, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_inch_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_inch, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_incw(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_incw, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_incw_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_incw, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqdecb_wide(dc, Rdn, pattern, imm) |
| #define | INSTR_CREATE_sqdecb(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqdecb, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqdecd_wide(dc, Rdn, pattern, imm) |
| #define | INSTR_CREATE_sqdecd(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqdecd, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqdecd_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqdecd, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqdech_wide(dc, Rdn, pattern, imm) |
| #define | INSTR_CREATE_sqdech(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqdech, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqdech_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqdech, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqdecw_wide(dc, Rdn, pattern, imm) |
| #define | INSTR_CREATE_sqdecw(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqdecw, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqdecw_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqdecw, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqincb_wide(dc, Rdn, pattern, imm) |
| #define | INSTR_CREATE_sqincb(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqincb, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqincd_wide(dc, Rdn, pattern, imm) |
| #define | INSTR_CREATE_sqincd(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqincd, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqincd_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqincd, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqinch_wide(dc, Rdn, pattern, imm) |
| #define | INSTR_CREATE_sqinch(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqinch, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqinch_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqinch, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqincw_wide(dc, Rdn, pattern, imm) |
| #define | INSTR_CREATE_sqincw(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqincw, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_sqincw_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_sqincw, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqdecb(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqdecb, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqdecd(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqdecd, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqdecd_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqdecd, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqdech(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqdech, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqdech_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqdech, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqdecw(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqdecw, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqdecw_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqdecw, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqincb(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqincb, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqincd(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqincd, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqincd_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqincd, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqinch(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqinch, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqinch_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqinch, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqincw(dc, Rdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqincw, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_uqincw_sve(dc, Zdn, pattern, imm) instr_create_1dst_4src(dc, OP_uqincw, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
| #define | INSTR_CREATE_brka_sve_pred(dc, Pd, Pg, Pn) INSTR_PRED(instr_create_1dst_2src(dc, OP_brka, Pd, Pg, Pn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_brkas_sve_pred(dc, Pd, Pg, Pn) INSTR_PRED(instr_create_1dst_2src(dc, OP_brkas, Pd, Pg, Pn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_brkb_sve_pred(dc, Pd, Pg, Pn) INSTR_PRED(instr_create_1dst_2src(dc, OP_brkb, Pd, Pg, Pn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_brkbs_sve_pred(dc, Pd, Pg, Pn) INSTR_PRED(instr_create_1dst_2src(dc, OP_brkbs, Pd, Pg, Pn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_brkn_sve_pred(dc, Pdm, Pg, Pn) INSTR_PRED(instr_create_1dst_3src(dc, OP_brkn, Pdm, Pg, Pn, Pdm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_brkns_sve_pred(dc, Pdm, Pg, Pn) INSTR_PRED(instr_create_1dst_3src(dc, OP_brkns, Pdm, Pg, Pn, Pdm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_brkpa_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpa, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_brkpas_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpas, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_brkpb_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpb, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_brkpbs_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpbs, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_whilele_sve(dc, Pd, Rn, Rm) instr_create_1dst_2src(dc, OP_whilele, Pd, Rn, Rm) |
| #define | INSTR_CREATE_whilelo_sve(dc, Pd, Rn, Rm) instr_create_1dst_2src(dc, OP_whilelo, Pd, Rn, Rm) |
| #define | INSTR_CREATE_whilels_sve(dc, Pd, Rn, Rm) instr_create_1dst_2src(dc, OP_whilels, Pd, Rn, Rm) |
| #define | INSTR_CREATE_whilelt_sve(dc, Pd, Rn, Rm) instr_create_1dst_2src(dc, OP_whilelt, Pd, Rn, Rm) |
| #define | INSTR_CREATE_tbl_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_tbl, Zd, Zn, Zm) |
| #define | INSTR_CREATE_tbl_sve_mulvec(dc, Zd, Zn, Zm) instr_create_1dst_3src(dc, OP_tbl, Zd, Zn, opnd_create_increment_reg(Zn, 1), Zm) |
| #define | INSTR_CREATE_dup_sve_shift(dc, Zd, simm, shift) instr_create_1dst_3src(dc, OP_dup, Zd, simm, OPND_CREATE_LSL(), shift) |
| #define | INSTR_CREATE_dup_sve_idx(dc, Zd, Zn, index) instr_create_1dst_2src(dc, OP_dup, Zd, Zn, index) |
| #define | INSTR_CREATE_dup_sve_scalar(dc, Zd, Rn) instr_create_1dst_1src(dc, OP_dup, Zd, Rn) |
| #define | INSTR_CREATE_insr_sve_scalar(dc, Zd, Rm) instr_create_1dst_2src(dc, OP_insr, Zd, Zd, Rm) |
| #define | INSTR_CREATE_insr_sve_simd_fp(dc, Zdn, Vm) instr_create_1dst_2src(dc, OP_insr, Zdn, Zdn, Vm) |
| #define | INSTR_CREATE_ext_sve(dc, Zdn, Zm, imm) instr_create_1dst_3src(dc, OP_ext, Zdn, Zdn, Zm, imm) |
| #define | INSTR_CREATE_splice_sve_des(dc, Zdn, Pv, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_splice, Zdn, Pv, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_splice_sve_con(dc, Zd, Pv, Zn) |
| #define | INSTR_CREATE_rev_sve_pred(dc, Pd, Pn) instr_create_1dst_1src(dc, OP_rev, Pd, Pn) |
| #define | INSTR_CREATE_rev_sve(dc, Zd, Zn) instr_create_1dst_1src(dc, OP_rev, Zd, Zn) |
| #define | INSTR_CREATE_revb_sve(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_revb, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_revh_sve(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_revh, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_revw_sve(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_revw, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_compact_sve(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_compact, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_punpkhi_sve(dc, Pd, Pn) instr_create_1dst_1src(dc, OP_punpkhi, Pd, Pn) |
| #define | INSTR_CREATE_punpklo_sve(dc, Pd, Pn) instr_create_1dst_1src(dc, OP_punpklo, Pd, Pn) |
| #define | INSTR_CREATE_sunpkhi_sve(dc, Zd, Zn) instr_create_1dst_1src(dc, OP_sunpkhi, Zd, Zn) |
| #define | INSTR_CREATE_sunpklo_sve(dc, Zd, Zn) instr_create_1dst_1src(dc, OP_sunpklo, Zd, Zn) |
| #define | INSTR_CREATE_uunpkhi_sve(dc, Zd, Zn) instr_create_1dst_1src(dc, OP_uunpkhi, Zd, Zn) |
| #define | INSTR_CREATE_uunpklo_sve(dc, Zd, Zn) instr_create_1dst_1src(dc, OP_uunpklo, Zd, Zn) |
| #define | INSTR_CREATE_uzp1_sve_pred(dc, Pd, Pn, Pm) instr_create_1dst_2src(dc, OP_uzp1, Pd, Pn, Pm) |
| #define | INSTR_CREATE_uzp2_sve_pred(dc, Pd, Pn, Pm) instr_create_1dst_2src(dc, OP_uzp2, Pd, Pn, Pm) |
| #define | INSTR_CREATE_uzp2_sve_vector(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_uzp2, Zd, Zn, Zm) |
| #define | INSTR_CREATE_zip1_sve_pred(dc, Pd, Pn, Pm) instr_create_1dst_2src(dc, OP_zip1, Pd, Pn, Pm) |
| #define | INSTR_CREATE_zip1_sve_vector(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_zip1, Zd, Zn, Zm) |
| #define | INSTR_CREATE_zip2_sve_pred(dc, Pd, Pn, Pm) instr_create_1dst_2src(dc, OP_zip2, Pd, Pn, Pm) |
| #define | INSTR_CREATE_zip2_sve_vector(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_zip2, Zd, Zn, Zm) |
| #define | INSTR_CREATE_trn1_sve_pred(dc, Pd, Pn, Pm) instr_create_1dst_2src(dc, OP_trn1, Pd, Pn, Pm) |
| #define | INSTR_CREATE_trn1_sve_vector(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_trn1, Zd, Zn, Zm) |
| #define | INSTR_CREATE_trn2_sve_pred(dc, Pd, Pn, Pm) instr_create_1dst_2src(dc, OP_trn2, Pd, Pn, Pm) |
| #define | INSTR_CREATE_trn2_sve_vector(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_trn2, Zd, Zn, Zm) |
| #define | INSTR_CREATE_dupm_sve(dc, Zd, imm) instr_create_1dst_1src(dc, OP_dupm, Zd, imm) |
| #define | INSTR_CREATE_eon_sve_imm(dc, Zdn, imm) instr_create_1dst_2src(dc, OP_eor, Zdn, Zdn, opnd_invert_immed_int(imm)) |
| #define | INSTR_CREATE_pfalse_sve(dc, Pd) instr_create_1dst_0src(dc, OP_pfalse, Pd) |
| #define | INSTR_CREATE_pfirst_sve(dc, Pdn, Pg) INSTR_PRED(instr_create_1dst_2src(dc, OP_pfirst, Pdn, Pg, Pdn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sel_sve_pred(dc, Pd, Pg, Pn, Pm) INSTR_PRED(instr_create_1dst_3src(dc, OP_sel, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sel_sve_vector(dc, Zd, Pv, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_sel, Zd, Pv, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_mov_sve_pred(dc, Pd, Pn) |
| #define | INSTR_CREATE_movs_sve_pred(dc, Pd, Pg, Pn) INSTR_PRED(instr_create_1dst_3src(dc, OP_ands, Pd, Pg, Pn, Pn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ptrue_sve(dc, Pd, pattern) instr_create_1dst_1src(dc, OP_ptrue, Pd, pattern) |
| #define | INSTR_CREATE_ptrues_sve(dc, Pd, pattern) instr_create_1dst_1src(dc, OP_ptrues, Pd, pattern) |
| #define | INSTR_CREATE_asr_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_asr, Zd, Zn, imm) |
| #define | INSTR_CREATE_asr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_asr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_asr_sve_pred_wide(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_asr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_asr_sve_wide(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_asr, Zd, Zn, Zm) |
| #define | INSTR_CREATE_asrd_sve_pred(dc, Zdn, Pg, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_asrd, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_asrr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_asrr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cls_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_cls, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_clz_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_clz, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cnt_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_cnt, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_lsl_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_lsl, Zd, Zn, imm) |
| #define | INSTR_CREATE_lsl_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_lsl, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_lsl_sve_pred_wide(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_lsl, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_lsl_sve_wide(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_lsl, Zd, Zn, Zm) |
| #define | INSTR_CREATE_lslr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_lslr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_lsr_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_lsr, Zd, Zn, imm) |
| #define | INSTR_CREATE_lsr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_lsr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_lsr_sve_pred_wide(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_lsr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_lsr_sve_wide(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_lsr, Zd, Zn, Zm) |
| #define | INSTR_CREATE_lsrr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_lsrr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_rbit_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_rbit, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_andv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_andv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_eorv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_eorv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fadda_sve_pred(dc, Vdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fadda, Vdn, Pg, Vdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_faddv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_faddv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmaxnmv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_fmaxnmv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmaxv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_fmaxv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fminnmv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_fminnmv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fminv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_fminv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_orv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_orv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_saddv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_saddv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_smaxv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_smaxv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sminv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_sminv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uaddv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_uaddv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_umaxv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_umaxv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uminv_sve_pred(dc, Vd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_uminv, Vd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fdup_sve(dc, Zd, imm) instr_create_1dst_1src(dc, OP_fdup, Zd, imm) |
| #define | INSTR_CREATE_ld1rb_sve(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rb, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1rh_sve(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rh, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1rw_sve(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rw, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1rd_sve(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rd, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1rsb_sve(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rsb, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1rsh_sve(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rsh, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1rsw_sve(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rsw, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_index_sve(dc, Zd, Rn_or_imm, Rm_or_imm) instr_create_1dst_2src(dc, OP_index, Zd, Rn_or_imm, Rm_or_imm) |
| #define | INSTR_CREATE_fcvt_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvt, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcvtzs_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvtzs, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcvtzu_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvtzu, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_frinta_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_frinta, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_frinti_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_frinti, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_frintm_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_frintm, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_frintn_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_frintn, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_frintp_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_frintp, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_frintx_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_frintx, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_frintz_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_frintz, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_scvtf_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_scvtf, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ucvtf_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ucvtf, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ctermeq(dc, Rn, Rm) instr_create_0dst_2src(dc, OP_ctermeq, Rn, Rm) |
| #define | INSTR_CREATE_ctermne(dc, Rn, Rm) instr_create_0dst_2src(dc, OP_ctermne, Rn, Rm) |
| #define | INSTR_CREATE_pnext_sve(dc, Pdn, Pv) INSTR_PRED(instr_create_1dst_2src(dc, OP_pnext, Pdn, Pv, Pdn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fabd_sve(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fabd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fabs_sve(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_fabs, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fdiv_sve(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fdiv, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fdivr_sve(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fdivr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmad_sve(dc, Zdn, Pg, Zm, Za) INSTR_PRED(instr_create_1dst_4src(dc, OP_fmad, Zdn, Zdn, Pg, Zm, Za), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmulx_sve(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fmulx, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fneg_sve(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_fneg, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fnmad_sve(dc, Zdn, Pg, Zm, Za) INSTR_PRED(instr_create_1dst_4src(dc, OP_fnmad, Zdn, Zdn, Pg, Zm, Za), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fnmla_sve(dc, Zda, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_4src(dc, OP_fnmla, Zda, Zda, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fnmls_sve(dc, Zda, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_4src(dc, OP_fnmls, Zda, Zda, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fnmsb_sve_pred(dc, Zdn, Pg, Zm, Za) INSTR_PRED(instr_create_1dst_4src(dc, OP_fnmsb, Zdn, Zdn, Pg, Zm, Za), DR_PRED_MASKED) |
| #define | INSTR_CREATE_frecpe_sve(dc, Zd, Zn) instr_create_1dst_1src(dc, OP_frecpe, Zd, Zn) |
| #define | INSTR_CREATE_frecps_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_frecps, Zd, Zn, Zm) |
| #define | INSTR_CREATE_frecpx_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_frecpx, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_frsqrte_sve(dc, Zd, Zn) instr_create_1dst_1src(dc, OP_frsqrte, Zd, Zn) |
| #define | INSTR_CREATE_frsqrts_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_frsqrts, Zd, Zn, Zm) |
| #define | INSTR_CREATE_fscale_sve(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fscale, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fsqrt_sve(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_fsqrt, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fadd_sve(dc, Zdn, Pg, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fadd, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fadd_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fadd_sve_vector(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_fadd, Zd, Zn, Zm) |
| #define | INSTR_CREATE_fsub_sve(dc, Zdn, Pg, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fsub, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fsub_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fsub, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fsub_sve_vector(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_fsub, Zd, Zn, Zm) |
| #define | INSTR_CREATE_fsubr_sve(dc, Zdn, Pg, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fsubr, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fsubr_sve_vector(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fsubr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmax_sve(dc, Zdn, Pg, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fmax, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmax_sve_vector(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fmax, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmaxnm_sve(dc, Zdn, Pg, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fmaxnm, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmaxnm_sve_vector(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fmaxnm, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmin_sve(dc, Zdn, Pg, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fmin, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmin_sve_vector(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fmin, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fminnm_sve(dc, Zdn, Pg, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fminnm, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fminnm_sve_vector(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fminnm, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmla_sve_vector(dc, Zda, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_4src(dc, OP_fmla, Zda, Zda, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmla_sve_idx(dc, Zda, Zn, Zm, index) instr_create_1dst_4src(dc, OP_fmla, Zda, Zda, Zn, Zm, index) |
| #define | INSTR_CREATE_fmls_sve_vector(dc, Zda, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_4src(dc, OP_fmls, Zda, Zda, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmls_sve_idx(dc, Zda, Zn, Zm, index) instr_create_1dst_4src(dc, OP_fmls, Zda, Zda, Zn, Zm, index) |
| #define | INSTR_CREATE_fmsb_sve(dc, Zdn, Pg, Zm, Za) INSTR_PRED(instr_create_1dst_4src(dc, OP_fmsb, Zdn, Zdn, Pg, Zm, Za), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmul_sve(dc, Zdn, Pg, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fmul, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmul_sve_pred_vector(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fmul, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmul_sve_vector(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_fmul, Zd, Zn, Zm) |
| #define | INSTR_CREATE_fmul_sve_idx(dc, Zd, Zn, Zm, index) instr_create_1dst_3src(dc, OP_fmul, Zd, Zn, Zm, index) |
| #define | INSTR_CREATE_addpl(dc, Rd, Rn, simm) instr_create_1dst_2src(dc, OP_addpl, Rd, Rn, simm) |
| #define | INSTR_CREATE_addvl(dc, Rd, Rn, simm) instr_create_1dst_2src(dc, OP_addvl, Rd, Rn, simm) |
| #define | INSTR_CREATE_rdvl(dc, Rd, simm) instr_create_1dst_1src(dc, OP_rdvl, Rd, simm) |
| #define | INSTR_CREATE_ldff1b_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1b, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldff1d_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1d, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldff1h_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1h, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldff1sb_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1sb, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldff1sh_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1sh, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldff1sw_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1sw, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldff1w_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1w, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcadd_sve_pred(dc, Zdn, Pg, Zm, rot) |
| #define | INSTR_CREATE_fcmla_sve_vector(dc, Zda, Pg, Zn, Zm, rot) |
| #define | INSTR_CREATE_fcmla_sve_idx(dc, Zda, Zn, Zm, imm, rot) instr_create_1dst_5src(dc, OP_fcmla, Zda, Zda, Zn, Zm, imm, rot) |
| #define | INSTR_CREATE_ld1b_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1b, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1rob_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rob, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1rqb_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rqb, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1rqh_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rqh, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1rqw_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rqw, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1rqd_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rqd, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1sb_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1sb, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldnt1b_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1b, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_st1b_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_st1b, Rn, Zt, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_stnt1b_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_stnt1b, Rn, Zt, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_bfcvt_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_bfcvt, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_bfdot_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_bfdot, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_bfdot_sve_idx(dc, Zda, Zn, Zm, index) instr_create_1dst_4src(dc, OP_bfdot, Zda, Zda, Zn, Zm, index) |
| #define | INSTR_CREATE_bfmlalb_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_bfmlalb, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_bfmlalb_sve_idx(dc, Zda, Zn, Zm, index) instr_create_1dst_4src(dc, OP_bfmlalb, Zda, Zda, Zn, Zm, index) |
| #define | INSTR_CREATE_bfmlalt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_bfmlalt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_bfmlalt_sve_idx(dc, Zda, Zn, Zm, index) instr_create_1dst_4src(dc, OP_bfmlalt, Zda, Zda, Zn, Zm, index) |
| #define | INSTR_CREATE_bfmmla_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_bfmmla, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_smmla_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_smmla, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sudot_sve_idx(dc, Zda, Zn, Zm, index) instr_create_1dst_4src(dc, OP_sudot, Zda, Zda, Zn, Zm, index) |
| #define | INSTR_CREATE_ummla_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_ummla, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_usdot_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_usdot, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_usdot_sve_idx(dc, Zda, Zn, Zm, index) instr_create_1dst_4src(dc, OP_usdot, Zda, Zda, Zn, Zm, index) |
| #define | INSTR_CREATE_usmmla_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_usmmla, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_prfb_sve_pred(dc, prfop, Pg, Rn) INSTR_PRED(instr_create_0dst_3src(dc, OP_prfb, prfop, Pg, Rn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_prfd_sve_pred(dc, prfop, Pg, Rn) INSTR_PRED(instr_create_0dst_3src(dc, OP_prfd, prfop, Pg, Rn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_prfh_sve_pred(dc, prfop, Pg, Rn) INSTR_PRED(instr_create_0dst_3src(dc, OP_prfh, prfop, Pg, Rn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_prfw_sve_pred(dc, prfop, Pg, Rn) INSTR_PRED(instr_create_0dst_3src(dc, OP_prfw, prfop, Pg, Rn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_adr_sve(dc, Zd, Zn) instr_create_1dst_1src(dc, OP_adr, Zd, Zn) |
| #define | INSTR_CREATE_ld2b_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_ld3b_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_ld4b_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_st2b_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_st3b_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_st4b_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_ld1h_sve_pred(dc, Zt, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1h, Zt, Zn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1sh_sve_pred(dc, Zt, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1sh, Zt, Zn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1w_sve_pred(dc, Zt, Pg, Zn) |
| #define | INSTR_CREATE_ld1d_sve_pred(dc, Zt, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1d, Zt, Zn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld1sw_sve_pred(dc, Zt, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1sw, Zt, Zn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_st1h_sve_pred(dc, Zt, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_st1h, Zn, Zt, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_st1w_sve_pred(dc, Zt, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_st1w, Zn, Zt, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_st1d_sve_pred(dc, Zt, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_st1d, Zn, Zt, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ld2d_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_ld2h_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_ld2w_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_ld3d_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_ld3h_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_ld3w_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_ld4d_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_ld4h_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_ld4w_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_ldnt1d_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1d, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldnt1h_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1h, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldnt1w_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1w, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_st2d_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_st2h_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_st2w_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_st3d_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_st3h_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_st3w_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_st4d_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_st4h_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_st4w_sve_pred(dc, Zt, Pg, Rn) |
| #define | INSTR_CREATE_stnt1d_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_stnt1d, Rn, Zt, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_stnt1h_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_stnt1h, Rn, Zt, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_stnt1w_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_stnt1w, Rn, Zt, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldnf1b_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1b, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldnf1d_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1d, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldnf1h_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1h, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldnf1sb_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1sb, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldnf1sh_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1sh, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldnf1sw_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1sw, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldnf1w_sve_pred(dc, Zt, Pg, Rn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1w, Zt, Rn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldapur(dc, Rt, mem) instr_create_1dst_1src(dc, OP_ldapur, Rt, mem) |
| #define | INSTR_CREATE_ldapurb(dc, Rt, mem) instr_create_1dst_1src(dc, OP_ldapurb, Rt, mem) |
| #define | INSTR_CREATE_ldapursb(dc, Rt, mem) instr_create_1dst_1src(dc, OP_ldapursb, Rt, mem) |
| #define | INSTR_CREATE_ldapurh(dc, Rt, mem) instr_create_1dst_1src(dc, OP_ldapurh, Rt, mem) |
| #define | INSTR_CREATE_ldapursh(dc, Rt, mem) instr_create_1dst_1src(dc, OP_ldapursh, Rt, mem) |
| #define | INSTR_CREATE_ldapursw(dc, Rt, mem) instr_create_1dst_1src(dc, OP_ldapursw, Rt, mem) |
| #define | INSTR_CREATE_stlur(dc, Rt, mem) instr_create_1dst_1src(dc, OP_stlur, mem, Rt) |
| #define | INSTR_CREATE_stlurb(dc, Rt, mem) instr_create_1dst_1src(dc, OP_stlurb, mem, Rt) |
| #define | INSTR_CREATE_stlurh(dc, Rt, mem) instr_create_1dst_1src(dc, OP_stlurh, mem, Rt) |
| #define | INSTR_CREATE_cfinv(dc) instr_create_0dst_0src(dc, OP_cfinv) |
| #define | INSTR_CREATE_rmif(dc, Rn, shift, mask) instr_create_0dst_3src(dc, OP_rmif, Rn, shift, mask) |
| #define | INSTR_CREATE_setf16(dc, Rn) instr_create_0dst_1src(dc, OP_setf16, Rn) |
| #define | INSTR_CREATE_setf8(dc, Rn) instr_create_0dst_1src(dc, OP_setf8, Rn) |
| #define | INSTR_CREATE_autda(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_autda, Rd, Rd, Rn) |
| #define | INSTR_CREATE_autdb(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_autdb, Rd, Rd, Rn) |
| #define | INSTR_CREATE_autdza(dc, Rd) instr_create_1dst_1src(dc, OP_autdza, Rd, Rd) |
| #define | INSTR_CREATE_autdzb(dc, Rd) instr_create_1dst_1src(dc, OP_autdzb, Rd, Rd) |
| #define | INSTR_CREATE_autia(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_autia, Rd, Rd, Rn) |
| #define | INSTR_CREATE_autia1716(dc) |
| #define | INSTR_CREATE_autiasp(dc) |
| #define | INSTR_CREATE_autiaz(dc) |
| #define | INSTR_CREATE_autib(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_autib, Rd, Rd, Rn) |
| #define | INSTR_CREATE_autib1716(dc) |
| #define | INSTR_CREATE_autibsp(dc) |
| #define | INSTR_CREATE_autibz(dc) |
| #define | INSTR_CREATE_autiza(dc, Rd) instr_create_1dst_1src(dc, OP_autiza, Rd, Rd) |
| #define | INSTR_CREATE_autizb(dc, Rd) instr_create_1dst_1src(dc, OP_autizb, Rd, Rd) |
| #define | INSTR_CREATE_blraa(dc, Rn, Rm) instr_create_1dst_2src(dc, OP_blraa, opnd_create_reg(DR_REG_X30), Rn, Rm) |
| #define | INSTR_CREATE_blraaz(dc, Rn) instr_create_1dst_1src(dc, OP_blraaz, opnd_create_reg(DR_REG_X30), Rn) |
| #define | INSTR_CREATE_blrab(dc, Rn, Rm) instr_create_1dst_2src(dc, OP_blrab, opnd_create_reg(DR_REG_X30), Rn, Rm) |
| #define | INSTR_CREATE_blrabz(dc, Rn) instr_create_1dst_1src(dc, OP_blrabz, opnd_create_reg(DR_REG_X30), Rn) |
| #define | INSTR_CREATE_braa(dc, Rn, Rm) instr_create_0dst_2src(dc, OP_braa, Rn, Rm) |
| #define | INSTR_CREATE_braaz(dc, Rn) instr_create_0dst_1src(dc, OP_braaz, Rn) |
| #define | INSTR_CREATE_brab(dc, Rn, Rm) instr_create_0dst_2src(dc, OP_brab, Rn, Rm) |
| #define | INSTR_CREATE_brabz(dc, Rn) instr_create_0dst_1src(dc, OP_brabz, Rn) |
| #define | INSTR_CREATE_pacda(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_pacda, Rd, Rd, Rn) |
| #define | INSTR_CREATE_pacdb(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_pacdb, Rd, Rd, Rn) |
| #define | INSTR_CREATE_pacdza(dc, Rd) instr_create_1dst_1src(dc, OP_pacdza, Rd, Rd) |
| #define | INSTR_CREATE_pacdzb(dc, Rd) instr_create_1dst_1src(dc, OP_pacdzb, Rd, Rd) |
| #define | INSTR_CREATE_pacga(dc, Rd, Rn, Rm) instr_create_1dst_2src(dc, OP_pacga, Rd, Rn, Rm) |
| #define | INSTR_CREATE_pacia(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_pacia, Rd, Rd, Rn) |
| #define | INSTR_CREATE_pacia1716(dc) |
| #define | INSTR_CREATE_paciasp(dc) |
| #define | INSTR_CREATE_paciaz(dc) |
| #define | INSTR_CREATE_pacib(dc, Rd, Rn) instr_create_1dst_2src(dc, OP_pacib, Rd, Rd, Rn) |
| #define | INSTR_CREATE_pacib1716(dc) |
| #define | INSTR_CREATE_pacibsp(dc) |
| #define | INSTR_CREATE_pacibz(dc) |
| #define | INSTR_CREATE_paciza(dc, Rd) instr_create_1dst_1src(dc, OP_paciza, Rd, Rd) |
| #define | INSTR_CREATE_pacizb(dc, Rd) instr_create_1dst_1src(dc, OP_pacizb, Rd, Rd) |
| #define | INSTR_CREATE_ldraa(dc, Rt, Rn) instr_create_1dst_1src(dc, OP_ldraa, Rt, Rn) |
| #define | INSTR_CREATE_ldraa_imm(dc, Rt, Xn, Rn, simm) instr_create_2dst_3src(dc, OP_ldraa, Rt, Xn, Rn, Xn, simm) |
| #define | INSTR_CREATE_ldrab(dc, Rt, Rn) instr_create_1dst_1src(dc, OP_ldrab, Rt, Rn) |
| #define | INSTR_CREATE_ldrab_imm(dc, Rt, Xn, Rn, simm) instr_create_2dst_3src(dc, OP_ldrab, Rt, Xn, Rn, Xn, simm) |
| #define | INSTR_CREATE_xpacd(dc, Rd) instr_create_1dst_1src(dc, OP_xpacd, Rd, Rd) |
| #define | INSTR_CREATE_xpaci(dc, Rd) instr_create_1dst_1src(dc, OP_xpaci, Rd, Rd) |
| #define | INSTR_CREATE_xpaclri(dc) |
| #define | INSTR_CREATE_eretaa(dc) |
| #define | INSTR_CREATE_eretab(dc) |
| #define | INSTR_CREATE_retaa(dc) |
| #define | INSTR_CREATE_retab(dc) |
| #define | INSTR_CREATE_fjcvtzs(dc, Rd, Rn) instr_create_1dst_1src(dc, OP_fjcvtzs, Rd, Rn) |
| #define | INSTR_CREATE_dc_cvap(dc, Rn) |
| #define | INSTR_CREATE_dc_cvadp(dc, Rn) |
| #define | INSTR_CREATE_sdot_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_sdot, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sdot_sve_idx(dc, Zda, Zn, Zm, index) instr_create_1dst_4src(dc, OP_sdot, Zda, Zda, Zn, Zm, index) |
| #define | INSTR_CREATE_udot_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_udot, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_udot_sve_idx(dc, Zda, Zn, Zm, index) instr_create_1dst_4src(dc, OP_udot, Zda, Zda, Zn, Zm, index) |
| #define | INSTR_CREATE_bfcvtnt_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_3src(dc, OP_bfcvtnt, Zd, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_aesd_sve(dc, Zdn, Zm) instr_create_1dst_2src(dc, OP_aesd, Zdn, Zdn, Zm) |
| #define | INSTR_CREATE_aese_sve(dc, Zdn, Zm) instr_create_1dst_2src(dc, OP_aese, Zdn, Zdn, Zm) |
| #define | INSTR_CREATE_bcax_sve(dc, Zdn, Zm, Zk) instr_create_1dst_3src(dc, OP_bcax, Zdn, Zdn, Zm, Zk) |
| #define | INSTR_CREATE_bsl1n_sve(dc, Zdn, Zm, Zk) instr_create_1dst_3src(dc, OP_bsl1n, Zdn, Zdn, Zm, Zk) |
| #define | INSTR_CREATE_bsl2n_sve(dc, Zdn, Zm, Zk) instr_create_1dst_3src(dc, OP_bsl2n, Zdn, Zdn, Zm, Zk) |
| #define | INSTR_CREATE_bsl_sve(dc, Zdn, Zm, Zk) instr_create_1dst_3src(dc, OP_bsl, Zdn, Zdn, Zm, Zk) |
| #define | INSTR_CREATE_eor3_sve(dc, Zdn, Zm, Zk) instr_create_1dst_3src(dc, OP_eor3, Zdn, Zdn, Zm, Zk) |
| #define | INSTR_CREATE_fmlalb_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_fmlalb, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_fmlalt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_fmlalt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_fmlslb_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_fmlslb, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_fmlslt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_fmlslt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_histseg_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_histseg, Zd, Zn, Zm) |
| #define | INSTR_CREATE_nbsl_sve(dc, Zdn, Zm, Zk) instr_create_1dst_3src(dc, OP_nbsl, Zdn, Zdn, Zm, Zk) |
| #define | INSTR_CREATE_pmul_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_pmul, Zd, Zn, Zm) |
| #define | INSTR_CREATE_rax1_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_rax1, Zd, Zn, Zm) |
| #define | INSTR_CREATE_sm4e_sve(dc, Zdn, Zm) instr_create_1dst_2src(dc, OP_sm4e, Zdn, Zdn, Zm) |
| #define | INSTR_CREATE_sm4ekey_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_sm4ekey, Zd, Zn, Zm) |
| #define | INSTR_CREATE_adclb_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_adclb, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_adclt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_adclt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_bdep_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_bdep, Zd, Zn, Zm) |
| #define | INSTR_CREATE_bext_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_bext, Zd, Zn, Zm) |
| #define | INSTR_CREATE_bgrp_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_bgrp, Zd, Zn, Zm) |
| #define | INSTR_CREATE_eorbt_sve(dc, Zd, Zn, Zm) instr_create_1dst_3src(dc, OP_eorbt, Zd, Zd, Zn, Zm) |
| #define | INSTR_CREATE_eortb_sve(dc, Zd, Zn, Zm) instr_create_1dst_3src(dc, OP_eortb, Zd, Zd, Zn, Zm) |
| #define | INSTR_CREATE_saba_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_saba, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sbclb_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_sbclb, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sbclt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_sbclt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sqdmulh_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_sqdmulh, Zd, Zn, Zm) |
| #define | INSTR_CREATE_sqrdmlah_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_sqrdmlah, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sqrdmlsh_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_sqrdmlsh, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sqrdmulh_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_sqrdmulh, Zd, Zn, Zm) |
| #define | INSTR_CREATE_tbx_sve(dc, Zd, Zn, Zm) instr_create_1dst_3src(dc, OP_tbx, Zd, Zd, Zn, Zm) |
| #define | INSTR_CREATE_uaba_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_uaba, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_addhnb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_addhnb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_addhnt_sve(dc, Zd, Zn, Zm) instr_create_1dst_3src(dc, OP_addhnt, Zd, Zd, Zn, Zm) |
| #define | INSTR_CREATE_pmullb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_pmullb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_pmullt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_pmullt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_raddhnb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_raddhnb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_raddhnt_sve(dc, Zd, Zn, Zm) instr_create_1dst_3src(dc, OP_raddhnt, Zd, Zd, Zn, Zm) |
| #define | INSTR_CREATE_rsubhnb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_rsubhnb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_rsubhnt_sve(dc, Zd, Zn, Zm) instr_create_1dst_3src(dc, OP_rsubhnt, Zd, Zd, Zn, Zm) |
| #define | INSTR_CREATE_sabalb_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_sabalb, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sabalt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_sabalt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sabdlb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_sabdlb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_sabdlt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_sabdlt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_saddlb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_saddlb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_saddlbt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_saddlbt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_saddlt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_saddlt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_saddwb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_saddwb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_saddwt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_saddwt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_smlalb_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_smlalb, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_smlalt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_smlalt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_smlslb_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_smlslb, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_smlslt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_smlslt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_smullb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_smullb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_smullt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_smullt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_sqdmlalb_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_sqdmlalb, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sqdmlalbt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_sqdmlalbt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sqdmlalt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_sqdmlalt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sqdmlslb_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_sqdmlslb, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sqdmlslbt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_sqdmlslbt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sqdmlslt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_sqdmlslt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_sqdmullb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_sqdmullb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_sqdmullt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_sqdmullt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_ssublb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_ssublb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_ssublbt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_ssublbt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_ssublt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_ssublt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_ssubltb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_ssubltb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_ssubwb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_ssubwb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_ssubwt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_ssubwt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_subhnb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_subhnb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_subhnt_sve(dc, Zd, Zn, Zm) instr_create_1dst_3src(dc, OP_subhnt, Zd, Zd, Zn, Zm) |
| #define | INSTR_CREATE_uabalb_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_uabalb, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_uabalt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_uabalt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_uabdlb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_uabdlb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_uabdlt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_uabdlt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_uaddlb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_uaddlb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_uaddlt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_uaddlt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_uaddwb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_uaddwb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_uaddwt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_uaddwt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_umlalb_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_umlalb, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_umlalt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_umlalt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_umlslb_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_umlslb, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_umlslt_sve(dc, Zda, Zn, Zm) instr_create_1dst_3src(dc, OP_umlslt, Zda, Zda, Zn, Zm) |
| #define | INSTR_CREATE_umullb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_umullb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_umullt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_umullt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_usublb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_usublb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_usublt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_usublt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_usubwb_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_usubwb, Zd, Zn, Zm) |
| #define | INSTR_CREATE_usubwt_sve(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_usubwt, Zd, Zn, Zm) |
| #define | INSTR_CREATE_aesimc_sve(dc, Zdn) instr_create_1dst_1src(dc, OP_aesimc, Zdn, Zdn) |
| #define | INSTR_CREATE_aesmc_sve(dc, Zdn) instr_create_1dst_1src(dc, OP_aesmc, Zdn, Zdn) |
| #define | INSTR_CREATE_sqxtnb_sve(dc, Zd, Zn) instr_create_1dst_1src(dc, OP_sqxtnb, Zd, Zn) |
| #define | INSTR_CREATE_sqxtnt_sve(dc, Zd, Zn) instr_create_1dst_2src(dc, OP_sqxtnt, Zd, Zd, Zn) |
| #define | INSTR_CREATE_sqxtunb_sve(dc, Zd, Zn) instr_create_1dst_1src(dc, OP_sqxtunb, Zd, Zn) |
| #define | INSTR_CREATE_sqxtunt_sve(dc, Zd, Zn) instr_create_1dst_2src(dc, OP_sqxtunt, Zd, Zd, Zn) |
| #define | INSTR_CREATE_uqxtnb_sve(dc, Zd, Zn) instr_create_1dst_1src(dc, OP_uqxtnb, Zd, Zn) |
| #define | INSTR_CREATE_uqxtnt_sve(dc, Zd, Zn) instr_create_1dst_2src(dc, OP_uqxtnt, Zd, Zd, Zn) |
| #define | INSTR_CREATE_fmlalt_sve_idx(dc, Zda, Zn, Zm, i3) instr_create_1dst_4src(dc, OP_fmlalt, Zda, Zda, Zn, Zm, i3) |
| #define | INSTR_CREATE_fmlslb_sve_idx(dc, Zda, Zn, Zm, i3) instr_create_1dst_4src(dc, OP_fmlslb, Zda, Zda, Zn, Zm, i3) |
| #define | INSTR_CREATE_fmlslt_sve_idx(dc, Zda, Zn, Zm, i3) instr_create_1dst_4src(dc, OP_fmlslt, Zda, Zda, Zn, Zm, i3) |
| #define | INSTR_CREATE_smlalb_sve_idx_vector(dc, Zda, Zn, Zm, i2) instr_create_1dst_4src(dc, OP_smlalb, Zda, Zda, Zn, Zm, i2) |
| #define | INSTR_CREATE_smlalt_sve_idx_vector(dc, Zda, Zn, Zm, i2) instr_create_1dst_4src(dc, OP_smlalt, Zda, Zda, Zn, Zm, i2) |
| #define | INSTR_CREATE_smlslb_sve_idx_vector(dc, Zda, Zn, Zm, i2) instr_create_1dst_4src(dc, OP_smlslb, Zda, Zda, Zn, Zm, i2) |
| #define | INSTR_CREATE_smlslt_sve_idx_vector(dc, Zda, Zn, Zm, i2) instr_create_1dst_4src(dc, OP_smlslt, Zda, Zda, Zn, Zm, i2) |
| #define | INSTR_CREATE_smullb_sve_idx_vector(dc, Zd, Zn, Zm, i2) instr_create_1dst_3src(dc, OP_smullb, Zd, Zn, Zm, i2) |
| #define | INSTR_CREATE_smullt_sve_idx_vector(dc, Zd, Zn, Zm, i2) instr_create_1dst_3src(dc, OP_smullt, Zd, Zn, Zm, i2) |
| #define | INSTR_CREATE_sqdmlalb_sve_idx_vector(dc, Zda, Zn, Zm, i2) instr_create_1dst_4src(dc, OP_sqdmlalb, Zda, Zda, Zn, Zm, i2) |
| #define | INSTR_CREATE_sqdmlalt_sve_idx_vector(dc, Zda, Zn, Zm, i2) instr_create_1dst_4src(dc, OP_sqdmlalt, Zda, Zda, Zn, Zm, i2) |
| #define | INSTR_CREATE_sqdmlslb_sve_idx_vector(dc, Zda, Zn, Zm, i2) instr_create_1dst_4src(dc, OP_sqdmlslb, Zda, Zda, Zn, Zm, i2) |
| #define | INSTR_CREATE_sqdmlslt_sve_idx_vector(dc, Zda, Zn, Zm, i2) instr_create_1dst_4src(dc, OP_sqdmlslt, Zda, Zda, Zn, Zm, i2) |
| #define | INSTR_CREATE_sqdmulh_sve_idx(dc, Zd, Zn, Zm, i1) instr_create_1dst_3src(dc, OP_sqdmulh, Zd, Zn, Zm, i1) |
| #define | INSTR_CREATE_sqdmullb_sve_idx_vector(dc, Zd, Zn, Zm, i2) instr_create_1dst_3src(dc, OP_sqdmullb, Zd, Zn, Zm, i2) |
| #define | INSTR_CREATE_sqdmullt_sve_idx_vector(dc, Zd, Zn, Zm, i2) instr_create_1dst_3src(dc, OP_sqdmullt, Zd, Zn, Zm, i2) |
| #define | INSTR_CREATE_sqrdmlah_sve_idx(dc, Zda, Zn, Zm, i1) instr_create_1dst_4src(dc, OP_sqrdmlah, Zda, Zda, Zn, Zm, i1) |
| #define | INSTR_CREATE_sqrdmlsh_sve_idx(dc, Zda, Zn, Zm, i1) instr_create_1dst_4src(dc, OP_sqrdmlsh, Zda, Zda, Zn, Zm, i1) |
| #define | INSTR_CREATE_sqrdmulh_sve_idx(dc, Zd, Zn, Zm, i1) instr_create_1dst_3src(dc, OP_sqrdmulh, Zd, Zn, Zm, i1) |
| #define | INSTR_CREATE_umlalb_sve_idx_vector(dc, Zda, Zn, Zm, i2) instr_create_1dst_4src(dc, OP_umlalb, Zda, Zda, Zn, Zm, i2) |
| #define | INSTR_CREATE_umlalt_sve_idx_vector(dc, Zda, Zn, Zm, i2) instr_create_1dst_4src(dc, OP_umlalt, Zda, Zda, Zn, Zm, i2) |
| #define | INSTR_CREATE_umlslb_sve_idx_vector(dc, Zda, Zn, Zm, i2) instr_create_1dst_4src(dc, OP_umlslb, Zda, Zda, Zn, Zm, i2) |
| #define | INSTR_CREATE_umlslt_sve_idx_vector(dc, Zda, Zn, Zm, i2) instr_create_1dst_4src(dc, OP_umlslt, Zda, Zda, Zn, Zm, i2) |
| #define | INSTR_CREATE_umullb_sve_idx_vector(dc, Zd, Zn, Zm, i2) instr_create_1dst_3src(dc, OP_umullb, Zd, Zn, Zm, i2) |
| #define | INSTR_CREATE_umullt_sve_idx_vector(dc, Zd, Zn, Zm, i2) instr_create_1dst_3src(dc, OP_umullt, Zd, Zn, Zm, i2) |
| #define | INSTR_CREATE_addp_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_addp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_faddp_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_faddp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmaxnmp_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fmaxnmp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fmaxp_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fmaxp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fminnmp_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fminnmp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fminp_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_fminp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_histcnt_sve_pred(dc, Zd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_histcnt, Zd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_shadd_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_shadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_shsub_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_shsub, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_shsubr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_shsubr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_smaxp_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_smaxp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sminp_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_sminp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sqrshl_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_sqrshl, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sqrshlr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_sqrshlr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sqshl_sve_pred(dc, Zdn, Pg, Zm_imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_sqshl, Zdn, Pg, Zdn, Zm_imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sqshlr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_sqshlr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sqsubr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_sqsubr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_srhadd_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_srhadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_srshl_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_srshl, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_srshlr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_srshlr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_suqadd_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_suqadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uhadd_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_uhadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uhsub_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_uhsub, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uhsubr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_uhsubr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_umaxp_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_umaxp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uminp_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_uminp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uqrshl_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_uqrshl, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uqrshlr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_uqrshlr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uqshl_sve_pred(dc, Zdn, Pg, Zm_imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_uqshl, Zdn, Pg, Zdn, Zm_imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uqshlr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_uqshlr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uqsubr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_uqsubr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_urhadd_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_urhadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_urshl_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_urshl, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_urshlr_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_urshlr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_usqadd_sve_pred(dc, Zdn, Pg, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_usqadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcvtlt_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvtlt, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcvtnt_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_3src(dc, OP_fcvtnt, Zd, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcvtx_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvtx, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_fcvtxnt_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_3src(dc, OP_fcvtxnt, Zd, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_flogb_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_flogb, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sadalp_sve_pred(dc, Zda, Pg, Zn) INSTR_PRED(instr_create_1dst_3src(dc, OP_sadalp, Zda, Zda, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sqabs_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_sqabs, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sqneg_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_sqneg, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uadalp_sve_pred(dc, Zda, Pg, Zn) INSTR_PRED(instr_create_1dst_3src(dc, OP_uadalp, Zda, Zda, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_cadd_sve(dc, Zdn, Zm, rot) instr_create_1dst_3src(dc, OP_cadd, Zdn, Zdn, Zm, rot) |
| #define | INSTR_CREATE_cdot_sve(dc, Zda, Zn, Zm, rot) instr_create_1dst_4src(dc, OP_cdot, Zda, Zda, Zn, Zm, rot) |
| #define | INSTR_CREATE_cmla_sve(dc, Zda, Zn, Zm, rot) instr_create_1dst_4src(dc, OP_cmla, Zda, Zda, Zn, Zm, rot) |
| #define | INSTR_CREATE_rshrnb_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_rshrnb, Zd, Zn, imm) |
| #define | INSTR_CREATE_rshrnt_sve(dc, Zd, Zn, imm) instr_create_1dst_3src(dc, OP_rshrnt, Zd, Zd, Zn, imm) |
| #define | INSTR_CREATE_shrnb_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_shrnb, Zd, Zn, imm) |
| #define | INSTR_CREATE_shrnt_sve(dc, Zd, Zn, imm) instr_create_1dst_3src(dc, OP_shrnt, Zd, Zd, Zn, imm) |
| #define | INSTR_CREATE_sli_sve(dc, Zd, Zn, imm) instr_create_1dst_3src(dc, OP_sli, Zd, Zd, Zn, imm) |
| #define | INSTR_CREATE_sqcadd_sve(dc, Zdn, Zm, rot) instr_create_1dst_3src(dc, OP_sqcadd, Zdn, Zdn, Zm, rot) |
| #define | INSTR_CREATE_sqrdcmlah_sve(dc, Zda, Zn, Zm, rot) instr_create_1dst_4src(dc, OP_sqrdcmlah, Zda, Zda, Zn, Zm, rot) |
| #define | INSTR_CREATE_sqrshrnb_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_sqrshrnb, Zd, Zn, imm) |
| #define | INSTR_CREATE_sqrshrnt_sve(dc, Zd, Zn, imm) instr_create_1dst_3src(dc, OP_sqrshrnt, Zd, Zd, Zn, imm) |
| #define | INSTR_CREATE_sqrshrunb_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_sqrshrunb, Zd, Zn, imm) |
| #define | INSTR_CREATE_sqrshrunt_sve(dc, Zd, Zn, imm) instr_create_1dst_3src(dc, OP_sqrshrunt, Zd, Zd, Zn, imm) |
| #define | INSTR_CREATE_sqshlu_sve_pred(dc, Zdn, Pg, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_sqshlu, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_sqshrnb_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_sqshrnb, Zd, Zn, imm) |
| #define | INSTR_CREATE_sqshrnt_sve(dc, Zd, Zn, imm) instr_create_1dst_3src(dc, OP_sqshrnt, Zd, Zd, Zn, imm) |
| #define | INSTR_CREATE_sqshrunb_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_sqshrunb, Zd, Zn, imm) |
| #define | INSTR_CREATE_sqshrunt_sve(dc, Zd, Zn, imm) instr_create_1dst_3src(dc, OP_sqshrunt, Zd, Zd, Zn, imm) |
| #define | INSTR_CREATE_sri_sve(dc, Zd, Zn, imm) instr_create_1dst_3src(dc, OP_sri, Zd, Zd, Zn, imm) |
| #define | INSTR_CREATE_srshr_sve_pred(dc, Zdn, Pg, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_srshr, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_srsra_sve(dc, Zda, Zn, imm) instr_create_1dst_3src(dc, OP_srsra, Zda, Zda, Zn, imm) |
| #define | INSTR_CREATE_sshllb_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_sshllb, Zd, Zn, imm) |
| #define | INSTR_CREATE_sshllt_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_sshllt, Zd, Zn, imm) |
| #define | INSTR_CREATE_ssra_sve(dc, Zda, Zn, imm) instr_create_1dst_3src(dc, OP_ssra, Zda, Zda, Zn, imm) |
| #define | INSTR_CREATE_uqrshrnb_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_uqrshrnb, Zd, Zn, imm) |
| #define | INSTR_CREATE_uqrshrnt_sve(dc, Zd, Zn, imm) instr_create_1dst_3src(dc, OP_uqrshrnt, Zd, Zd, Zn, imm) |
| #define | INSTR_CREATE_uqshrnb_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_uqshrnb, Zd, Zn, imm) |
| #define | INSTR_CREATE_uqshrnt_sve(dc, Zd, Zn, imm) instr_create_1dst_3src(dc, OP_uqshrnt, Zd, Zd, Zn, imm) |
| #define | INSTR_CREATE_urshr_sve_pred(dc, Zdn, Pg, imm) INSTR_PRED(instr_create_1dst_3src(dc, OP_urshr, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ursra_sve(dc, Zda, Zn, imm) instr_create_1dst_3src(dc, OP_ursra, Zda, Zda, Zn, imm) |
| #define | INSTR_CREATE_ushllb_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_ushllb, Zd, Zn, imm) |
| #define | INSTR_CREATE_ushllt_sve(dc, Zd, Zn, imm) instr_create_1dst_2src(dc, OP_ushllt, Zd, Zn, imm) |
| #define | INSTR_CREATE_usra_sve(dc, Zda, Zn, imm) instr_create_1dst_3src(dc, OP_usra, Zda, Zda, Zn, imm) |
| #define | INSTR_CREATE_xar_sve(dc, Zdn, Zm, imm) instr_create_1dst_3src(dc, OP_xar, Zdn, Zdn, Zm, imm) |
| #define | INSTR_CREATE_ldnt1sb_sve_pred(dc, Zt, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1sb, Zt, Zn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldnt1sh_sve_pred(dc, Zt, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1sh, Zt, Zn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ldnt1sw_sve_pred(dc, Zt, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1sw, Zt, Zn, Pg), DR_PRED_MASKED) |
| #define | INSTR_CREATE_uzp1_sve_vector(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_uzp1, Zd, Zn, Zm) |
| #define | INSTR_CREATE_cmla_sve_idx_imm_vector(dc, Zda, Zn, Zm, i1, rot) instr_create_1dst_5src(dc, OP_cmla, Zda, Zda, Zn, Zm, i1, rot) |
| #define | INSTR_CREATE_sqrdcmlah_sve_idx_imm_vector(dc, Zda, Zn, Zm, i1, rot) instr_create_1dst_5src(dc, OP_sqrdcmlah, Zda, Zda, Zn, Zm, i1, rot) |
| #define | INSTR_CREATE_match_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_match, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_nmatch_sve_pred(dc, Pd, Pg, Zn, Zm) INSTR_PRED(instr_create_1dst_3src(dc, OP_nmatch, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
| #define | INSTR_CREATE_urecpe_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_urecpe, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_ursqrte_sve_pred(dc, Zd, Pg, Zn) INSTR_PRED(instr_create_1dst_2src(dc, OP_ursqrte, Zd, Pg, Zn), DR_PRED_MASKED) |
| #define | INSTR_CREATE_whilege_sve(dc, Pd, Rn, Rm) instr_create_1dst_2src(dc, OP_whilege, Pd, Rn, Rm) |
| #define | INSTR_CREATE_whilegt_sve(dc, Pd, Rn, Rm) instr_create_1dst_2src(dc, OP_whilegt, Pd, Rn, Rm) |
| #define | INSTR_CREATE_whilehi_sve(dc, Pd, Rn, Rm) instr_create_1dst_2src(dc, OP_whilehi, Pd, Rn, Rm) |
| #define | INSTR_CREATE_whilehs_sve(dc, Pd, Rn, Rm) instr_create_1dst_2src(dc, OP_whilehs, Pd, Rn, Rm) |
| #define | INSTR_CREATE_whilerw_sve(dc, Pd, Rn, Rm) instr_create_1dst_2src(dc, OP_whilerw, Pd, Rn, Rm) |
| #define | INSTR_CREATE_whilewr_sve(dc, Pd, Rn, Rm) instr_create_1dst_2src(dc, OP_whilewr, Pd, Rn, Rm) |
| #define | INSTR_CREATE_ldg(dc, Rt, Rn) instr_create_1dst_2src(dc, OP_ldg, Rt, Rt, Rn) |
| #define | INSTR_CREATE_st2g_post(dc, Rn, Rt, simm) |
| #define | INSTR_CREATE_st2g_pre(dc, Rn, Rt) |
| #define | INSTR_CREATE_st2g_offset(dc, Rn, Rt) instr_create_1dst_1src(dc, OP_st2g, Rn, Rt) |
| #define | INSTR_CREATE_stg_post(dc, Rn, Rt, simm) |
| #define | INSTR_CREATE_stg_pre(dc, Rn, Rt) |
| #define | INSTR_CREATE_stg_offset(dc, Rn, Rt) instr_create_1dst_1src(dc, OP_stg, Rn, Rt) |
| #define | INSTR_CREATE_stz2g_post(dc, Rn, Rt, simm) |
| #define | INSTR_CREATE_stz2g_pre(dc, Rn, Rt) |
| #define | INSTR_CREATE_stz2g_offset(dc, Rn, Rt) instr_create_1dst_1src(dc, OP_stz2g, Rn, Rt) |
| #define | INSTR_CREATE_stzg_post(dc, Rn, Rt, simm) |
| #define | INSTR_CREATE_stzg_pre(dc, Rn, Rt) |
| #define | INSTR_CREATE_stzg_offset(dc, Rn, Rt) instr_create_1dst_1src(dc, OP_stzg, Rn, Rt) |
| #define | INSTR_CREATE_stgp_post(dc, Rn, Rt, Rt2, simm) |
| #define | INSTR_CREATE_stgp_pre(dc, Rn, Rt, Rt2) |
| #define | INSTR_CREATE_stgp_offset(dc, Rn, Rt, Rt2) instr_create_1dst_2src(dc, OP_stgp, Rn, Rt, Rt2) |
| #define | INSTR_CREATE_gmi(dc, Rd, Rn, Rm) instr_create_1dst_2src(dc, OP_gmi, Rd, Rn, Rm) |
| #define | INSTR_CREATE_irg(dc, Rd, Rn, Rm) instr_create_1dst_2src(dc, OP_irg, Rd, Rn, Rm) |
| #define | INSTR_CREATE_subp(dc, Rd, Rn, Rm) instr_create_1dst_2src(dc, OP_subp, Rd, Rn, Rm) |
| #define | INSTR_CREATE_subps(dc, Rd, Rn, Rm) instr_create_1dst_2src(dc, OP_subps, Rd, Rn, Rm) |
| #define | INSTR_CREATE_addg(dc, Rd, Rn, imm1, imm2) instr_create_1dst_3src(dc, OP_addg, Rd, Rn, imm1, imm2) |
| #define | INSTR_CREATE_subg(dc, Rd, Rn, imm1, imm2) instr_create_1dst_3src(dc, OP_subg, Rd, Rn, imm1, imm2) |
| #define | INSTR_CREATE_dc_gva(dc, Rn) |
| #define | INSTR_CREATE_dc_gzva(dc, Rn) |
| #define | INSTR_CREATE_mul_sve_vector(dc, Zd, Zn, Zm) instr_create_1dst_2src(dc, OP_mul, Zd, Zn, Zm) |
| #define | INSTR_CREATE_mul_sve_idx(dc, Zd, Zn, Zm, index) instr_create_1dst_3src(dc, OP_mul, Zd, Zn, Zm, index) |
| #define | INSTR_CREATE_frint32x(dc, Rd, Rn) instr_create_1dst_1src(dc, OP_frint32x, Rd, Rn) |
| #define | INSTR_CREATE_frint32x_vector(dc, Rd, Rn) instr_create_1dst_1src(dc, OP_frint32x, Rd, Rn) |
| #define | INSTR_CREATE_frint32z(dc, Rd, Rn) instr_create_1dst_1src(dc, OP_frint32z, Rd, Rn) |
| #define | INSTR_CREATE_frint32z_vector(dc, Rd, Rn) instr_create_1dst_1src(dc, OP_frint32z, Rd, Rn) |
| #define | INSTR_CREATE_frint64x(dc, Rd, Rn) instr_create_1dst_1src(dc, OP_frint64x, Rd, Rn) |
| #define | INSTR_CREATE_frint64x_vector(dc, Rd, Rn) instr_create_1dst_1src(dc, OP_frint64x, Rd, Rn) |
| #define | INSTR_CREATE_frint64z(dc, Rd, Rn) instr_create_1dst_1src(dc, OP_frint64z, Rd, Rn) |
| #define | INSTR_CREATE_frint64z_vector(dc, Rd, Rn) instr_create_1dst_1src(dc, OP_frint64z, Rd, Rn) |
| #define | INSTR_CREATE_stgm(dc, Rn, Rt) instr_create_1dst_1src(dc, OP_stgm, Rn, Rt) |
| #define | INSTR_CREATE_stzgm(dc, Rn, Rt) instr_create_1dst_1src(dc, OP_stzgm, Rn, Rt) |
| #define | INSTR_CREATE_ldgm(dc, Rt, Rn) instr_create_1dst_1src(dc, OP_ldgm, Rt, Rn) |
| #define | INSTR_CREATE_axflag(dc) instr_create_0dst_0src(dc, OP_axflag) |
| #define | INSTR_CREATE_xaflag(dc) instr_create_0dst_0src(dc, OP_xaflag) |
| #define | INSTR_CREATE_wfe(dc) instr_create_0dst_0src(dc, OP_wfe) |
| #define | INSTR_CREATE_wfi(dc) instr_create_0dst_0src(dc, OP_wfi) |
| #define | INSTR_CREATE_wfet(dc, Rt) instr_create_0dst_1src(dc, OP_wfet, Rt) |
| #define | INSTR_CREATE_wfit(dc, Rt) instr_create_0dst_1src(dc, OP_wfit, Rt) |
Platform-independent macros | |
| #define | XINST_CREATE_debug_instr(dc) INSTR_CREATE_brk((dc), OPND_CREATE_INT16(0)) |
| #define | XINST_CREATE_load(dc, r, m) |
| #define | XINST_CREATE_load_1byte_zext4(dc, r, m) INSTR_CREATE_ldrb(dc, r, m) |
| #define | XINST_CREATE_load_1byte(dc, r, m) INSTR_CREATE_ldrb(dc, r, m) |
| #define | XINST_CREATE_load_2bytes(dc, r, m) INSTR_CREATE_ldrh(dc, r, m) |
| #define | XINST_CREATE_store(dc, m, r) |
| #define | XINST_CREATE_store_1byte(dc, m, r) INSTR_CREATE_strb(dc, m, opnd_create_reg(reg_resize_to_opsz(opnd_get_reg(r), OPSZ_4))) |
| #define | XINST_CREATE_store_2bytes(dc, m, r) INSTR_CREATE_strh(dc, m, opnd_create_reg(reg_resize_to_opsz(opnd_get_reg(r), OPSZ_4))) |
| #define | XINST_CREATE_store_pair(dc, m, r1, r2) INSTR_CREATE_stp(dc, m, r1, r2) |
| #define | XINST_CREATE_load_pair(dc, r1, r2, m) INSTR_CREATE_ldp(dc, r1, r2, m) |
| #define | XINST_CREATE_move(dc, d, s) |
| #define | XINST_CREATE_load_simd(dc, r, m) INSTR_CREATE_ldr((dc), (r), (m)) |
| #define | XINST_CREATE_store_simd(dc, m, r) INSTR_CREATE_str((dc), (m), (r)) |
| #define | XINST_CREATE_jump_reg(dc, r) INSTR_CREATE_br((dc), (r)) |
| #define | XINST_CREATE_load_int(dc, r, i) |
| #define | XINST_CREATE_return(dc) INSTR_CREATE_ret(dc, opnd_create_reg(DR_REG_X30)) |
| #define | XINST_CREATE_jump(dc, t) INSTR_CREATE_b((dc), (t)) |
| #define | XINST_CREATE_jump_short(dc, t) INSTR_CREATE_b((dc), (t)) |
| #define | XINST_CREATE_call(dc, t) INSTR_CREATE_bl(dc, t) |
| #define | XINST_CREATE_jump_cond(dc, pred, t) (INSTR_PRED(INSTR_CREATE_bcond((dc), (t)), (pred))) |
| #define | XINST_CREATE_add(dc, d, s) INSTR_CREATE_add(dc, d, d, s) |
| #define | XINST_CREATE_add_2src(dc, d, s1, s2) INSTR_CREATE_add(dc, d, s1, s2) |
| #define | XINST_CREATE_add_sll(dc, d, s1, s2_toshift, shift_amount) |
| #define | XINST_CREATE_add_s(dc, d, s) INSTR_CREATE_adds(dc, d, d, s) |
| #define | XINST_CREATE_sub(dc, d, s) INSTR_CREATE_sub(dc, d, d, s) |
| #define | XINST_CREATE_sub_s(dc, d, s) INSTR_CREATE_subs(dc, d, d, s) |
| #define | XINST_CREATE_and_s(dc, d, s) INSTR_CREATE_ands(dc, d, d, s) |
| #define | XINST_CREATE_cmp(dc, s1, s2) INSTR_CREATE_cmp(dc, s1, s2) |
| #define | XINST_CREATE_interrupt(dc, i) INSTR_CREATE_svc(dc, (i)) |
| #define | XINST_CREATE_slr_s(dc, d, rm_or_imm) |
| #define | XINST_CREATE_nop(dc) INSTR_CREATE_nop(dc) |
| #define | XINST_CREATE_call_reg(dc, r) INSTR_CREATE_blr(dc, r) |
Detailed Description
AArch64-specific instruction creation convenience macros.
Macro Definition Documentation
◆ INSTR_CREATE_abs_sve_pred
| #define INSTR_CREATE_abs_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_abs, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates an ABS instruction.
This macro is used to encode the forms:
* ABS <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable)
◆ INSTR_CREATE_adclb_sve
| #define INSTR_CREATE_adclb_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_adclb, Zda, Zda, Zn, Zm) |
Creates an ADCLB instruction.
This macro is used to encode the forms:
* ADCLB <Zda>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_adclt_sve
| #define INSTR_CREATE_adclt_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_adclt, Zda, Zda, Zn, Zm) |
Creates an ADCLT instruction.
This macro is used to encode the forms:
* ADCLT <Zda>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_add_sve
| #define INSTR_CREATE_add_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_add, Zd, Zn, Zm) |
Creates a ADD instruction.
This macro is used to encode the forms:
* ADD <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The first destination vector register, Z (Scalable) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_add_sve_pred
| #define INSTR_CREATE_add_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_add, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a ADD instruction.
This macro is used to encode the forms:
* ADD <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and first destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_add_sve_shift
| #define INSTR_CREATE_add_sve_shift | ( | dc, | |
| Zdn, | |||
| imm, | |||
| shift | |||
| ) | instr_create_1dst_4src(dc, OP_add, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift) |
Creates a ADD instruction.
This macro is used to encode the forms:
* ADD <Zdn>.<Ts>, <Zdn>.<Ts>, #<imm>, <shift> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and first destination vector register, Z (Scalable) imm The immediate imm shift The immediate shiftOp for imm
◆ INSTR_CREATE_add_vector
| #define INSTR_CREATE_add_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_add, Rd, Rm, Rn, width) |
Creates a ADD vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_addg
| #define INSTR_CREATE_addg | ( | dc, | |
| Rd, | |||
| Rn, | |||
| imm1, | |||
| imm2 | |||
| ) | instr_create_1dst_3src(dc, OP_addg, Rd, Rn, imm1, imm2) |
Creates an ADDG instruction.
This macro is used to encode the forms:
ADDG <Xd|SP>, <Xn|SP>, #<imm1>, #<imm2>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register, X (Extended, 64 bits). Rn The first source register, X (Extended, 64 bits). imm1 The immediate unsigned imm (must be a multiple of 16). imm2 The immediate unsigned imm.
◆ INSTR_CREATE_addhn2_vector
| #define INSTR_CREATE_addhn2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_addhn2, Rd, Rm, Rn, width) |
Creates a ADDHN2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_addhn_vector
| #define INSTR_CREATE_addhn_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_addhn, Rd, Rm, Rn, width) |
Creates a ADDHN vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_addhnb_sve
| #define INSTR_CREATE_addhnb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_addhnb, Zd, Zn, Zm) |
Creates an ADDHNB instruction.
This macro is used to encode the forms:
ADDHNB <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.b, Z.h or Z.s. Zn The first source vector register. Can be Z.h, Z.s or Z.d. Zm The second source vector register. Can be Z.h, Z.s or Z.d.
◆ INSTR_CREATE_addhnt_sve
| #define INSTR_CREATE_addhnt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_addhnt, Zd, Zd, Zn, Zm) |
Creates an ADDHNT instruction.
This macro is used to encode the forms:
ADDHNT <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The source and destination vector register. Can be Z.b, Z.h or Z.s. Zn The second source vector register. Can be Z.h, Z.s or Z.d. Zm The third source vector register. Can be Z.h, Z.s or Z.d.
◆ INSTR_CREATE_addp_sve_pred
| #define INSTR_CREATE_addp_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_addp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an ADDP instruction.
This macro is used to encode the forms:
ADDP <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_addp_vector
| #define INSTR_CREATE_addp_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_addp, Rd, Rm, Rn, width) |
Creates a ADDP vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_addpl
| #define INSTR_CREATE_addpl | ( | dc, | |
| Rd, | |||
| Rn, | |||
| simm | |||
| ) | instr_create_1dst_2src(dc, OP_addpl, Rd, Rn, simm) |
Creates an ADDPL instruction.
This macro is used to encode the forms:
* ADDPL <Xd|SP>, <Xn|SP>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register, X (Extended, 64 bits). Rn The first source register, X (Extended, 64 bits). simm The signed immediate imm.
◆ INSTR_CREATE_addvl
| #define INSTR_CREATE_addvl | ( | dc, | |
| Rd, | |||
| Rn, | |||
| simm | |||
| ) | instr_create_1dst_2src(dc, OP_addvl, Rd, Rn, simm) |
Creates an ADDVL instruction.
This macro is used to encode the forms:
* ADDVL <Xd|SP>, <Xn|SP>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register, X (Extended, 64 bits). Rn The first source register, X (Extended, 64 bits). simm The signed immediate imm.
◆ INSTR_CREATE_adr_sve
| #define INSTR_CREATE_adr_sve | ( | dc, | |
| Zd, | |||
| Zn | |||
| ) | instr_create_1dst_1src(dc, OP_adr, Zd, Zn) |
Creates an ADR instruction.
This macro is used to encode the forms:
* ADR <Zd>.D, [<Zn>.D, <Zm>.D, SXTW <amount>] * ADR <Zd>.D, [<Zn>.D, <Zm>.D, UXTW <amount>] * ADR <Zd>.<Ts>, [<Zn>.<Ts>, <Zm>.<Ts>, <extend> <amount>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector base register with a register offset, constructed with one of: opnd_create_vector_base_disp_aarch64(Zn, Zm, OPSZ_8, DR_EXTEND_SXTW, 0, 0, 0, OPSZ_0, shift_amount) opnd_create_vector_base_disp_aarch64(Zn, Zm, OPSZ_8, DR_EXTEND_UXTW, 0, 0, 0, OPSZ_0, shift_amount) opnd_create_vector_base_disp_aarch64(Zn, Zm, elsz, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_0, shift_amount)
◆ INSTR_CREATE_aesd_sve
| #define INSTR_CREATE_aesd_sve | ( | dc, | |
| Zdn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_aesd, Zdn, Zdn, Zm) |
Creates an AESD instruction.
This macro is used to encode the forms:
* AESD <Zdn>.B, <Zdn>.B, <Zm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_aese_sve
| #define INSTR_CREATE_aese_sve | ( | dc, | |
| Zdn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_aese, Zdn, Zdn, Zm) |
Creates an AESE instruction.
This macro is used to encode the forms:
* AESE <Zdn>.B, <Zdn>.B, <Zm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_aesimc_sve
| #define INSTR_CREATE_aesimc_sve | ( | dc, | |
| Zdn | |||
| ) | instr_create_1dst_1src(dc, OP_aesimc, Zdn, Zdn) |
Creates an AESIMC instruction.
This macro is used to encode the forms:
AESIMC <Zdn>.B, <Zdn>.B
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z.b.
◆ INSTR_CREATE_aesmc_sve
| #define INSTR_CREATE_aesmc_sve | ( | dc, | |
| Zdn | |||
| ) | instr_create_1dst_1src(dc, OP_aesmc, Zdn, Zdn) |
Creates an AESMC instruction.
This macro is used to encode the forms:
AESMC <Zdn>.B, <Zdn>.B
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z.b.
◆ INSTR_CREATE_and
| #define INSTR_CREATE_and | ( | dc, | |
| rd, | |||
| rn, | |||
| rm_or_imm | |||
| ) |
Value:
(opnd_is_immed(rm_or_imm) \
? instr_create_1dst_2src((dc), OP_and, (rd), (rn), (rm_or_imm)) \
: INSTR_CREATE_and_shift(dc, rd, rn, rm_or_imm, OPND_CREATE_LSL(), \
OPND_CREATE_INT(0)))
disabled_until_i4106_is_fixed Creates an AND instruction with one output and two inputs.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. rd The output register. rn The first input register. rm_or_imm The second input register or immediate.
◆ INSTR_CREATE_and_sve
| #define INSTR_CREATE_and_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_and, Zd, Zn, Zm) |
Creates an AND instruction.
This macro is used to encode the forms:
* AND <Zd>.D, <Zn>.D, <Zm>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_and_sve_imm
| #define INSTR_CREATE_and_sve_imm | ( | dc, | |
| Zdn, | |||
| imm | |||
| ) | instr_create_1dst_2src(dc, OP_and, Zdn, Zdn, imm) |
Creates an AND instruction.
This macro is used to encode the forms:
* AND <Zdn>.<T>, <Zdn>.<T>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). imm The immediate logicalImm. The 13 bit immediate defining a 64, 32, 16 or 8 bit mask of 2, 4, 8, 16, 32 or 64 bit fields.
◆ INSTR_CREATE_and_sve_pred
| #define INSTR_CREATE_and_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_and, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an AND instruction.
This macro is used to encode the forms:
* AND <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_and_sve_pred_b
| #define INSTR_CREATE_and_sve_pred_b | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_and, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates an AND instruction.
This macro is used to encode the forms:
* AND <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_and_vector
| #define INSTR_CREATE_and_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_and, Rd, Rm, Rn) |
Creates a AND vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register.
◆ INSTR_CREATE_ands
| #define INSTR_CREATE_ands | ( | dc, | |
| rd, | |||
| rn, | |||
| rm_or_imm | |||
| ) |
Value:
(opnd_is_immed(rm_or_imm) \
? instr_create_1dst_2src((dc), OP_ands, (rd), (rn), (rm_or_imm)) \
: INSTR_CREATE_ands_shift(dc, rd, rn, rm_or_imm, OPND_CREATE_LSL(), \
OPND_CREATE_INT(0)))
disabled_until_i4106_is_fixed Creates an ANDS instruction with one output and two inputs.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. rd The output register. rn The first input register. rm_or_imm The second input register or immediate.
◆ INSTR_CREATE_ands_sve_pred
| #define INSTR_CREATE_ands_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_ands, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates an ANDS instruction.
This macro is used to encode the forms:
* ANDS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_andv_sve_pred
| #define INSTR_CREATE_andv_sve_pred | ( | dc, | |
| Vd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_andv, Vd, Pg, Zn), DR_PRED_MASKED) |
Creates an ANDV instruction.
This macro is used to encode the forms:
* ANDV <V><d>, <Pg>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vd The destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits), B (byte, 8 bits) or D (doubleword, 64 bits). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_asr_sve
| #define INSTR_CREATE_asr_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_2src(dc, OP_asr, Zd, Zn, imm) |
Creates an ASR instruction.
This macro is used to encode the forms:
* ASR <Zd>.<Ts>, <Zn>.<Ts>, #<const> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). imm The immediate imm, one indexed.
◆ INSTR_CREATE_asr_sve_pred
| #define INSTR_CREATE_asr_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_asr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an ASR instruction.
This macro is used to encode the forms:
* ASR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_asr_sve_pred_wide
| #define INSTR_CREATE_asr_sve_pred_wide | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_asr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an ASR instruction.
This macro is used to encode the forms:
* ASR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_asr_sve_wide
| #define INSTR_CREATE_asr_sve_wide | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_asr, Zd, Zn, Zm) |
Creates an ASR instruction.
This macro is used to encode the forms:
* ASR <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_asrd_sve_pred
| #define INSTR_CREATE_asrd_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| imm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_asrd, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
Creates an ASRD instruction.
This macro is used to encode the forms:
* ASRD <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, #<const> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). imm The immediate imm, one indexed.
◆ INSTR_CREATE_asrr_sve_pred
| #define INSTR_CREATE_asrr_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_asrr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an ASRR instruction.
This macro is used to encode the forms:
* ASRR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_autda
| #define INSTR_CREATE_autda | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_autda, Rd, Rd, Rn) |
Creates an AUTDA instruction.
This macro is used to encode the forms:
* AUTDA <Xd>, <Xn|SP> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination register, X (Extended, 64 bits). Rn The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_autdb
| #define INSTR_CREATE_autdb | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_autdb, Rd, Rd, Rn) |
Creates an AUTDB instruction.
This macro is used to encode the forms:
* AUTDB <Xd>, <Xn|SP> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination register, X (Extended, 64 bits). Rn The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_autdza
| #define INSTR_CREATE_autdza | ( | dc, | |
| Rd | |||
| ) | instr_create_1dst_1src(dc, OP_autdza, Rd, Rd) |
Creates an AUTDZA instruction.
This macro is used to encode the forms:
* AUTDZA <Xd> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination register, X (Extended, 64 bits).
◆ INSTR_CREATE_autdzb
| #define INSTR_CREATE_autdzb | ( | dc, | |
| Rd | |||
| ) | instr_create_1dst_1src(dc, OP_autdzb, Rd, Rd) |
Creates an AUTDZB instruction.
This macro is used to encode the forms:
* AUTDZB <Xd> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination register, X (Extended, 64 bits).
◆ INSTR_CREATE_autia
| #define INSTR_CREATE_autia | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_autia, Rd, Rd, Rn) |
Creates an AUTIA instruction.
This macro is used to encode the forms:
* AUTIA <Xd>, <Xn|SP> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination register, X (Extended, 64 bits). Rn The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_autia1716
| #define INSTR_CREATE_autia1716 | ( | dc | ) |
Value:
instr_create_1dst_2src(dc, OP_autia1716, opnd_create_reg(DR_REG_X17), \
opnd_create_reg(DR_REG_X17), opnd_create_reg(DR_REG_X16))
Creates an AUTIA1716 instruction.
This macro is used to encode the forms:
* AUTIA1716 *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_autiasp
| #define INSTR_CREATE_autiasp | ( | dc | ) |
Value:
instr_create_1dst_2src(dc, OP_autiasp, opnd_create_reg(DR_REG_X30), \
Creates an AUTIASP instruction.
This macro is used to encode the forms:
* AUTIASP *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_autiaz
| #define INSTR_CREATE_autiaz | ( | dc | ) |
Value:
instr_create_1dst_1src(dc, OP_autiaz, opnd_create_reg(DR_REG_X30), \
opnd_create_reg(DR_REG_X30))
Creates an AUTIAZ instruction.
This macro is used to encode the forms:
* AUTIAZ *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_autib
| #define INSTR_CREATE_autib | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_autib, Rd, Rd, Rn) |
Creates an AUTIB instruction.
This macro is used to encode the forms:
* AUTIB <Xd>, <Xn|SP> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination register, X (Extended, 64 bits). Rn The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_autib1716
| #define INSTR_CREATE_autib1716 | ( | dc | ) |
Value:
instr_create_1dst_2src(dc, OP_autib1716, opnd_create_reg(DR_REG_X17), \
opnd_create_reg(DR_REG_X17), opnd_create_reg(DR_REG_X16))
Creates an AUTIB1716 instruction.
This macro is used to encode the forms:
* AUTIB1716 *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_autibsp
| #define INSTR_CREATE_autibsp | ( | dc | ) |
Value:
instr_create_1dst_2src(dc, OP_autibsp, opnd_create_reg(DR_REG_X30), \
Creates an AUTIBSP instruction.
This macro is used to encode the forms:
* AUTIBSP *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_autibz
| #define INSTR_CREATE_autibz | ( | dc | ) |
Value:
instr_create_1dst_1src(dc, OP_autibz, opnd_create_reg(DR_REG_X30), \
opnd_create_reg(DR_REG_X30))
Creates an AUTIBZ instruction.
This macro is used to encode the forms:
* AUTIBZ *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_autiza
| #define INSTR_CREATE_autiza | ( | dc, | |
| Rd | |||
| ) | instr_create_1dst_1src(dc, OP_autiza, Rd, Rd) |
Creates an AUTIZA instruction.
This macro is used to encode the forms:
* AUTIZA <Xd> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination register, X (Extended, 64 bits).
◆ INSTR_CREATE_autizb
| #define INSTR_CREATE_autizb | ( | dc, | |
| Rd | |||
| ) | instr_create_1dst_1src(dc, OP_autizb, Rd, Rd) |
Creates an AUTIZB instruction.
This macro is used to encode the forms:
* AUTIZB <Xd> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination register, X (Extended, 64 bits).
◆ INSTR_CREATE_axflag
| #define INSTR_CREATE_axflag | ( | dc | ) | instr_create_0dst_0src(dc, OP_axflag) |
Creates an AXFLAG instruction.
This macro is used to encode the forms:
AXFLAG
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_bcax
| #define INSTR_CREATE_bcax | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Ra | |||
| ) | instr_create_1dst_4src(dc, OP_bcax, Rd, Rn, Rm, Ra, OPND_CREATE_BYTE()) |
Creates a BCAX instruction.
This macro is used to encode the forms:
* BCAX <Bd>.16B, <Bn>.16B, <Bm>.16B, <Ba>.16B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register, Q (quadword, 128 bits) Rn The second source vector register, Q (quadword, 128 bits) Rm The third source vector register, Q (quadword, 128 bits) Ra The fourth source vector register, Q (quadword, 128 bits)
◆ INSTR_CREATE_bcax_sve
| #define INSTR_CREATE_bcax_sve | ( | dc, | |
| Zdn, | |||
| Zm, | |||
| Zk | |||
| ) | instr_create_1dst_3src(dc, OP_bcax, Zdn, Zdn, Zm, Zk) |
Creates a BCAX instruction.
This macro is used to encode the forms:
* BCAX <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Zm The second source vector register, Z (Scalable). Zk The third source vector register, Z (Scalable).
◆ INSTR_CREATE_bcond
| #define INSTR_CREATE_bcond | ( | dc, | |
| pc | |||
| ) | instr_create_0dst_1src((dc), OP_bcond, (pc)) |
◆ INSTR_CREATE_bdep_sve
| #define INSTR_CREATE_bdep_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_bdep, Zd, Zn, Zm) |
Creates a BDEP instruction.
This macro is used to encode the forms:
* BDEP <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_bext_sve
| #define INSTR_CREATE_bext_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_bext, Zd, Zn, Zm) |
Creates a BEXT instruction.
This macro is used to encode the forms:
* BEXT <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_bfcvt
| #define INSTR_CREATE_bfcvt | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_bfcvt, Rd, Rn) |
Creates a BFCVT instruction.
This macro is used to encode the forms:
* BFCVT <Hd>, <Sn> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register, H (halfword, 16 bits). Rn The source register, S (singleword, 32 bits).
◆ INSTR_CREATE_bfcvt_sve_pred
| #define INSTR_CREATE_bfcvt_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_bfcvt, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a BFCVT instruction.
This macro is used to encode the forms:
* BFCVT <Zd>.H, <Pg>/M, <Zn>.S *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_bfcvtn2_vector
| #define INSTR_CREATE_bfcvtn2_vector | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_bfcvtn2, Rd, Rn, OPND_CREATE_SINGLE()) |
Creates a BFCVTN2 instruction.
This macro is used to encode the forms:
* BFCVTN2 <Vd>.8H, <Vn>.4S *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination vector register, Q (quadword, 128 bits). Rn The source vector register, Q (quadword, 128 bits).
◆ INSTR_CREATE_bfcvtn_vector
| #define INSTR_CREATE_bfcvtn_vector | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_bfcvtn, Rd, Rn, OPND_CREATE_SINGLE()) |
Creates a BFCVTN instruction.
This macro is used to encode the forms:
* BFCVTN <Vd>.4H, <Vn>.4S *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination vector register, D (doubleword, 64 bits). Rn The source vector register, Q (quadword, 128 bits).
◆ INSTR_CREATE_bfcvtnt_sve_pred
| #define INSTR_CREATE_bfcvtnt_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_bfcvtnt, Zd, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a BFCVTNT instruction.
This macro is used to encode the forms:
* BFCVTNT <Zd>.H, <Pg>/M, <Zn>.S *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The second source vector register, Z (Scalable).
◆ INSTR_CREATE_bfdot_sve
| #define INSTR_CREATE_bfdot_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_bfdot, Zda, Zda, Zn, Zm) |
Creates a BFDOT instruction.
This macro is used to encode the forms:
* BFDOT <Zda>.S, <Zn>.H, <Zm>.H *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_bfdot_sve_idx
| #define INSTR_CREATE_bfdot_sve_idx | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| index | |||
| ) | instr_create_1dst_4src(dc, OP_bfdot, Zda, Zda, Zn, Zm, index) |
Creates a BFDOT instruction.
This macro is used to encode the forms:
* BFDOT <Zda>.S, <Zn>.H, <Zm>.H[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable). index The immediate index
◆ INSTR_CREATE_bfdot_vector
| #define INSTR_CREATE_bfdot_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_4src(dc, OP_bfdot, Rd, Rd, Rn, Rm, OPND_CREATE_HALF()) |
Creates a BFDOT instruction.
This macro is used to encode the forms:
* BFDOT <Vd>.<Ts>, <Vn>.<Tb>, <Vm>.<Tb> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits). Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits). Rm The third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits).
◆ INSTR_CREATE_bfdot_vector_idx
| #define INSTR_CREATE_bfdot_vector_idx | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| index | |||
| ) | instr_create_1dst_5src(dc, OP_bfdot, Rd, Rd, Rn, Rm, index, OPND_CREATE_HALF()) |
Creates a BFDOT instruction.
This macro is used to encode the forms:
* BFDOT <Vd>.<Ts>, <Vn>.<Tb>, <Vm>.2H[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits). Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits). Rm The third source vector register, Q (quadword, 128 bits). index The immediate index for Rm, in the range 0-3.
◆ INSTR_CREATE_bfmlalb_sve
| #define INSTR_CREATE_bfmlalb_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_bfmlalb, Zda, Zda, Zn, Zm) |
Creates a BFMLALB instruction.
This macro is used to encode the forms:
* BFMLALB <Zda>.S, <Zn>.H, <Zm>.H *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_bfmlalb_sve_idx
| #define INSTR_CREATE_bfmlalb_sve_idx | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| index | |||
| ) | instr_create_1dst_4src(dc, OP_bfmlalb, Zda, Zda, Zn, Zm, index) |
Creates a BFMLALB instruction.
This macro is used to encode the forms:
* BFMLALB <Zda>.S, <Zn>.H, <Zm>.H[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable). index The immediate index
◆ INSTR_CREATE_bfmlalb_vector
| #define INSTR_CREATE_bfmlalb_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_4src(dc, OP_bfmlalb, Rd, Rd, Rn, Rm, OPND_CREATE_HALF()) |
Creates a BFMLALB instruction.
This macro is used to encode the forms:
* BFMLALB <Vd>.4S, <Vn>.8H, <Vm>.8H *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination vector register, Q (quadword, 128 bits). Rn The second source vector register, Q (quadword, 128 bits). Rm The third source vector register, Q (quadword, 128 bits).
◆ INSTR_CREATE_bfmlalb_vector_idx
| #define INSTR_CREATE_bfmlalb_vector_idx | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| index | |||
| ) | instr_create_1dst_5src(dc, OP_bfmlalb, Rd, Rd, Rn, Rm, index, OPND_CREATE_HALF()) |
Creates a BFMLALB instruction.
This macro is used to encode the forms:
* BFMLALB <Vd>.4S, <Vn>.8H, <Vm>.H[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination vector register, Q (quadword, 128 bits). Rn The second source vector register, Q (quadword, 128 bits). Rm The third source vector register, Q (quadword, 128 bits). index The immediate index for Rm, in the range 0-7.
◆ INSTR_CREATE_bfmlalt_sve
| #define INSTR_CREATE_bfmlalt_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_bfmlalt, Zda, Zda, Zn, Zm) |
Creates a BFMLALT instruction.
This macro is used to encode the forms:
* BFMLALT <Zda>.S, <Zn>.H, <Zm>.H *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_bfmlalt_sve_idx
| #define INSTR_CREATE_bfmlalt_sve_idx | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| index | |||
| ) | instr_create_1dst_4src(dc, OP_bfmlalt, Zda, Zda, Zn, Zm, index) |
Creates a BFMLALT instruction.
This macro is used to encode the forms:
* BFMLALT <Zda>.S, <Zn>.H, <Zm>.H[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable). index The immediate index
◆ INSTR_CREATE_bfmlalt_vector
| #define INSTR_CREATE_bfmlalt_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_4src(dc, OP_bfmlalt, Rd, Rd, Rn, Rm, OPND_CREATE_HALF()) |
Creates a BFMLALT instruction.
This macro is used to encode the forms:
* BFMLALT <Vd>.4S, <Vn>.8H, <Vm>.8H *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination vector register, Q (quadword, 128 bits). Rn The second source vector register, Q (quadword, 128 bits). Rm The third source vector register, Q (quadword, 128 bits).
◆ INSTR_CREATE_bfmlalt_vector_idx
| #define INSTR_CREATE_bfmlalt_vector_idx | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| index | |||
| ) | instr_create_1dst_5src(dc, OP_bfmlalt, Rd, Rd, Rn, Rm, index, OPND_CREATE_HALF()) |
Creates a BFMLALT instruction.
This macro is used to encode the forms:
* BFMLALT <Vd>.4S, <Vn>.8H, <Vm>.H[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination vector register, Q (quadword, 128 bits). Rn The second source vector register, Q (quadword, 128 bits). Rm The third source vector register, Q (quadword, 128 bits). index The immediate index for Rm, in the range 0-7.
◆ INSTR_CREATE_bfmmla_sve
| #define INSTR_CREATE_bfmmla_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_bfmmla, Zda, Zda, Zn, Zm) |
Creates a BFMMLA instruction.
This macro is used to encode the forms:
* BFMMLA <Zda>.S, <Zn>.H, <Zm>.H *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_bfmmla_vector
| #define INSTR_CREATE_bfmmla_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_4src(dc, OP_bfmmla, Rd, Rd, Rn, Rm, OPND_CREATE_HALF()) |
Creates a BFMMLA instruction.
This macro is used to encode the forms:
* BFMMLA <Vd>.4S, <Vn>.8H, <Vm>.8H *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination vector register, Q (quadword, 128 bits). Rn The second source vector register, Q (quadword, 128 bits). Rm The third source vector register, Q (quadword, 128 bits).
◆ INSTR_CREATE_bgrp_sve
| #define INSTR_CREATE_bgrp_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_bgrp, Zd, Zn, Zm) |
Creates a BGRP instruction.
This macro is used to encode the forms:
* BGRP <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_bic_sve
| #define INSTR_CREATE_bic_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_bic, Zd, Zn, Zm) |
Creates a BIC instruction.
This macro is used to encode the forms:
* BIC <Zd>.D, <Zn>.D, <Zm>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_bic_sve_imm
| #define INSTR_CREATE_bic_sve_imm | ( | dc, | |
| Zdn, | |||
| imm | |||
| ) | instr_create_1dst_2src(dc, OP_and, Zdn, Zdn, opnd_invert_immed_int(imm)) |
Creates a BIC instruction.
This macro is used to encode the forms:
* BIC <Zdn>.<T>, <Zdn>.<T>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). imm The immediate logicalImm. The 13 bit immediate defining a 64, 32, 16 or 8 bit mask of 2, 4, 8, 16, 32 or 64 bit fields.
◆ INSTR_CREATE_bic_sve_pred
| #define INSTR_CREATE_bic_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_bic, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a BIC instruction.
This macro is used to encode the forms:
* BIC <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_bic_sve_pred_b
| #define INSTR_CREATE_bic_sve_pred_b | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_bic, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates a BIC instruction.
This macro is used to encode the forms:
* BIC <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_bic_vector
| #define INSTR_CREATE_bic_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_bic, Rd, Rm, Rn) |
Creates a BIC vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register.
◆ INSTR_CREATE_bics_sve_pred
| #define INSTR_CREATE_bics_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_bics, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates a BICS instruction.
This macro is used to encode the forms:
* BICS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_bif_vector
| #define INSTR_CREATE_bif_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_bif, Rd, Rm, Rn) |
Creates a BIF vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register.
◆ INSTR_CREATE_bit_vector
| #define INSTR_CREATE_bit_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_bit, Rd, Rm, Rn) |
Creates a BIT vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register.
◆ INSTR_CREATE_bl
| #define INSTR_CREATE_bl | ( | dc, | |
| pc | |||
| ) | instr_create_1dst_1src((dc), OP_bl, opnd_create_reg(DR_REG_X30), (pc)) |
◆ INSTR_CREATE_blraa
| #define INSTR_CREATE_blraa | ( | dc, | |
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_blraa, opnd_create_reg(DR_REG_X30), Rn, Rm) |
Creates a BLRAA instruction.
This macro is used to encode the forms:
* BLRAA <Xn>, <Xm|SP> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The first source register, X (Extended, 64 bits). Rm The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_blraaz
| #define INSTR_CREATE_blraaz | ( | dc, | |
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_blraaz, opnd_create_reg(DR_REG_X30), Rn) |
Creates a BLRAAZ instruction.
This macro is used to encode the forms:
* BLRAAZ <Xn> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The source register, X (Extended, 64 bits).
◆ INSTR_CREATE_blrab
| #define INSTR_CREATE_blrab | ( | dc, | |
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_blrab, opnd_create_reg(DR_REG_X30), Rn, Rm) |
Creates a BLRAB instruction.
This macro is used to encode the forms:
* BLRAB <Xn>, <Xm|SP> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The first source register, X (Extended, 64 bits). Rm The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_blrabz
| #define INSTR_CREATE_blrabz | ( | dc, | |
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_blrabz, opnd_create_reg(DR_REG_X30), Rn) |
Creates a BLRABZ instruction.
This macro is used to encode the forms:
* BLRABZ <Xn> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The source register, X (Extended, 64 bits).
◆ INSTR_CREATE_braa
| #define INSTR_CREATE_braa | ( | dc, | |
| Rn, | |||
| Rm | |||
| ) | instr_create_0dst_2src(dc, OP_braa, Rn, Rm) |
Creates a BRAA instruction.
This macro is used to encode the forms:
* BRAA <Xn>, <Xm|SP> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The first source register, X (Extended, 64 bits). Rm The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_braaz
| #define INSTR_CREATE_braaz | ( | dc, | |
| Rn | |||
| ) | instr_create_0dst_1src(dc, OP_braaz, Rn) |
Creates a BRAAZ instruction.
This macro is used to encode the forms:
* BRAAZ <Xn> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The source register, X (Extended, 64 bits).
◆ INSTR_CREATE_brab
| #define INSTR_CREATE_brab | ( | dc, | |
| Rn, | |||
| Rm | |||
| ) | instr_create_0dst_2src(dc, OP_brab, Rn, Rm) |
Creates a BRAB instruction.
This macro is used to encode the forms:
* BRAB <Xn>, <Xm|SP> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The first source register, X (Extended, 64 bits). Rm The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_brabz
| #define INSTR_CREATE_brabz | ( | dc, | |
| Rn | |||
| ) | instr_create_0dst_1src(dc, OP_brabz, Rn) |
Creates a BRABZ instruction.
This macro is used to encode the forms:
* BRABZ <Xn> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The source register, X (Extended, 64 bits).
◆ INSTR_CREATE_brka_sve_pred
| #define INSTR_CREATE_brka_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_brka, Pd, Pg, Pn), DR_PRED_MASKED) |
Creates a BRKA instruction.
This macro is used to encode the forms:
* BRKA <Pd>.B, <Pg>/<ZM>, <Pn>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The source predicate register, P (Predicate).
◆ INSTR_CREATE_brkas_sve_pred
| #define INSTR_CREATE_brkas_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_brkas, Pd, Pg, Pn), DR_PRED_MASKED) |
Creates a BRKAS instruction.
This macro is used to encode the forms:
* BRKAS <Pd>.B, <Pg>/Z, <Pn>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The source predicate register, P (Predicate).
◆ INSTR_CREATE_brkb_sve_pred
| #define INSTR_CREATE_brkb_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_brkb, Pd, Pg, Pn), DR_PRED_MASKED) |
Creates a BRKB instruction.
This macro is used to encode the forms:
* BRKB <Pd>.B, <Pg>/<ZM>, <Pn>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The source predicate register, P (Predicate).
◆ INSTR_CREATE_brkbs_sve_pred
| #define INSTR_CREATE_brkbs_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_brkbs, Pd, Pg, Pn), DR_PRED_MASKED) |
Creates a BRKBS instruction.
This macro is used to encode the forms:
* BRKBS <Pd>.B, <Pg>/Z, <Pn>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The source predicate register, P (Predicate).
◆ INSTR_CREATE_brkn_sve_pred
| #define INSTR_CREATE_brkn_sve_pred | ( | dc, | |
| Pdm, | |||
| Pg, | |||
| Pn | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_brkn, Pdm, Pg, Pn, Pdm), DR_PRED_MASKED) |
Creates a BRKN instruction.
This macro is used to encode the forms:
* BRKN <Pdm>.B, <Pg>/Z, <Pn>.B, <Pdm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pdm The second source and destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate).
◆ INSTR_CREATE_brkns_sve_pred
| #define INSTR_CREATE_brkns_sve_pred | ( | dc, | |
| Pdm, | |||
| Pg, | |||
| Pn | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_brkns, Pdm, Pg, Pn, Pdm), DR_PRED_MASKED) |
Creates a BRKNS instruction.
This macro is used to encode the forms:
* BRKNS <Pdm>.B, <Pg>/Z, <Pn>.B, <Pdm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pdm The second source and destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate).
◆ INSTR_CREATE_brkpa_sve_pred
| #define INSTR_CREATE_brkpa_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpa, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates a BRKPA instruction.
This macro is used to encode the forms:
* BRKPA <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_brkpas_sve_pred
| #define INSTR_CREATE_brkpas_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpas, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates a BRKPAS instruction.
This macro is used to encode the forms:
* BRKPAS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_brkpb_sve_pred
| #define INSTR_CREATE_brkpb_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpb, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates a BRKPB instruction.
This macro is used to encode the forms:
* BRKPB <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_brkpbs_sve_pred
| #define INSTR_CREATE_brkpbs_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpbs, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates a BRKPBS instruction.
This macro is used to encode the forms:
* BRKPBS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_bsl1n_sve
| #define INSTR_CREATE_bsl1n_sve | ( | dc, | |
| Zdn, | |||
| Zm, | |||
| Zk | |||
| ) | instr_create_1dst_3src(dc, OP_bsl1n, Zdn, Zdn, Zm, Zk) |
Creates a BSL1N instruction.
This macro is used to encode the forms:
* BSL1N <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Zm The second source vector register, Z (Scalable). Zk The third source vector register, Z (Scalable).
◆ INSTR_CREATE_bsl2n_sve
| #define INSTR_CREATE_bsl2n_sve | ( | dc, | |
| Zdn, | |||
| Zm, | |||
| Zk | |||
| ) | instr_create_1dst_3src(dc, OP_bsl2n, Zdn, Zdn, Zm, Zk) |
Creates a BSL2N instruction.
This macro is used to encode the forms:
* BSL2N <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Zm The second source vector register, Z (Scalable). Zk The third source vector register, Z (Scalable).
◆ INSTR_CREATE_bsl_sve
| #define INSTR_CREATE_bsl_sve | ( | dc, | |
| Zdn, | |||
| Zm, | |||
| Zk | |||
| ) | instr_create_1dst_3src(dc, OP_bsl, Zdn, Zdn, Zm, Zk) |
Creates a BSL instruction.
This macro is used to encode the forms:
* BSL <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Zm The second source vector register, Z (Scalable). Zk The third source vector register, Z (Scalable).
◆ INSTR_CREATE_bsl_vector
| #define INSTR_CREATE_bsl_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_bsl, Rd, Rm, Rn) |
Creates a BSL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register.
◆ INSTR_CREATE_cadd_sve
| #define INSTR_CREATE_cadd_sve | ( | dc, | |
| Zdn, | |||
| Zm, | |||
| rot | |||
| ) | instr_create_1dst_3src(dc, OP_cadd, Zdn, Zdn, Zm, rot) |
Creates a CADD instruction.
This macro is used to encode the forms:
CADD <Zdn>.<Ts>, <Zdn>.<Ts>, <Zm>.<Ts>, <const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. rot The immediate rotation which must be 90 or 270.
◆ INSTR_CREATE_ccmn
| #define INSTR_CREATE_ccmn | ( | dc, | |
| Rn, | |||
| Op, | |||
| nzcv, | |||
| cond | |||
| ) | instr_create_0dst_4src(dc, OP_ccmn, Rn, Op, nzcv, cond) |
Creates a CCMN (Conditional Compare Negative) instruction. Sets the NZCV flags to the result of a comparison of its two source values if the named input condition is true, or to an immediate value if the input condition is false. The comparison is based on a negated second source value (Op) if an immediate, inverted if a register.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. cond A 4-bit immediate value created using cond_create_cond() specifying the condition used for the comparison. For example opnd_create_cond(DR_PRED_EQ). Rn The GPR source register. Op Either a 5-bit immediate (use opnd_create_immed_uint() to create the operand, e.g. opnd_create_immed_uint(val, OPSZ_5b)) or a GPR source register. nzcv The 4 bit NZCV flags value used if the input condition is false. (use opnd_create_immed_uint() to create the operand, e.g. opnd_create_immed_uint(val, OPSZ_4b)).
◆ INSTR_CREATE_ccmp
| #define INSTR_CREATE_ccmp | ( | dc, | |
| Rn, | |||
| Op, | |||
| nzcv, | |||
| cond | |||
| ) | instr_create_0dst_4src(dc, OP_ccmp, Rn, Op, nzcv, cond) |
Creates a CCMP (Conditional Compare) instruction. Sets the NZCV flags to the result of a comparison of its two source values if the named input condition is true, or to an immediate value if the input condition is false.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. cond A 4-bit immediate value created using cond_create_cond() specifying the condition used for the comparison. For example opnd_create_cond(DR_PRED_EQ). Rn The GPR source register. Op Either a 5-bit immediate (use opnd_create_immed_uint() to create the operand, e.g. opnd_create_immed_uint(val, OPSZ_5b)) or a GPR source register. nzcv The 4 bit NZCV flags value used if the input condition is false. (use opnd_create_immed_uint() to create the operand, e.g. opnd_create_immed_uint(val, OPSZ_4b)).
◆ INSTR_CREATE_cdot_sve
| #define INSTR_CREATE_cdot_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| rot | |||
| ) | instr_create_1dst_4src(dc, OP_cdot, Zda, Zda, Zn, Zm, rot) |
Creates a CDOT instruction.
This macro is used to encode the forms:
CDOT <Zda>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>, <const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.s or Z.d. Zn The second source vector register. Can be Z.b or Z.h. Zm The third source vector register. Can be Z.b or Z.h. rot The immediate rotation which must be 0, 90, 180 or 270.
◆ INSTR_CREATE_cfinv
| #define INSTR_CREATE_cfinv | ( | dc | ) | instr_create_0dst_0src(dc, OP_cfinv) |
Creates a CFINV instruction.
This macro is used to encode the forms:
* CFINV *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_clasta_sve_scalar
| #define INSTR_CREATE_clasta_sve_scalar | ( | dc, | |
| Rdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_clasta, Rdn, Pg, Rdn, Zm), DR_PRED_MASKED) |
Creates a CLASTA instruction.
This macro is used to encode the forms:
* CLASTA <R><dn>, <Pg>, <R><dn>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register. Can be W (Word, 32 bits) or X (Extended, 64 bits). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_clasta_sve_simd_fp
| #define INSTR_CREATE_clasta_sve_simd_fp | ( | dc, | |
| Vdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_clasta, Vdn, Pg, Vdn, Zm), DR_PRED_MASKED) |
Creates a CLASTA instruction.
This macro is used to encode the forms:
* CLASTA <V><dn>, <Pg>, <V><dn>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vdn The first source and destination register. Can be D (doubleword, 64 bits), S (singleword, 32 bits), H (halfword, 16 bits) or B (byte, 8 bits). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_clasta_sve_vector
| #define INSTR_CREATE_clasta_sve_vector | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_clasta, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a CLASTA instruction.
This macro is used to encode the forms:
* CLASTA <Zdn>.<Ts>, <Pg>, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_clastb_sve_scalar
| #define INSTR_CREATE_clastb_sve_scalar | ( | dc, | |
| Rdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_clastb, Rdn, Pg, Rdn, Zm), DR_PRED_MASKED) |
Creates a CLASTB instruction.
This macro is used to encode the forms:
* CLASTB <R><dn>, <Pg>, <R><dn>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register. Can be W (Word, 32 bits) or X (Extended, 64 bits). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_clastb_sve_simd_fp
| #define INSTR_CREATE_clastb_sve_simd_fp | ( | dc, | |
| Vdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_clastb, Vdn, Pg, Vdn, Zm), DR_PRED_MASKED) |
Creates a CLASTB instruction.
This macro is used to encode the forms:
* CLASTB <V><dn>, <Pg>, <V><dn>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vdn The first source and destination register. Can be D (doubleword, 64 bits), S (singleword, 32 bits), H (halfword, 16 bits) or B (byte, 8 bits). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_clastb_sve_vector
| #define INSTR_CREATE_clastb_sve_vector | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_clastb, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a CLASTB instruction.
This macro is used to encode the forms:
* CLASTB <Zdn>.<Ts>, <Pg>, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_cls_sve_pred
| #define INSTR_CREATE_cls_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_cls, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a CLS instruction.
This macro is used to encode the forms:
* CLS <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_clz_sve_pred
| #define INSTR_CREATE_clz_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_clz, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a CLZ instruction.
This macro is used to encode the forms:
* CLZ <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_cmeq_vector
| #define INSTR_CREATE_cmeq_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_cmeq, Rd, Rm, Rn, width) |
Creates a CMEQ vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_cmge_vector
| #define INSTR_CREATE_cmge_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_cmge, Rd, Rm, Rn, width) |
Creates a CMGE vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_cmgt_vector
| #define INSTR_CREATE_cmgt_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_cmgt, Rd, Rm, Rn, width) |
Creates a CMGT vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_cmhi_vector
| #define INSTR_CREATE_cmhi_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_cmhi, Rd, Rm, Rn, width) |
Creates a CMHI vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_cmhs_vector
| #define INSTR_CREATE_cmhs_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_cmhs, Rd, Rm, Rn, width) |
Creates a CMHS vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_cmla_sve
| #define INSTR_CREATE_cmla_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| rot | |||
| ) | instr_create_1dst_4src(dc, OP_cmla, Zda, Zda, Zn, Zm, rot) |
Creates a CMLA instruction.
This macro is used to encode the forms:
CMLA <Zda>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts>, <const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. Zm The third source vector register. Can be Z.b, Z.h, Z.s or Z.d. rot The immediate rotation which must be 0, 90, 180 or 270.
◆ INSTR_CREATE_cmla_sve_idx_imm_vector
| #define INSTR_CREATE_cmla_sve_idx_imm_vector | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| i1, | |||
| rot | |||
| ) | instr_create_1dst_5src(dc, OP_cmla, Zda, Zda, Zn, Zm, i1, rot) |
Creates a CMLA instruction.
This macro is used to encode the forms:
CMLA <Zda>.S, <Zn>.S, <Zm>.S[<imm>], <const> CMLA <Zda>.H, <Zn>.H, <Zm>.H[<imm>], <const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.s or Z.h. Zn The second source vector register. Can be Z.s or Z.h. Zm The third source vector register. Can be Z.s or Z.h. i1 The immediate index for Zm. rot The immediate rotation which must be 0, 90, 180 or 270.
◆ INSTR_CREATE_cmpeq_sve_pred
| #define INSTR_CREATE_cmpeq_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpeq, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a CMPEQ instruction.
This macro is used to encode the forms:
* CMPEQ <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D * CMPEQ <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_cmpeq_sve_pred_simm
| #define INSTR_CREATE_cmpeq_sve_pred_simm | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| simm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpeq, Pd, Pg, Zn, simm), DR_PRED_MASKED) |
Creates a CMPEQ instruction.
This macro is used to encode the forms:
* CMPEQ <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable) simm The signed immediate imm
◆ INSTR_CREATE_cmpge_sve_pred
| #define INSTR_CREATE_cmpge_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpge, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a CMPGE instruction.
This macro is used to encode the forms:
* CMPGE <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D * CMPGE <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_cmpge_sve_pred_simm
| #define INSTR_CREATE_cmpge_sve_pred_simm | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| simm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpge, Pd, Pg, Zn, simm), DR_PRED_MASKED) |
Creates a CMPGE instruction.
This macro is used to encode the forms:
* CMPGE <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable) simm The signed immediate imm
◆ INSTR_CREATE_cmpgt_sve_pred
| #define INSTR_CREATE_cmpgt_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpgt, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a CMPGT instruction.
This macro is used to encode the forms:
* CMPGT <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D * CMPGT <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_cmpgt_sve_pred_simm
| #define INSTR_CREATE_cmpgt_sve_pred_simm | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| simm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpgt, Pd, Pg, Zn, simm), DR_PRED_MASKED) |
Creates a CMPGT instruction.
This macro is used to encode the forms:
* CMPGT <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable) simm The signed immediate imm
◆ INSTR_CREATE_cmphi_sve_pred
| #define INSTR_CREATE_cmphi_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphi, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a CMPHI instruction.
This macro is used to encode the forms:
* CMPHI <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D * CMPHI <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_cmphi_sve_pred_imm
| #define INSTR_CREATE_cmphi_sve_pred_imm | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| imm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphi, Pd, Pg, Zn, imm), DR_PRED_MASKED) |
Creates a CMPHI instruction.
This macro is used to encode the forms:
* CMPHI <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable) imm The immediate imm
◆ INSTR_CREATE_cmphs_sve_pred
| #define INSTR_CREATE_cmphs_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphs, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a CMPHS instruction.
This macro is used to encode the forms:
* CMPHS <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D * CMPHS <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_cmphs_sve_pred_imm
| #define INSTR_CREATE_cmphs_sve_pred_imm | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| imm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphs, Pd, Pg, Zn, imm), DR_PRED_MASKED) |
Creates a CMPHS instruction.
This macro is used to encode the forms:
* CMPHS <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable) imm The immediate imm
◆ INSTR_CREATE_cmple_sve_pred
| #define INSTR_CREATE_cmple_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmple, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a CMPLE instruction.
This macro is used to encode the forms:
* CMPLE <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_cmple_sve_pred_simm
| #define INSTR_CREATE_cmple_sve_pred_simm | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| simm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmple, Pd, Pg, Zn, simm), DR_PRED_MASKED) |
Creates a CMPLE instruction.
This macro is used to encode the forms:
* CMPLE <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable) simm The signed immediate imm
◆ INSTR_CREATE_cmplo_sve_pred
| #define INSTR_CREATE_cmplo_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplo, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a CMPLO instruction.
This macro is used to encode the forms:
* CMPLO <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_cmplo_sve_pred_imm
| #define INSTR_CREATE_cmplo_sve_pred_imm | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| imm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplo, Pd, Pg, Zn, imm), DR_PRED_MASKED) |
Creates a CMPLO instruction.
This macro is used to encode the forms:
* CMPLO <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable) imm The immediate imm
◆ INSTR_CREATE_cmpls_sve_pred
| #define INSTR_CREATE_cmpls_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpls, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a CMPLS instruction.
This macro is used to encode the forms:
* CMPLS <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_cmpls_sve_pred_imm
| #define INSTR_CREATE_cmpls_sve_pred_imm | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| imm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpls, Pd, Pg, Zn, imm), DR_PRED_MASKED) |
Creates a CMPLS instruction.
This macro is used to encode the forms:
* CMPLS <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable) imm The immediate imm
◆ INSTR_CREATE_cmplt_sve_pred
| #define INSTR_CREATE_cmplt_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplt, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a CMPLT instruction.
This macro is used to encode the forms:
* CMPLT <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_cmplt_sve_pred_simm
| #define INSTR_CREATE_cmplt_sve_pred_simm | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| simm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplt, Pd, Pg, Zn, simm), DR_PRED_MASKED) |
Creates a CMPLT instruction.
This macro is used to encode the forms:
* CMPLT <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable) simm The signed immediate imm
◆ INSTR_CREATE_cmpne_sve_pred
| #define INSTR_CREATE_cmpne_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpne, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a CMPNE instruction.
This macro is used to encode the forms:
* CMPNE <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.D * CMPNE <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_cmpne_sve_pred_simm
| #define INSTR_CREATE_cmpne_sve_pred_simm | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| simm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpne, Pd, Pg, Zn, simm), DR_PRED_MASKED) |
Creates a CMPNE instruction.
This macro is used to encode the forms:
* CMPNE <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable) simm The signed immediate imm
◆ INSTR_CREATE_cmtst_vector
| #define INSTR_CREATE_cmtst_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_cmtst, Rd, Rm, Rn, width) |
Creates a CMTST vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_cnot_sve_pred
| #define INSTR_CREATE_cnot_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_cnot, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a CNOT instruction.
This macro is used to encode the forms:
* CNOT <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable)
◆ INSTR_CREATE_cnt_sve_pred [1/2]
| #define INSTR_CREATE_cnt_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_cnt, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a CNT instruction.
This macro is used to encode the forms:
* CNT <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_cnt_sve_pred [2/2]
| #define INSTR_CREATE_cnt_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_cnt, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a CNT instruction.
This macro is used to encode the forms:
* CNT <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_cntb
| #define INSTR_CREATE_cntb | ( | dc, | |
| Rd, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_3src(dc, OP_cntb, Rd, pattern, OPND_CREATE_MUL(), imm) |
Creates a CNTB instruction.
This macro is used to encode the forms:
* CNTB <Xd>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register, X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_cntd
| #define INSTR_CREATE_cntd | ( | dc, | |
| Rd, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_3src(dc, OP_cntd, Rd, pattern, OPND_CREATE_MUL(), imm) |
Creates a CNTD instruction.
This macro is used to encode the forms:
* CNTD <Xd>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register, X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_cnth
| #define INSTR_CREATE_cnth | ( | dc, | |
| Rd, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_3src(dc, OP_cnth, Rd, pattern, OPND_CREATE_MUL(), imm) |
Creates a CNTH instruction.
This macro is used to encode the forms:
* CNTH <Xd>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register, X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_cntp_sve_pred
| #define INSTR_CREATE_cntp_sve_pred | ( | dc, | |
| Rd, | |||
| Pg, | |||
| Pn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_cntp, Rd, Pg, Pn), DR_PRED_MASKED) |
Creates a CNTP instruction.
This macro is used to encode the forms:
* CNTP <Xd>, <Pg>, <Pn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register, X (Extended, 64 bits). Pg The governing predicate register, P (Predicate). Pn The source predicate register, P (Predicate).
◆ INSTR_CREATE_cntw
| #define INSTR_CREATE_cntw | ( | dc, | |
| Rd, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_3src(dc, OP_cntw, Rd, pattern, OPND_CREATE_MUL(), imm) |
Creates a CNTW instruction.
This macro is used to encode the forms:
* CNTW <Xd>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register, X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_compact_sve
| #define INSTR_CREATE_compact_sve | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_compact, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a COMPACT instruction.
This macro is used to encode the forms:
* COMPACT <Zd>.<Ts>, <Pg>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_cpy_sve_pred
| #define INSTR_CREATE_cpy_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Rn_or_Vn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_cpy, Zd, Pg, Rn_or_Vn), DR_PRED_MASKED) |
Creates a CPY instruction.
This macro is used to encode the forms:
* CPY <Zd>.<T>, <Pg>/M, <R><n|SP> * CPY <Zd>.<T>, <Pg>/M, <V><n> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The first destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Rn_or_Vn The source register. Can be a general purpose register W (Word, 32 bits) or X (Extended, 64 bits), or a vector register B (Byte, 8 bits), H (Halfword, 16 bits), S (Singleword, 32 bits), or D (Doubleword, 64 bits).
◆ INSTR_CREATE_cpy_sve_shift_pred
| #define INSTR_CREATE_cpy_sve_shift_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| simm, | |||
| shift | |||
| ) |
Value:
INSTR_PRED( \
DR_PRED_MASKED)
Creates a CPY instruction.
This macro is used to encode the forms:
* CPY <Zd>.<Ts>, <Pg>/Z, #<simm>, <shift> * CPY <Zd>.<Ts>, <Pg>/M, #<simm>, <shift> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The first destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) simm The signed immediate imm shift The immediate shiftOp for simm
◆ INSTR_CREATE_ctermeq
| #define INSTR_CREATE_ctermeq | ( | dc, | |
| Rn, | |||
| Rm | |||
| ) | instr_create_0dst_2src(dc, OP_ctermeq, Rn, Rm) |
Creates a CTERMEQ instruction.
This macro is used to encode the forms:
* CTERMEQ <R><n>, <R><m> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The first source register. Can be X (Extended, 64 bits) or W (Word, 32 bits). Rm The second source register. Can be X (Extended, 64 bits) or W (Word, 32 bits).
◆ INSTR_CREATE_ctermne
| #define INSTR_CREATE_ctermne | ( | dc, | |
| Rn, | |||
| Rm | |||
| ) | instr_create_0dst_2src(dc, OP_ctermne, Rn, Rm) |
Creates a CTERMNE instruction.
This macro is used to encode the forms:
* CTERMNE <R><n>, <R><m> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The first source register. Can be X (Extended, 64 bits) or W (Word, 32 bits). Rm The second source register. Can be X (Extended, 64 bits) or W (Word, 32 bits).
◆ INSTR_CREATE_dc_cvadp
| #define INSTR_CREATE_dc_cvadp | ( | dc, | |
| Rn | |||
| ) |
Value:
dc, OP_dc_cvadp, \
Creates a DC CVADP instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The input register containing the virtual address to use. No alignment restrictions apply to this VA.
◆ INSTR_CREATE_dc_cvap
| #define INSTR_CREATE_dc_cvap | ( | dc, | |
| Rn | |||
| ) |
Value:
dc, OP_dc_cvap, \
Creates a DC CVAP instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The input register containing the virtual address to use. No alignment restrictions apply to this VA.
◆ INSTR_CREATE_dc_gva
| #define INSTR_CREATE_dc_gva | ( | dc, | |
| Rn | |||
| ) |
Value:
dc, OP_dc_gva, \
Creates a DC GVA instruction.
Writes allocation tags of a naturally aligned block of N bytes, where N is identified in DCZID_EL0 system register. This macro is used to encode the forms:
DC GVA, <Xt>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The input register containing the virtual address to use. There is no alignment restriction on the address within the block of N bytes that is used.
◆ INSTR_CREATE_dc_gzva
| #define INSTR_CREATE_dc_gzva | ( | dc, | |
| Rn | |||
| ) |
Value:
dc, OP_dc_gzva, \
Creates a DC GZVA instruction.
Writes zeros and allocation tags of a naturally aligned block of N bytes, where N is identified in DCZID_EL0 system register. This macro is used to encode the forms:
DC GZVA, <Xt>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The input register containing the virtual address to use. There is no alignment restriction on the address within the block of N bytes that is used.
◆ INSTR_CREATE_decb
| #define INSTR_CREATE_decb | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_decb, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
Creates a DECB instruction.
This macro is used to encode the forms:
* DECB <Xdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The GPR register to be decremented, X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_decd
| #define INSTR_CREATE_decd | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_decd, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
Creates a DECD instruction.
This macro is used to encode the forms:
* DECD <Xdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The GPR register to be decremented, X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_decd_sve
| #define INSTR_CREATE_decd_sve | ( | dc, | |
| Zdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_decd, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
Creates a DECD instruction.
This macro is used to encode the forms:
* DECD <Zdn>.D{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The vector register to be decremented, Z (Scalable). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_dech
| #define INSTR_CREATE_dech | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_dech, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
Creates a DECH instruction.
This macro is used to encode the forms:
* DECH <Xdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The GPR register to be decremented, X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_dech_sve
| #define INSTR_CREATE_dech_sve | ( | dc, | |
| Zdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_dech, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
Creates a DECH instruction.
This macro is used to encode the forms:
* DECH <Zdn>.H{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The vector register to be decremented, Z (Scalable). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_decp_sve
| #define INSTR_CREATE_decp_sve | ( | dc, | |
| Rdn, | |||
| Pm | |||
| ) | instr_create_1dst_2src(dc, OP_decp, Rdn, Rdn, Pm) |
Creates a DECP instruction.
This macro is used to encode the forms:
* DECP <Xdn>, <Pm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The GPR register to be decremented, X (Extended, 64 bits). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_decp_sve_vector
| #define INSTR_CREATE_decp_sve_vector | ( | dc, | |
| Zdn, | |||
| Pm | |||
| ) | instr_create_1dst_2src(dc, OP_decp, Zdn, Zdn, Pm) |
Creates a DECP instruction.
This macro is used to encode the forms:
* DECP <Zdn>.<Ts>, <Pm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The vector register to be decremented, Z (Scalable). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_decw
| #define INSTR_CREATE_decw | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_decw, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
Creates a DECW instruction.
This macro is used to encode the forms:
* DECW <Xdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The GPR register to be decremented, X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_decw_sve
| #define INSTR_CREATE_decw_sve | ( | dc, | |
| Zdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_decw, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
Creates a DECW instruction.
This macro is used to encode the forms:
* DECW <Zdn>.S{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The vector register to be decremented, Z (Scalable). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_dup_sve_idx
| #define INSTR_CREATE_dup_sve_idx | ( | dc, | |
| Zd, | |||
| Zn, | |||
| index | |||
| ) | instr_create_1dst_2src(dc, OP_dup, Zd, Zn, index) |
Creates a DUP instruction.
This macro is used to encode the forms:
* DUP <Zd>.<Ts>, <Zn>.<Ts>[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The source vector register, Z (Scalable). index Immediate index of source vector. The operand size must match the encoded field size, which depends on the element size of Zd and Zn; OPSZ_6b for byte, OPSZ_5b for halfword, OPSZ_4b for singleword, OPSZ_3b for doubleword, and OPSZ_2b for quadword.
◆ INSTR_CREATE_dup_sve_scalar
| #define INSTR_CREATE_dup_sve_scalar | ( | dc, | |
| Zd, | |||
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_dup, Zd, Rn) |
Creates a DUP instruction.
This macro is used to encode the forms:
* DUP <Zd>.<Ts>, <R><n|SP> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Rn The source vector register. Can be X (Extended, 64 bits) or W (Word, 32 bits).
◆ INSTR_CREATE_dup_sve_shift
| #define INSTR_CREATE_dup_sve_shift | ( | dc, | |
| Zd, | |||
| simm, | |||
| shift | |||
| ) | instr_create_1dst_3src(dc, OP_dup, Zd, simm, OPND_CREATE_LSL(), shift) |
Creates a DUP instruction.
This macro is used to encode the forms:
* DUP <Zd>.<Ts>, #<simm>, <shift> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). simm The signed immediate imm. shift Left shift to apply to the immediate, defaulting to LSL #0. Can be 0 or 8
◆ INSTR_CREATE_dupm_sve
| #define INSTR_CREATE_dupm_sve | ( | dc, | |
| Zd, | |||
| imm | |||
| ) | instr_create_1dst_1src(dc, OP_dupm, Zd, imm) |
Creates a DUPM instruction.
This macro is used to encode the forms:
* DUPM <Zd>.<Ts>, #<const> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). imm The immediate logicalImm. The 13 bit immediate defining a 64, 32, 16 or 8 bit mask of 2, 4, 8, 16, 32 or 64 bit fields.
◆ INSTR_CREATE_eon_sve_imm
| #define INSTR_CREATE_eon_sve_imm | ( | dc, | |
| Zdn, | |||
| imm | |||
| ) | instr_create_1dst_2src(dc, OP_eor, Zdn, Zdn, opnd_invert_immed_int(imm)) |
Creates an EON instruction.
This macro is used to encode the forms:
* EON <Zdn>.<Ts>, <Zdn>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). imm The immediate logicalImm. The 13 bit immediate defining a 64, 32, 16 or 8 bit mask of 2, 4, 8, 16, 32 or 64 bit fields.
◆ INSTR_CREATE_eor3
| #define INSTR_CREATE_eor3 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Ra | |||
| ) | instr_create_1dst_4src(dc, OP_eor3, Rd, Rn, Rm, Ra, OPND_CREATE_BYTE()) |
Creates a EOR3 instruction.
This macro is used to encode the forms:
* EOR3 <Bd>.16B, <Bn>.16B, <Bm>.16B, <Ba>.16B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register, Q (quadword, 128 bits) Rn The second source vector register, Q (quadword, 128 bits) Rm The third source vector register, Q (quadword, 128 bits) Ra The fourth source vector register, Q (quadword, 128 bits)
◆ INSTR_CREATE_eor3_sve
| #define INSTR_CREATE_eor3_sve | ( | dc, | |
| Zdn, | |||
| Zm, | |||
| Zk | |||
| ) | instr_create_1dst_3src(dc, OP_eor3, Zdn, Zdn, Zm, Zk) |
Creates an EOR3 instruction.
This macro is used to encode the forms:
* EOR3 <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Zm The second source vector register, Z (Scalable). Zk The third source vector register, Z (Scalable).
◆ INSTR_CREATE_eor_sve
| #define INSTR_CREATE_eor_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_eor, Zd, Zn, Zm) |
Creates an EOR instruction.
This macro is used to encode the forms:
* EOR <Zd>.D, <Zn>.D, <Zm>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_eor_sve_imm
| #define INSTR_CREATE_eor_sve_imm | ( | dc, | |
| Zdn, | |||
| imm | |||
| ) | instr_create_1dst_2src(dc, OP_eor, Zdn, Zdn, imm) |
Creates an EOR instruction.
This macro is used to encode the forms:
* EOR <Zdn>.<T>, <Zdn>.<T>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). imm The immediate logicalImm. The 13 bit immediate defining a 64, 32, 16 or 8 bit mask of 2, 4, 8, 16, 32 or 64 bit fields.
◆ INSTR_CREATE_eor_sve_pred
| #define INSTR_CREATE_eor_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_eor, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an EOR instruction.
This macro is used to encode the forms:
* EOR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_eor_sve_pred_b
| #define INSTR_CREATE_eor_sve_pred_b | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_eor, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates an EOR instruction.
This macro is used to encode the forms:
* EOR <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_eor_vector
| #define INSTR_CREATE_eor_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_eor, Rd, Rm, Rn) |
Creates a EOR vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register.
◆ INSTR_CREATE_eorbt_sve
| #define INSTR_CREATE_eorbt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_eorbt, Zd, Zd, Zn, Zm) |
Creates an EORBT instruction.
This macro is used to encode the forms:
* EORBT <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_eors_sve_pred
| #define INSTR_CREATE_eors_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_eors, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates an EORS instruction.
This macro is used to encode the forms:
* EORS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_eortb_sve
| #define INSTR_CREATE_eortb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_eortb, Zd, Zd, Zn, Zm) |
Creates an EORTB instruction.
This macro is used to encode the forms:
* EORTB <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_eorv_sve_pred
| #define INSTR_CREATE_eorv_sve_pred | ( | dc, | |
| Vd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_eorv, Vd, Pg, Zn), DR_PRED_MASKED) |
Creates an EORV instruction.
This macro is used to encode the forms:
* EORV <V><d>, <Pg>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vd The destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits), B (byte, 8 bits) or D (doubleword, 64 bits). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_eretaa
| #define INSTR_CREATE_eretaa | ( | dc | ) |
Value:
instr_create_0dst_2src(dc, OP_eretaa, opnd_create_reg(DR_REG_X30), \
Creates an ERETAA instruction.
This macro is used to encode the forms:
* ERETAA *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_eretab
| #define INSTR_CREATE_eretab | ( | dc | ) |
Value:
instr_create_0dst_2src(dc, OP_eretab, opnd_create_reg(DR_REG_X30), \
Creates an ERETAB instruction.
This macro is used to encode the forms:
* ERETAB *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_esb
| #define INSTR_CREATE_esb | ( | dc | ) | instr_create_0dst_0src(dc, OP_esb) |
Creates a ESB instruction.
This macro is used to encode the forms:
* ESB *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_ext_sve
| #define INSTR_CREATE_ext_sve | ( | dc, | |
| Zdn, | |||
| Zm, | |||
| imm | |||
| ) | instr_create_1dst_3src(dc, OP_ext, Zdn, Zdn, Zm, imm) |
Creates an EXT instruction (destructive).
This macro is used to encode the forms:
* EXT <Zdn>.B, <Zdn>.B, <Zm>.B, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Zm The second source vector register, Z (Scalable). imm The immediate imm.
◆ INSTR_CREATE_fabd_sve
| #define INSTR_CREATE_fabd_sve | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fabd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a FABD instruction.
This macro is used to encode the forms:
* FABD <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_fabd_vector
| #define INSTR_CREATE_fabd_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_fabd, Rd, Rm, Rn, width) |
Creates a FABD vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_fabs_scalar
| #define INSTR_CREATE_fabs_scalar | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src(dc, OP_fabs, Rd, Rm) |
Creates a FABS floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register.
◆ INSTR_CREATE_fabs_sve
| #define INSTR_CREATE_fabs_sve | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_fabs, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a FABS instruction.
This macro is used to encode the forms:
* FABS <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_facge
| #define INSTR_CREATE_facge | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_facge, Rd, Rn, Rm) |
Creates a FACGE instruction.
This macro is used to encode the forms:
* FACGE <Hd>, <Hn>, <Hm> * FACGE <V><d>, <V><n>, <V><m> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits) Rn The second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits) Rm The third source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
◆ INSTR_CREATE_facge_sve_pred
| #define INSTR_CREATE_facge_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_facge, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a FACGE instruction.
This macro is used to encode the forms:
* FACGE <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_facge_vector
| #define INSTR_CREATE_facge_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_3src(dc, OP_facge, Rd, Rn, Rm, Rm_elsz) |
Creates a FACGE vector instruction.
This macro is used to encode the forms:
* FACGE <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts> * FACGE <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm The third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm_elsz The element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_facgt
| #define INSTR_CREATE_facgt | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_facgt, Rd, Rn, Rm) |
Creates a FACGT instruction.
This macro is used to encode the forms:
* FACGT <Hd>, <Hn>, <Hm> * FACGT <V><d>, <V><n>, <V><m> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits) Rn The second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits) Rm The third source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
◆ INSTR_CREATE_facgt_sve_pred
| #define INSTR_CREATE_facgt_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_facgt, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a FACGT instruction.
This macro is used to encode the forms:
* FACGT <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_facgt_vector
| #define INSTR_CREATE_facgt_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_3src(dc, OP_facgt, Rd, Rn, Rm, Rm_elsz) |
Creates a FACGT vector instruction.
This macro is used to encode the forms:
* FACGT <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts> * FACGT <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm The third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm_elsz The element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_fadd_scalar
| #define INSTR_CREATE_fadd_scalar | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_fadd, Rd, Rm, Rn) |
Creates a FADD floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register.
◆ INSTR_CREATE_fadd_sve
| #define INSTR_CREATE_fadd_sve | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| imm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fadd, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
Creates a FADD instruction.
This macro is used to encode the forms:
* FADD <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). imm Floating point constant, either 0.5 or 1.0.
◆ INSTR_CREATE_fadd_sve_pred
| #define INSTR_CREATE_fadd_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a FADD instruction.
This macro is used to encode the forms:
* FADD <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_fadd_sve_vector
| #define INSTR_CREATE_fadd_sve_vector | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_fadd, Zd, Zn, Zm) |
Creates a FADD instruction.
This macro is used to encode the forms:
* FADD <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_fadd_vector
| #define INSTR_CREATE_fadd_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_fadd, Rd, Rm, Rn, width) |
Creates a FADD vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_fadda_sve_pred
| #define INSTR_CREATE_fadda_sve_pred | ( | dc, | |
| Vdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fadda, Vdn, Pg, Vdn, Zm), DR_PRED_MASKED) |
Creates a FADDA instruction.
This macro is used to encode the forms:
* FADDA <V><dn>, <Pg>, <V><dn>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vdn The first source and destination register. Can be S (singleword, 32 bits), H (halfword, 16 bits) or D (doubleword, 64 bits). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_faddp_scalar
| #define INSTR_CREATE_faddp_scalar | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rn_elsz | |||
| ) | instr_create_1dst_2src(dc, OP_faddp, Rd, Rn, Rn_elsz) |
Creates a FADDP instruction.
This macro is used to encode the forms:
* FADDP <Hd>, <Hn>.2H * FADDP <V><d>, <Sn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits) Rn The second source vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn_elsz The element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_faddp_sve_pred
| #define INSTR_CREATE_faddp_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_faddp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a FADDP instruction.
This macro is used to encode the forms:
FADDP <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.h, Z.s or Z.d.
◆ INSTR_CREATE_faddp_vector
| #define INSTR_CREATE_faddp_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_3src(dc, OP_faddp, Rd, Rn, Rm, Rm_elsz) |
Creates a FADDP instruction.
This macro is used to encode the forms:
* FADDP <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts> * FADDP <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm The third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm_elsz The element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_faddv_sve_pred
| #define INSTR_CREATE_faddv_sve_pred | ( | dc, | |
| Vd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_faddv, Vd, Pg, Zn), DR_PRED_MASKED) |
Creates a FADDV instruction.
This macro is used to encode the forms:
* FADDV <V><d>, <Pg>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vd The destination register. Can be S (singleword, 32 bits), H (halfword, 16 bits) or D (doubleword, 64 bits). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_fcadd_sve_pred
| #define INSTR_CREATE_fcadd_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm, | |||
| rot | |||
| ) |
Value:
INSTR_PRED(instr_create_1dst_4src(dc, OP_fcadd, Zdn, Pg, Zdn, Zm, rot), \
DR_PRED_MASKED)
Creates a FCADD instruction.
This macro is used to encode the forms:
* FCADD <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>, <rot> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable). rot The immediate rot, must be 90 or 270.
◆ INSTR_CREATE_fcadd_vector
| #define INSTR_CREATE_fcadd_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| rot, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_5src(dc, OP_fcadd, Rd, Rd, Rn, Rm, rot, Rm_elsz) |
Creates a FCADD instruction.
This macro is used to encode the forms:
* FCADD <Vd>.<Ts>, <Vn>.<Ts>, <Vm>.<Ts>, #<rot> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits). Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits). Rm The third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits). rot The immediate rot, must be 90 or 270. Rm_elsz The element size for Rm. Can be OPND_CREATE_HALF() or OPND_CREATE_SINGLE()
◆ INSTR_CREATE_fccmp
| #define INSTR_CREATE_fccmp | ( | dc, | |
| Rn, | |||
| Rm, | |||
| nzcv, | |||
| cond | |||
| ) | instr_create_0dst_4src(dc, OP_fccmp, Rn, Rm, nzcv, cond) |
Creates a FCCMP instruction.
This macro is used to encode the forms:
* FCCMP <Dn>, <Dm>, #<imm>, <cond> * FCCMP <Hn>, <Hm>, #<imm>, <cond> * FCCMP <Sn>, <Sm>, #<imm>, <cond> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The first source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits) Rm The second source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits) nzcv The 4 bit NZCV flags value used if the input condition is false. (use opnd_create_immed_uint() to create the operand, e.g. opnd_create_immed_uint(val, OPSZ_4b)). cond A 4-bit immediate value created using cond_create_cond() specifying the condition used for the comparison. For example opnd_create_cond(DR_PRED_EQ).
◆ INSTR_CREATE_fccmpe
| #define INSTR_CREATE_fccmpe | ( | dc, | |
| Rn, | |||
| Rm, | |||
| nzcv, | |||
| cond | |||
| ) | instr_create_0dst_4src(dc, OP_fccmpe, Rn, Rm, nzcv, cond) |
Creates a FCCMPE instruction.
This macro is used to encode the forms:
* FCCMPE <Dn>, <Dm>, #<imm>, <cond> * FCCMPE <Hn>, <Hm>, #<imm>, <cond> * FCCMPE <Sn>, <Sm>, #<imm>, <cond> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The first source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits) Rm The second source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits) nzcv The 4 bit NZCV flags value used if the input condition is false. (use opnd_create_immed_uint() to create the operand, e.g. opnd_create_immed_uint(val, OPSZ_4b)). cond A 4-bit immediate value created using cond_create_cond() specifying the condition used for the comparison. For example opnd_create_cond(DR_PRED_EQ).
◆ INSTR_CREATE_fcmeq
| #define INSTR_CREATE_fcmeq | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_fcmeq, Rd, Rn, Rm) |
Creates a FCMEQ instruction.
This macro is used to encode the forms:
* FCMEQ <Hd>, <Hn>, <Hm> * FCMEQ <V><d>, <V><n>, <V><m> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits) Rn The second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits) Rm The third source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
◆ INSTR_CREATE_fcmeq_sve_pred
| #define INSTR_CREATE_fcmeq_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmeq, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a FCMEQ instruction.
This macro is used to encode the forms:
* FCMEQ <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_fcmeq_sve_zero_pred
| #define INSTR_CREATE_fcmeq_sve_zero_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn | |||
| ) |
Value:
INSTR_PRED( \
instr_create_1dst_3src(dc, OP_fcmeq, Pd, Pg, Zn, opnd_create_immed_float(0.0)), \
DR_PRED_MASKED)
Creates a FCMEQ instruction.
This macro is used to encode the forms:
* FCMEQ <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #0.0 *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable)
◆ INSTR_CREATE_fcmeq_vector
| #define INSTR_CREATE_fcmeq_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_3src(dc, OP_fcmeq, Rd, Rn, Rm, Rm_elsz) |
Creates a FCMEQ instruction.
This macro is used to encode the forms:
* FCMEQ <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts> * FCMEQ <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm The third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm_elsz The element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_fcmeq_vector_zero
| #define INSTR_CREATE_fcmeq_vector_zero | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rn_elsz | |||
| ) | instr_create_1dst_3src(dc, OP_fcmeq, Rd, Rn, opnd_create_immed_float(0), Rn_elsz) |
Creates a FCMEQ instruction.
This macro is used to encode the forms:
* FCMEQ <Hd>.<Ts>, <Hn>.<Ts>, #0 * FCMEQ <Dd>.<Ts>, <Dn>.<Ts>, #0 *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn_elsz The element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_fcmeq_zero
| #define INSTR_CREATE_fcmeq_zero | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_fcmeq, Rd, Rn, opnd_create_immed_float(0)) |
Creates a FCMEQ instruction.
This macro is used to encode the forms:
* FCMEQ <Hd>, <Hn>, #0 * FCMEQ <V><d>, <V><n>, #0 *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits) Rn The second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
◆ INSTR_CREATE_fcmge_sve_pred
| #define INSTR_CREATE_fcmge_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmge, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a FCMGE instruction.
This macro is used to encode the forms:
* FCMGE <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_fcmge_sve_zero_pred
| #define INSTR_CREATE_fcmge_sve_zero_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn | |||
| ) |
Value:
INSTR_PRED( \
instr_create_1dst_3src(dc, OP_fcmge, Pd, Pg, Zn, opnd_create_immed_float(0.0)), \
DR_PRED_MASKED)
Creates a FCMGE instruction.
This macro is used to encode the forms:
* FCMGE <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #0.0 *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable)
◆ INSTR_CREATE_fcmge_vector
| #define INSTR_CREATE_fcmge_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_fcmge, Rd, Rm, Rn, width) |
Creates a FCMGE vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_fcmgt
| #define INSTR_CREATE_fcmgt | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_fcmgt, Rd, Rn, Rm) |
Creates a FCMGT instruction.
This macro is used to encode the forms:
* FCMGT <Hd>, <Hn>, <Hm> * FCMGT <V><d>, <V><n>, <V><m> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits) Rn The second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits) Rm The third source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
◆ INSTR_CREATE_fcmgt_sve_pred
| #define INSTR_CREATE_fcmgt_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmgt, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a FCMGT instruction.
This macro is used to encode the forms:
* FCMGT <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_fcmgt_sve_zero_pred
| #define INSTR_CREATE_fcmgt_sve_zero_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn | |||
| ) |
Value:
INSTR_PRED( \
instr_create_1dst_3src(dc, OP_fcmgt, Pd, Pg, Zn, opnd_create_immed_float(0.0)), \
DR_PRED_MASKED)
Creates a FCMGT instruction.
This macro is used to encode the forms:
* FCMGT <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #0.0 *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable)
◆ INSTR_CREATE_fcmgt_vector
| #define INSTR_CREATE_fcmgt_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_3src(dc, OP_fcmgt, Rd, Rn, Rm, Rm_elsz) |
Creates a FCMGT instruction.
This macro is used to encode the forms:
* FCMGT <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts> * FCMGT <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm The third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm_elsz The element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_fcmgt_vector_zero
| #define INSTR_CREATE_fcmgt_vector_zero | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rn_elsz | |||
| ) | instr_create_1dst_3src(dc, OP_fcmgt, Rd, Rn, opnd_create_immed_float(0.0), Rn_elsz) |
Creates a FCMGT instruction.
This macro is used to encode the forms:
* FCMGT <Hd>.<Ts>, <Hn>.<Ts>, #0 * FCMGT <Dd>.<Ts>, <Dn>.<Ts>, #0 *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn_elsz The element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_fcmgt_zero
| #define INSTR_CREATE_fcmgt_zero | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_fcmgt, Rd, Rn, opnd_create_immed_float(0.0)) |
Creates a FCMGT instruction.
This macro is used to encode the forms:
* FCMGT <Hd>, <Hn>, #0 * FCMGT <V><d>, <V><n>, #0 *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits) Rn The second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
◆ INSTR_CREATE_fcmla_sve_idx
| #define INSTR_CREATE_fcmla_sve_idx | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| imm, | |||
| rot | |||
| ) | instr_create_1dst_5src(dc, OP_fcmla, Zda, Zda, Zn, Zm, imm, rot) |
Creates a FCMLA instruction.
This macro is used to encode the forms:
* FCMLA <Zda>.H, <Zn>.H, <Zm>.H[<imm>], <rot> * FCMLA <Zda>.S, <Zn>.S, <Zm>.S[<imm>], <rot> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable). imm The immediate imm representing index of a Real and Imaginary pair rot The immediate rot, must be 0, 90, 180, or 270.
◆ INSTR_CREATE_fcmla_sve_vector
| #define INSTR_CREATE_fcmla_sve_vector | ( | dc, | |
| Zda, | |||
| Pg, | |||
| Zn, | |||
| Zm, | |||
| rot | |||
| ) |
Value:
INSTR_PRED(instr_create_1dst_5src(dc, OP_fcmla, Zda, Zda, Pg, Zn, Zm, rot), \
DR_PRED_MASKED)
Creates a FCMLA instruction.
This macro is used to encode the forms:
* FCMLA <Zda>.<Ts>, <Pg>/M, <Zn>.<Ts>, <Zm>.<Ts>, <rot> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable). rot The immediate rot, must be 0, 90, 180, or 270.
◆ INSTR_CREATE_fcmla_vector
| #define INSTR_CREATE_fcmla_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| rot, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_5src(dc, OP_fcmla, Rd, Rd, Rn, Rm, rot, Rm_elsz) |
Creates a FCMLA instruction.
This macro is used to encode the forms:
* FCMLA <Vd>.<Ts>, <Vn>.<Ts>, <Vm>.<Ts>, #<rot> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits). Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits). Rm The third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits). rot The immediate rot, must be 0, 90, 180, or 270. Rm_elsz The element size for Rm. Can be OPND_CREATE_HALF() or OPND_CREATE_SINGLE()
◆ INSTR_CREATE_fcmla_vector_idx
| #define INSTR_CREATE_fcmla_vector_idx | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| index, | |||
| rot, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_6src(dc, OP_fcmla, Rd, Rd, Rn, Rm, index, rot, Rm_elsz) |
Creates a FCMLA instruction.
This macro is used to encode the forms:
* FCMLA <Vd>.<Ts>, <Vn>.<Ts>, <Vm>.<Tb>[<index>], #<rot> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits). Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits). Rm The third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits). index The immediate index for Rm. In the range 0-3 for when Rm_elsz is OPND_CREATE_HALF() and Rm is Q, othewise in range 0-1. rot The immediate rot, must be 0, 90, 180, or 270. Rm_elsz The element size for Rm. Can be OPND_CREATE_HALF() or OPND_CREATE_SINGLE()
◆ INSTR_CREATE_fcmle_sve_pred
| #define INSTR_CREATE_fcmle_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zm, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmle, Pd, Pg, Zm, Zn), DR_PRED_MASKED) |
Creates a FCMLE instruction.
This macro is used to encode the forms:
* FCMLE <Pd>.<Ts>, <Pg>/Z, <Zm>.<Ts>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zm The first source vector register, Z (Scalable) Zn The second source vector register, Z (Scalable)
◆ INSTR_CREATE_fcmle_sve_zero_pred
| #define INSTR_CREATE_fcmle_sve_zero_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn | |||
| ) |
Value:
INSTR_PRED( \
instr_create_1dst_3src(dc, OP_fcmle, Pd, Pg, Zn, opnd_create_immed_float(0.0)), \
DR_PRED_MASKED)
Creates a FCMLE instruction.
This macro is used to encode the forms:
* FCMLE <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #0.0 *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable)
◆ INSTR_CREATE_fcmle_vector_zero
| #define INSTR_CREATE_fcmle_vector_zero | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rn_elsz | |||
| ) | instr_create_1dst_3src(dc, OP_fcmle, Rd, Rn, opnd_create_immed_float(0.0), Rn_elsz) |
Creates a FCMLE instruction.
This macro is used to encode the forms:
* FCMLE <Hd>.<Ts>, <Hn>.<Ts>, #0 * FCMLE <Dd>.<Ts>, <Dn>.<Ts>, #0 *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn_elsz The element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_fcmle_zero
| #define INSTR_CREATE_fcmle_zero | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_fcmle, Rd, Rn, opnd_create_immed_float(0.0)) |
Creates a FCMLE instruction.
This macro is used to encode the forms:
* FCMLE <Hd>, <Hn>, #0 * FCMLE <V><d>, <V><n>, #0 *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits) Rn The second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
◆ INSTR_CREATE_fcmlt_sve_pred
| #define INSTR_CREATE_fcmlt_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zm, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmlt, Pd, Pg, Zm, Zn), DR_PRED_MASKED) |
Creates a FCMLT instruction.
This macro is used to encode the forms:
* FCMLT <Pd>.<Ts>, <Pg>/Z, <Zm>.<Ts>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zm The first source vector register, Z (Scalable) Zn The second source vector register, Z (Scalable)
◆ INSTR_CREATE_fcmlt_sve_zero_pred
| #define INSTR_CREATE_fcmlt_sve_zero_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn | |||
| ) |
Value:
INSTR_PRED( \
instr_create_1dst_3src(dc, OP_fcmlt, Pd, Pg, Zn, opnd_create_immed_float(0.0)), \
DR_PRED_MASKED)
Creates a FCMLT instruction.
This macro is used to encode the forms:
* FCMLT <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #0.0 *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable)
◆ INSTR_CREATE_fcmlt_vector_zero
| #define INSTR_CREATE_fcmlt_vector_zero | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rn_elsz | |||
| ) | instr_create_1dst_3src(dc, OP_fcmlt, Rd, Rn, opnd_create_immed_float(0.0), Rn_elsz) |
Creates a FCMLT instruction.
This macro is used to encode the forms:
* FCMLT <Hd>.<Ts>, <Hn>.<Ts>, #0 * FCMLT <Dd>.<Ts>, <Dn>.<Ts>, #0 *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn_elsz The element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_fcmlt_zero
| #define INSTR_CREATE_fcmlt_zero | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_fcmlt, Rd, Rn, opnd_create_immed_float(0.0)) |
Creates a FCMLT instruction.
This macro is used to encode the forms:
* FCMLT <Hd>, <Hn>, #0 * FCMLT <V><d>, <V><n>, #0 *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits) Rn The second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
◆ INSTR_CREATE_fcmne_sve_pred
| #define INSTR_CREATE_fcmne_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmne, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a FCMNE instruction.
This macro is used to encode the forms:
* FCMNE <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_fcmne_sve_zero_pred
| #define INSTR_CREATE_fcmne_sve_zero_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn | |||
| ) |
Value:
INSTR_PRED( \
instr_create_1dst_3src(dc, OP_fcmne, Pd, Pg, Zn, opnd_create_immed_float(0.0)), \
DR_PRED_MASKED)
Creates a FCMNE instruction.
This macro is used to encode the forms:
* FCMNE <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, #0.0 *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable)
◆ INSTR_CREATE_fcmp
| #define INSTR_CREATE_fcmp | ( | dc, | |
| Rn, | |||
| Rm | |||
| ) | instr_create_0dst_2src(dc, OP_fcmp, Rn, Rm) |
Creates a FCMP instruction.
This macro is used to encode the forms:
* FCMP <Dn>, <Dm> * FCMP <Hn>, <Hm> * FCMP <Sn>, <Sm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The first source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits) Rm The second source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)
◆ INSTR_CREATE_fcmp_zero
| #define INSTR_CREATE_fcmp_zero | ( | dc, | |
| Rn | |||
| ) | instr_create_0dst_2src(dc, OP_fcmp, Rn, opnd_create_immed_float(0.0)) |
Creates a FCMP instruction.
This macro is used to encode the forms:
* FCMP <Dn>, #0.0 * FCMP <Hn>, #0.0 * FCMP <Sn>, #0.0 *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The first source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)
◆ INSTR_CREATE_fcmpe
| #define INSTR_CREATE_fcmpe | ( | dc, | |
| Rn, | |||
| Rm | |||
| ) | instr_create_0dst_2src(dc, OP_fcmpe, Rn, Rm) |
Creates a FCMPE instruction.
This macro is used to encode the forms:
* FCMPE <Dn>, <Dm> * FCMPE <Hn>, <Hm> * FCMPE <Sn>, <Sm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The first source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits) Rm The second source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)
◆ INSTR_CREATE_fcmpe_zero
| #define INSTR_CREATE_fcmpe_zero | ( | dc, | |
| Rn | |||
| ) | instr_create_0dst_2src(dc, OP_fcmpe, Rn, opnd_create_immed_float(0.0)) |
Creates a FCMPE instruction.
This macro is used to encode the forms:
* FCMPE <Dn>, #0.0 * FCMPE <Hn>, #0.0 * FCMPE <Sn>, #0.0 *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The first source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits)
◆ INSTR_CREATE_fcmuo_sve_pred
| #define INSTR_CREATE_fcmuo_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmuo, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a FCMUO instruction.
This macro is used to encode the forms:
* FCMUO <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_fcsel
| #define INSTR_CREATE_fcsel | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| cond | |||
| ) | instr_create_1dst_3src(dc, OP_fcsel, Rd, Rn, Rm, cond) |
Creates a FCSEL instruction.
This macro is used to encode the forms:
* FCSEL <Dd>, <Dn>, <Dm>, <cond> * FCSEL <Hd>, <Hn>, <Hm>, <cond> * FCSEL <Sd>, <Sn>, <Sm>, <cond> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits) Rn The second source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits) Rm The third source register. Can be D (doubleword, 64 bits), H (halfword, 16 bits) or S (singleword, 32 bits) cond A 4-bit immediate value created using cond_create_cond() specifying the condition used for the comparison. For example opnd_create_cond(DR_PRED_EQ).
◆ INSTR_CREATE_fcvt_scalar
| #define INSTR_CREATE_fcvt_scalar | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src(dc, OP_fcvt, Rd, Rm) |
Creates an FCVT floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd Floating-point or integer output register. Rm Floating-point input register.
◆ INSTR_CREATE_fcvt_sve_pred
| #define INSTR_CREATE_fcvt_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvt, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a FCVT instruction.
This macro is used to encode the forms:
* FCVT <Zd>.H, <Pg>/M, <Zn>.D * FCVT <Zd>.S, <Pg>/M, <Zn>.D * FCVT <Zd>.D, <Pg>/M, <Zn>.H * FCVT <Zd>.S, <Pg>/M, <Zn>.H * FCVT <Zd>.D, <Pg>/M, <Zn>.S * FCVT <Zd>.H, <Pg>/M, <Zn>.S *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_fcvtas_scalar
| #define INSTR_CREATE_fcvtas_scalar | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src(dc, OP_fcvtas, Rd, Rm) |
Creates an FCVTAS floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd Floating-point or integer output register. Rm Floating-point input register.
◆ INSTR_CREATE_fcvtas_vector
| #define INSTR_CREATE_fcvtas_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| width | |||
| ) | instr_create_1dst_2src(dc, OP_fcvtas, Rd, Rm, width) |
Creates an FCVTAS vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The input vector register. width Immediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_fcvtau_scalar
| #define INSTR_CREATE_fcvtau_scalar | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src(dc, OP_fcvtau, Rd, Rm) |
Creates an FCVTAU floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd Floating-point or integer output register. Rm Floating-point input register.
◆ INSTR_CREATE_fcvtau_vector
| #define INSTR_CREATE_fcvtau_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| width | |||
| ) | instr_create_1dst_2src(dc, OP_fcvtau, Rd, Rm, width) |
Creates an FCVTAU vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The input vector register. width Immediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_fcvtlt_sve_pred
| #define INSTR_CREATE_fcvtlt_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvtlt, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a FCVTLT instruction.
This macro is used to encode the forms:
FCVTLT <Zd>.S, <Pg>/M, <Zn>.H FCVTLT <Zd>.D, <Pg>/M, <Zn>.S
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zn The source vector register. Can be Z.h or Z.s.
◆ INSTR_CREATE_fcvtms_scalar
| #define INSTR_CREATE_fcvtms_scalar | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src(dc, OP_fcvtms, Rd, Rm) |
Creates an FCVTMS floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd Floating-point or integer output register. Rm Floating-point input register.
◆ INSTR_CREATE_fcvtms_vector
| #define INSTR_CREATE_fcvtms_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| width | |||
| ) | instr_create_1dst_2src(dc, OP_fcvtms, Rd, Rm, width) |
Creates an FCVTMS vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The input vector register. width Immediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_fcvtmu_scalar
| #define INSTR_CREATE_fcvtmu_scalar | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src(dc, OP_fcvtmu, Rd, Rm) |
Creates an FCVTMU floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd Floating-point or integer output register. Rm Floating-point input register.
◆ INSTR_CREATE_fcvtmu_vector
| #define INSTR_CREATE_fcvtmu_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| width | |||
| ) | instr_create_1dst_2src(dc, OP_fcvtmu, Rd, Rm, width) |
Creates an FCVTMU vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The input vector register. width Immediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_fcvtns_scalar
| #define INSTR_CREATE_fcvtns_scalar | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src(dc, OP_fcvtns, Rd, Rm) |
Creates an FCVTNS floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd Floating-point or integer output register. Rm Floating-point input register.
◆ INSTR_CREATE_fcvtns_vector
| #define INSTR_CREATE_fcvtns_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| width | |||
| ) | instr_create_1dst_2src(dc, OP_fcvtns, Rd, Rm, width) |
Creates an FCVTNS vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. width Immediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_fcvtnt_sve_pred
| #define INSTR_CREATE_fcvtnt_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fcvtnt, Zd, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a FCVTNT instruction.
This macro is used to encode the forms:
FCVTNT <Zd>.S, <Pg>/M, <Zn>.D FCVTNT <Zd>.H, <Pg>/M, <Zn>.S
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The source and destination vector register. Can be Z.s or Z.h. Pg The governing predicate register, P (Predicate). Zn The second source vector register. Can be Z.d or Z.s.
◆ INSTR_CREATE_fcvtnu_scalar
| #define INSTR_CREATE_fcvtnu_scalar | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src(dc, OP_fcvtnu, Rd, Rm) |
Creates an FCVTNU floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd Floating-point or integer output register. Rm Floating-point input register.
◆ INSTR_CREATE_fcvtnu_vector
| #define INSTR_CREATE_fcvtnu_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| width | |||
| ) | instr_create_1dst_2src(dc, OP_fcvtnu, Rd, Rm, width) |
Creates an FCVTNU vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. width Immediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_fcvtps_scalar
| #define INSTR_CREATE_fcvtps_scalar | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src(dc, OP_fcvtps, Rd, Rm) |
Creates an FCVTPS floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd Floating-point or integer output register. Rm Floating-point input register.
◆ INSTR_CREATE_fcvtps_vector
| #define INSTR_CREATE_fcvtps_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| width | |||
| ) | instr_create_1dst_2src(dc, OP_fcvtps, Rd, Rm, width) |
Creates an FCVTPS vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. width Immediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_fcvtpu_scalar
| #define INSTR_CREATE_fcvtpu_scalar | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src(dc, OP_fcvtpu, Rd, Rm) |
Creates an FCVTPU floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd Floating-point or integer output register. Rm Floating-point input register.
◆ INSTR_CREATE_fcvtpu_vector
| #define INSTR_CREATE_fcvtpu_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| width | |||
| ) | instr_create_1dst_2src(dc, OP_fcvtpu, Rd, Rm, width) |
Creates an FCVTPU vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. width Immediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_fcvtx_sve_pred
| #define INSTR_CREATE_fcvtx_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvtx, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a FCVTX instruction.
This macro is used to encode the forms:
FCVTX <Zd>.S, <Pg>/M, <Zn>.D
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z.s. Pg The governing predicate register, P (Predicate). Zn The source vector register, Z.d.
◆ INSTR_CREATE_fcvtxnt_sve_pred
| #define INSTR_CREATE_fcvtxnt_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fcvtxnt, Zd, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a FCVTXNT instruction.
This macro is used to encode the forms:
FCVTXNT <Zd>.S, <Pg>/M, <Zn>.D
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The source and destination vector register, Z.s. Pg The governing predicate register, P (Predicate). Zn The second source vector register, Z.d.
◆ INSTR_CREATE_fcvtzs_scalar
| #define INSTR_CREATE_fcvtzs_scalar | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src(dc, OP_fcvtzs, Rd, Rm) |
Creates an FCVTZS floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd Floating-point or integer output register. Rm Floating-point input register.
◆ INSTR_CREATE_fcvtzs_scalar_fixed
| #define INSTR_CREATE_fcvtzs_scalar_fixed | ( | dc, | |
| Rd, | |||
| Rm, | |||
| fbits | |||
| ) | instr_create_1dst_2src(dc, OP_fcvtzs, Rd, Rm, fbits) |
Creates an FCVTZS scalar floating-point to fixed-point convert instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd Floating-point or integer output register. Rm Floating-point input register. fbits The number of bits after the binary point in the fixed-point destination.
◆ INSTR_CREATE_fcvtzs_sve_pred
| #define INSTR_CREATE_fcvtzs_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvtzs, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a FCVTZS instruction.
This macro is used to encode the forms:
* FCVTZS <Zd>.S, <Pg>/M, <Zn>.D * FCVTZS <Zd>.D, <Pg>/M, <Zn>.D * FCVTZS <Zd>.H, <Pg>/M, <Zn>.H * FCVTZS <Zd>.S, <Pg>/M, <Zn>.H * FCVTZS <Zd>.D, <Pg>/M, <Zn>.H * FCVTZS <Zd>.S, <Pg>/M, <Zn>.S * FCVTZS <Zd>.D, <Pg>/M, <Zn>.S *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_fcvtzs_vector
| #define INSTR_CREATE_fcvtzs_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| width | |||
| ) | instr_create_1dst_2src(dc, OP_fcvtzs, Rd, Rm, width) |
Creates an FCVTZS vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. width Immediate int of the vector element width. Must be OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_fcvtzu_scalar
| #define INSTR_CREATE_fcvtzu_scalar | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src(dc, OP_fcvtzu, Rd, Rm) |
Creates an FCVTZU floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd Floating-point or integer output register. Rm Floating-point input register.
◆ INSTR_CREATE_fcvtzu_scalar_fixed
| #define INSTR_CREATE_fcvtzu_scalar_fixed | ( | dc, | |
| Rd, | |||
| Rm, | |||
| fbits | |||
| ) | instr_create_1dst_2src(dc, OP_fcvtzu, Rd, Rm, fbits) |
Creates an FCVTZU scalar floating-point to fixed-point convert instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd Floating-point or integer output register. Rm Floating-point input register. fbits The number of bits after the binary point in the fixed-point destination.
◆ INSTR_CREATE_fcvtzu_sve_pred
| #define INSTR_CREATE_fcvtzu_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvtzu, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a FCVTZU instruction.
This macro is used to encode the forms:
* FCVTZU <Zd>.S, <Pg>/M, <Zn>.D * FCVTZU <Zd>.D, <Pg>/M, <Zn>.D * FCVTZU <Zd>.H, <Pg>/M, <Zn>.H * FCVTZU <Zd>.S, <Pg>/M, <Zn>.H * FCVTZU <Zd>.D, <Pg>/M, <Zn>.H * FCVTZU <Zd>.S, <Pg>/M, <Zn>.S * FCVTZU <Zd>.D, <Pg>/M, <Zn>.S *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_fcvtzu_vector
| #define INSTR_CREATE_fcvtzu_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| width | |||
| ) | instr_create_1dst_2src(dc, OP_fcvtzu, Rd, Rm, width) |
Creates an FCVTZU vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. width Immediate int of the vector element width. Must be OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_fcvtzu_vector_fixed
| #define INSTR_CREATE_fcvtzu_vector_fixed | ( | dc, | |
| Rd, | |||
| Rm, | |||
| width, | |||
| fbits | |||
| ) | instr_create_1dst_3src(dc, OP_fcvtzu, Rd, Rm, width, fbits) |
Creates an FCVTZU vector floating-point to fixed-point convert instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The input register. width The vector element width. Use either OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE(). fbits The number of bits after the binary point in the fixed-point destination element.
◆ INSTR_CREATE_fdiv_scalar
| #define INSTR_CREATE_fdiv_scalar | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_fdiv, Rd, Rm, Rn) |
Creates a FDIV floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register.
◆ INSTR_CREATE_fdiv_sve
| #define INSTR_CREATE_fdiv_sve | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fdiv, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a FDIV instruction.
This macro is used to encode the forms:
* FDIV <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_fdiv_vector
| #define INSTR_CREATE_fdiv_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_fdiv, Rd, Rm, Rn, width) |
Creates a FDIV vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_fdivr_sve
| #define INSTR_CREATE_fdivr_sve | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fdivr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a FDIVR instruction.
This macro is used to encode the forms:
* FDIVR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_fdup_sve
| #define INSTR_CREATE_fdup_sve | ( | dc, | |
| Zd, | |||
| imm | |||
| ) | instr_create_1dst_1src(dc, OP_fdup, Zd, imm) |
Creates a FDUP instruction.
This macro is used to encode the forms:
* FDUP <Zd>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). imm The floating-point immediate value to be copied.
◆ INSTR_CREATE_fexpa_sve
| #define INSTR_CREATE_fexpa_sve | ( | dc, | |
| Zd, | |||
| Zn | |||
| ) | instr_create_1dst_1src(dc, OP_fexpa, Zd, Zn) |
Creates a FEXPA instruction.
This macro is used to encode the forms:
* FEXPA <Zd>.<Ts>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable) Zn The source vector register, Z (Scalable)
◆ INSTR_CREATE_fjcvtzs
| #define INSTR_CREATE_fjcvtzs | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_fjcvtzs, Rd, Rn) |
Creates a FJCVTZS instruction.
This macro is used to encode the forms:
* FJCVTZS <Wd>, <Dn> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register, W (Word, 32 bits). Rn The source register, D (doubleword, 64 bits).
◆ INSTR_CREATE_flogb_sve_pred
| #define INSTR_CREATE_flogb_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_flogb, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a FLOGB instruction.
This macro is used to encode the forms:
FLOGB <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zn The source vector register. Can be Z.h, Z.s or Z.d.
◆ INSTR_CREATE_fmad_sve
| #define INSTR_CREATE_fmad_sve | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm, | |||
| Za | |||
| ) | INSTR_PRED(instr_create_1dst_4src(dc, OP_fmad, Zdn, Zdn, Pg, Zm, Za), DR_PRED_MASKED) |
Creates a FMAD instruction.
This macro is used to encode the forms:
* FMAD <Zdn>.<Ts>, <Pg>/M, <Zm>.<Ts>, <Za>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable). Za The third source vector register, Z (Scalable).
◆ INSTR_CREATE_fmadd_scalar
| #define INSTR_CREATE_fmadd_scalar | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| Ra | |||
| ) | instr_create_1dst_3src(dc, OP_fmadd, Rd, Rm, Rn, Ra) |
Creates a FMADD floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. Ra The third input register.
◆ INSTR_CREATE_fmax_scalar
| #define INSTR_CREATE_fmax_scalar | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_fmax, Rd, Rm, Rn) |
Creates a FMAX floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register.
◆ INSTR_CREATE_fmax_sve
| #define INSTR_CREATE_fmax_sve | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| imm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fmax, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
Creates a FMAX instruction.
This macro is used to encode the forms:
* FMAX <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <const> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). imm Floating point constant, either 0.0 or 1.0.
◆ INSTR_CREATE_fmax_sve_vector
| #define INSTR_CREATE_fmax_sve_vector | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fmax, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a FMAX instruction.
This macro is used to encode the forms:
* FMAX <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_fmax_vector
| #define INSTR_CREATE_fmax_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_fmax, Rd, Rm, Rn, width) |
Creates a FMAX vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_fmaxnm_scalar
| #define INSTR_CREATE_fmaxnm_scalar | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_fmaxnm, Rd, Rm, Rn) |
Creates a FMAXNM floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register.
◆ INSTR_CREATE_fmaxnm_sve
| #define INSTR_CREATE_fmaxnm_sve | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| imm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fmaxnm, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
Creates a FMAXNM instruction.
This macro is used to encode the forms:
* FMAXNM <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <const> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). imm Floating point constant, either 0.0 or 1.0.
◆ INSTR_CREATE_fmaxnm_sve_vector
| #define INSTR_CREATE_fmaxnm_sve_vector | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fmaxnm, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a FMAXNM instruction.
This macro is used to encode the forms:
* FMAXNM <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_fmaxnm_vector
| #define INSTR_CREATE_fmaxnm_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_fmaxnm, Rd, Rm, Rn, width) |
Creates a FMAXNM vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_fmaxnmp_scalar
| #define INSTR_CREATE_fmaxnmp_scalar | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rn_elsz | |||
| ) | instr_create_1dst_2src(dc, OP_fmaxnmp, Rd, Rn, Rn_elsz) |
Creates a FMAXNMP instruction.
This macro is used to encode the forms:
* FMAXNMP <Hd>, <Hn>.2H * FMAXNMP <V><d>, <Sn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits) Rn The second source vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn_elsz The element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_fmaxnmp_sve_pred
| #define INSTR_CREATE_fmaxnmp_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fmaxnmp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a FMAXNMP instruction.
This macro is used to encode the forms:
FMAXNMP <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.h, Z.s or Z.d.
◆ INSTR_CREATE_fmaxnmp_vector
| #define INSTR_CREATE_fmaxnmp_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_3src(dc, OP_fmaxnmp, Rd, Rn, Rm, Rm_elsz) |
Creates a FMAXNMP instruction.
This macro is used to encode the forms:
* FMAXNMP <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts> * FMAXNMP <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm The third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm_elsz The element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_fmaxnmv_sve_pred
| #define INSTR_CREATE_fmaxnmv_sve_pred | ( | dc, | |
| Vd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_fmaxnmv, Vd, Pg, Zn), DR_PRED_MASKED) |
Creates a FMAXNMV instruction.
This macro is used to encode the forms:
* FMAXNMV <V><d>, <Pg>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vd The destination register. Can be S (singleword, 32 bits), H (halfword, 16 bits) or D (doubleword, 64 bits). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_fmaxp_scalar
| #define INSTR_CREATE_fmaxp_scalar | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rn_elsz | |||
| ) | instr_create_1dst_2src(dc, OP_fmaxp, Rd, Rn, Rn_elsz) |
Creates a FMAXP instruction.
This macro is used to encode the forms:
* FMAXP <Hd>, <Hn>.2H * FMAXP <V><d>, <Sn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits) Rn The second source vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn_elsz The element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_fmaxp_sve_pred
| #define INSTR_CREATE_fmaxp_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fmaxp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a FMAXP instruction.
This macro is used to encode the forms:
FMAXP <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.h, Z.s or Z.d.
◆ INSTR_CREATE_fmaxp_vector
| #define INSTR_CREATE_fmaxp_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_3src(dc, OP_fmaxp, Rd, Rn, Rm, Rm_elsz) |
Creates a FMAXP instruction.
This macro is used to encode the forms:
* FMAXP <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts> * FMAXP <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm The third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm_elsz The element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_fmaxv_sve_pred
| #define INSTR_CREATE_fmaxv_sve_pred | ( | dc, | |
| Vd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_fmaxv, Vd, Pg, Zn), DR_PRED_MASKED) |
Creates a FMAXV instruction.
This macro is used to encode the forms:
* FMAXV <V><d>, <Pg>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vd The destination register. Can be S (singleword, 32 bits), H (halfword, 16 bits) or D (doubleword, 64 bits). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_fmin_scalar
| #define INSTR_CREATE_fmin_scalar | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_fmin, Rd, Rm, Rn) |
Creates a FMIN floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register.
◆ INSTR_CREATE_fmin_sve
| #define INSTR_CREATE_fmin_sve | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| imm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fmin, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
Creates a FMIN instruction.
This macro is used to encode the forms:
* FMIN <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <const> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). imm Floating point constant, either 0.0 or 1.0.
◆ INSTR_CREATE_fmin_sve_vector
| #define INSTR_CREATE_fmin_sve_vector | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fmin, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a FMIN instruction.
This macro is used to encode the forms:
* FMIN <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_fmin_vector
| #define INSTR_CREATE_fmin_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_fmin, Rd, Rm, Rn, width) |
Creates a FMIN vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_fminnm_scalar
| #define INSTR_CREATE_fminnm_scalar | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_fminnm, Rd, Rm, Rn) |
Creates a FMINNM floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register.
◆ INSTR_CREATE_fminnm_sve
| #define INSTR_CREATE_fminnm_sve | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| imm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fminnm, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
Creates a FMINNM instruction.
This macro is used to encode the forms:
* FMINNM <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <const> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). imm Floating point constant, either 0.0 or 1.0.
◆ INSTR_CREATE_fminnm_sve_vector
| #define INSTR_CREATE_fminnm_sve_vector | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fminnm, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a FMINNM instruction.
This macro is used to encode the forms:
* FMINNM <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_fminnm_vector
| #define INSTR_CREATE_fminnm_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_fminnm, Rd, Rm, Rn, width) |
Creates a FMINNM vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_fminnmp_scalar
| #define INSTR_CREATE_fminnmp_scalar | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rn_elsz | |||
| ) | instr_create_1dst_2src(dc, OP_fminnmp, Rd, Rn, Rn_elsz) |
Creates a FMINNMP instruction.
This macro is used to encode the forms:
* FMINNMP <Hd>, <Hn>.2H * FMINNMP <V><d>, <Sn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits) Rn The second source vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn_elsz The element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_fminnmp_sve_pred
| #define INSTR_CREATE_fminnmp_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fminnmp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a FMINNMP instruction.
This macro is used to encode the forms:
FMINNMP <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.h, Z.s or Z.d.
◆ INSTR_CREATE_fminnmp_vector
| #define INSTR_CREATE_fminnmp_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_3src(dc, OP_fminnmp, Rd, Rn, Rm, Rm_elsz) |
Creates a FMINNMP instruction.
This macro is used to encode the forms:
* FMINNMP <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts> * FMINNMP <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm The third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm_elsz The element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_fminnmv_sve_pred
| #define INSTR_CREATE_fminnmv_sve_pred | ( | dc, | |
| Vd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_fminnmv, Vd, Pg, Zn), DR_PRED_MASKED) |
Creates a FMINNMV instruction.
This macro is used to encode the forms:
* FMINNMV <V><d>, <Pg>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vd The destination register. Can be S (singleword, 32 bits), H (halfword, 16 bits) or D (doubleword, 64 bits). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_fminnmv_vector
| #define INSTR_CREATE_fminnmv_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rn_elsz | |||
| ) | instr_create_1dst_2src(dc, OP_fminnmv, Rd, Rn, Rn_elsz) |
Creates a FMINNMV instruction.
This macro is used to encode the forms:
* FMINNMV <Hd>, <Hn>.<Ts> * FMINNMV <Sd>, <Sn>.4S *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination register. Can be H (halfword, 16 bits) or S (singleword, 32 bits) Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn_elsz The element size for Rn. Can be OPND_CREATE_HALF() or OPND_CREATE_SINGLE()
◆ INSTR_CREATE_fminp_scalar
| #define INSTR_CREATE_fminp_scalar | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rn_elsz | |||
| ) | instr_create_1dst_2src(dc, OP_fminp, Rd, Rn, Rn_elsz) |
Creates a FMINP instruction.
This macro is used to encode the forms:
* FMINP <Hd>, <Hn>.2H * FMINP <V><d>, <Sn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits) Rn The second source vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn_elsz The element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_fminp_sve_pred
| #define INSTR_CREATE_fminp_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fminp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a FMINP instruction.
This macro is used to encode the forms:
FMINP <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.h, Z.s or Z.d.
◆ INSTR_CREATE_fminp_vector
| #define INSTR_CREATE_fminp_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_3src(dc, OP_fminp, Rd, Rn, Rm, Rm_elsz) |
Creates a FMINP instruction.
This macro is used to encode the forms:
* FMINP <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts> * FMINP <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm The third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm_elsz The element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_fminv_sve_pred
| #define INSTR_CREATE_fminv_sve_pred | ( | dc, | |
| Vd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_fminv, Vd, Pg, Zn), DR_PRED_MASKED) |
Creates a FMINV instruction.
This macro is used to encode the forms:
* FMINV <V><d>, <Pg>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vd The destination register. Can be S (singleword, 32 bits), H (halfword, 16 bits) or D (doubleword, 64 bits). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_fmla_sve_idx
| #define INSTR_CREATE_fmla_sve_idx | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| index | |||
| ) | instr_create_1dst_4src(dc, OP_fmla, Zda, Zda, Zn, Zm, index) |
Creates a FMLA instruction.
This macro is used to encode the forms:
* FMLA <Zda>.H, <Zn>.H, <Zm>.H[<index>] * FMLA <Zda>.S, <Zn>.S, <Zm>.S[<index>] * FMLA <Zda>.D, <Zn>.D, <Zm>.D[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The third source and destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable). index Second source index constant.
◆ INSTR_CREATE_fmla_sve_vector
| #define INSTR_CREATE_fmla_sve_vector | ( | dc, | |
| Zda, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_4src(dc, OP_fmla, Zda, Zda, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a FMLA instruction.
This macro is used to encode the forms:
* FMLA <Zda>.<Ts>, <Pg>/M, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The third source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_fmla_vector
| #define INSTR_CREATE_fmla_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_4src(dc, OP_fmla, Rd, Rd, Rn, Rm, Rm_elsz) |
Creates a FMLA instruction.
This macro is used to encode the forms:
* FMLA <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts> * FMLA <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm The third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm_elsz The element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_fmla_vector_idx
| #define INSTR_CREATE_fmla_vector_idx | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| index, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_5src(dc, OP_fmla, Rd, Rd, Rn, Rm, index, Rm_elsz) |
Creates a FMLA instruction.
This macro is used to encode the forms:
* FMLA <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.H[<index>] * FMLA <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Tb>[<index>] * FMLA <Hd>, <Hn>, <Hm>.H[<index>] * FMLA <V><d>, <V><n>, <Sm>.<Ts>[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm The third source vector register. Can be Q (quadword, 128 bits) index The immediate index for Rm Rm_elsz The element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_fmlal2_vector
| #define INSTR_CREATE_fmlal2_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_4src(dc, OP_fmlal2, Rd, Rd, Rn, Rm, OPND_CREATE_HALF()) |
Creates a FMLAL2 instruction.
This macro is used to encode the forms:
* FMLAL2 <Sd>.<Ts>, <Hn>.<Tb>, <Hm>.<Tb> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register, S (singleword, 32 bits) or D (doubleword, 64 bits) Rm The third source vector register, S (singleword, 32 bits) or D (doubleword, 64 bits)
◆ INSTR_CREATE_fmlal2_vector_idx
| #define INSTR_CREATE_fmlal2_vector_idx | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| index | |||
| ) | instr_create_1dst_5src(dc, OP_fmlal2, Rd, Rd, Rn, Rm, index, OPND_CREATE_HALF()) |
Creates a FMLAL2 instruction.
This macro is used to encode the forms:
* FMLAL2 <Sd>.<Ts>, <Hn>.<Tb>, <Hm>.H[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register, S (singleword, 32 bits) or D (doubleword, 64 bits) Rm The third source vector register, Q (quadword, 128 bits) index The immediate index for Rm
◆ INSTR_CREATE_fmlal_vector
| #define INSTR_CREATE_fmlal_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_4src(dc, OP_fmlal, Rd, Rd, Rn, Rm, OPND_CREATE_HALF()) |
Creates a FMLAL instruction.
This macro is used to encode the forms:
* FMLAL <Sd>.<Ts>, <Hn>.<Tb>, <Hm>.<Tb> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register, S (singleword, 32 bits) or D (doubleword, 64 bits) Rm The third source vector register, S (singleword, 32 bits) or D (doubleword, 64 bits)
◆ INSTR_CREATE_fmlal_vector_idx
| #define INSTR_CREATE_fmlal_vector_idx | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| index | |||
| ) | instr_create_1dst_5src(dc, OP_fmlal, Rd, Rd, Rn, Rm, index, OPND_CREATE_HALF()) |
Creates a FMLAL instruction.
This macro is used to encode the forms:
* FMLAL <Sd>.<Ts>, <Hn>.<Tb>, <Hm>.H[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register, S (singleword, 32 bits) or D (doubleword, 64 bits) Rm The third source vector register, Q (quadword, 128 bits) index The immediate index for Rm
◆ INSTR_CREATE_fmlalb_sve
| #define INSTR_CREATE_fmlalb_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_fmlalb, Zda, Zda, Zn, Zm) |
Creates a FMLALB instruction.
This macro is used to encode the forms:
* FMLALB <Zda>.S, <Zn>.H, <Zm>.H *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_fmlalt_sve
| #define INSTR_CREATE_fmlalt_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_fmlalt, Zda, Zda, Zn, Zm) |
Creates a FMLALT instruction.
This macro is used to encode the forms:
* FMLALT <Zda>.S, <Zn>.H, <Zm>.H *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_fmlalt_sve_idx
| #define INSTR_CREATE_fmlalt_sve_idx | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| i3 | |||
| ) | instr_create_1dst_4src(dc, OP_fmlalt, Zda, Zda, Zn, Zm, i3) |
Creates a FMLALT instruction.
This macro is used to encode the forms:
FMLALT <Zda>.S, <Zn>.H, <Zm>.H[<index>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z.s. Zn The second source vector register, Z.h. Zm The third source vector register, Z.h. i3 The immediate index for Zm.
◆ INSTR_CREATE_fmls_sve_idx
| #define INSTR_CREATE_fmls_sve_idx | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| index | |||
| ) | instr_create_1dst_4src(dc, OP_fmls, Zda, Zda, Zn, Zm, index) |
Creates a FMLS instruction.
This macro is used to encode the forms:
* FMLS <Zda>.H, <Zn>.H, <Zm>.H[<index>] * FMLS <Zda>.S, <Zn>.S, <Zm>.S[<index>] * FMLS <Zda>.D, <Zn>.D, <Zm>.D[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The third source and destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable). index Second source index constant.
◆ INSTR_CREATE_fmls_sve_vector
| #define INSTR_CREATE_fmls_sve_vector | ( | dc, | |
| Zda, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_4src(dc, OP_fmls, Zda, Zda, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a FMLS instruction.
This macro is used to encode the forms:
* FMLS <Zda>.<Ts>, <Pg>/M, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The third source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_fmls_vector
| #define INSTR_CREATE_fmls_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_4src(dc, OP_fmls, Rd, Rd, Rn, Rm, Rm_elsz) |
Creates a FMLS instruction.
This macro is used to encode the forms:
* FMLS <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts> * FMLS <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm The third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm_elsz The element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_fmls_vector_idx
| #define INSTR_CREATE_fmls_vector_idx | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| index, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_5src(dc, OP_fmls, Rd, Rd, Rn, Rm, index, Rm_elsz) |
Creates a FMLS instruction.
This macro is used to encode the forms:
* FMLS <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.H[<index>] * FMLS <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Tb>[<index>] * FMLS <Hd>, <Hn>, <Hm>.H[<index>] * FMLS <V><d>, <V><n>, <Sm>.<Ts>[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm The third source vector register. Can be Q (quadword, 128 bits) index The immediate index for Rm Rm_elsz The element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_fmlsl2_vector
| #define INSTR_CREATE_fmlsl2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_4src(dc, OP_fmlsl2, Rd, Rd, Rm, Rn, OPND_CREATE_HALF()) |
Creates a FMLSL2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. The instruction also reads this register. Rm The first input register. Rn The second input register.
◆ INSTR_CREATE_fmlsl2_vector_idx
| #define INSTR_CREATE_fmlsl2_vector_idx | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| index | |||
| ) | instr_create_1dst_5src(dc, OP_fmlsl2, Rd, Rd, Rm, Rn, index, OPND_CREATE_HALF()) |
Creates a FMLSL2 indexed vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. The instruction also reads this register. Rm The first input register. Rn The second input register. index The first input register's vector element index.
◆ INSTR_CREATE_fmlsl_vector
| #define INSTR_CREATE_fmlsl_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_4src(dc, OP_fmlsl, Rd, Rd, Rm, Rn, OPND_CREATE_HALF()) |
Creates a FMLSL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. The instruction also reads this register. Rm The first input register. Rn The second input register.
◆ INSTR_CREATE_fmlsl_vector_idx
| #define INSTR_CREATE_fmlsl_vector_idx | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| index | |||
| ) | instr_create_1dst_5src(dc, OP_fmlsl, Rd, Rd, Rm, Rn, index, OPND_CREATE_HALF()) |
Creates a FMLSL indexed vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. The instruction also reads this register. Rm The first input register. Rn The second input register. index The first input register's vector element index.
◆ INSTR_CREATE_fmlslb_sve
| #define INSTR_CREATE_fmlslb_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_fmlslb, Zda, Zda, Zn, Zm) |
Creates a FMLSLB instruction.
This macro is used to encode the forms:
* FMLSLB <Zda>.S, <Zn>.H, <Zm>.H *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_fmlslb_sve_idx
| #define INSTR_CREATE_fmlslb_sve_idx | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| i3 | |||
| ) | instr_create_1dst_4src(dc, OP_fmlslb, Zda, Zda, Zn, Zm, i3) |
Creates a FMLSLB instruction.
This macro is used to encode the forms:
FMLSLB <Zda>.S, <Zn>.H, <Zm>.H[<index>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z.s. Zn The second source vector register, Z.h. Zm The third source vector register, Z.h. i3 The immediate index for Zm.
◆ INSTR_CREATE_fmlslt_sve
| #define INSTR_CREATE_fmlslt_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_fmlslt, Zda, Zda, Zn, Zm) |
Creates a FMLSLT instruction.
This macro is used to encode the forms:
* FMLSLT <Zda>.S, <Zn>.H, <Zm>.H *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_fmlslt_sve_idx
| #define INSTR_CREATE_fmlslt_sve_idx | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| i3 | |||
| ) | instr_create_1dst_4src(dc, OP_fmlslt, Zda, Zda, Zn, Zm, i3) |
Creates a FMLSLT instruction.
This macro is used to encode the forms:
FMLSLT <Zda>.S, <Zn>.H, <Zm>.H[<index>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z.s. Zn The second source vector register, Z.h. Zm The third source vector register, Z.h. i3 The immediate index for Zm.
◆ INSTR_CREATE_fmov_general
| #define INSTR_CREATE_fmov_general | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_fmov, Rd, Rn) |
disabled_until_i4106_is_fixed Creates an FMOV instruction to move between GPRs and floating point registers. This macro is used to encode the forms:
* FMOV <Wd>, <Hn> * FMOV <Wd>, <Sn> * FMOV <Xd>, <Dn> * FMOV <Xd>, <Hn> * FMOV <Dd>, <Xn> * FMOV <Hd>, <Wn> * FMOV <Hd>, <Xn> * FMOV <Sd>, <Wn> * FMOV <Dd>, <Dn> * FMOV <Hd>, <Hn> * FMOV <Sd>, <Sn> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rn The first input register.
◆ INSTR_CREATE_fmov_scalar
| #define INSTR_CREATE_fmov_scalar | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src(dc, OP_fmov, Rd, Rm) |
Creates an FMOV floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register.
◆ INSTR_CREATE_fmov_scalar_imm
| #define INSTR_CREATE_fmov_scalar_imm | ( | dc, | |
| Rd, | |||
| f | |||
| ) | instr_create_1dst_1src(dc, OP_fmov, Rd, f) |
Creates an FMOV immediate to scalar floating point move instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output scalar register. f The source immediate floating point opnd.
◆ INSTR_CREATE_fmov_upper_vec
| #define INSTR_CREATE_fmov_upper_vec | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) |
Value:
Creates an FMOV instruction to move between GPRs and floating point registers.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rn The first input vector register.
◆ INSTR_CREATE_fmov_vector_imm
| #define INSTR_CREATE_fmov_vector_imm | ( | dc, | |
| Rd, | |||
| f, | |||
| width | |||
| ) | instr_create_1dst_2src(dc, OP_fmov, Rd, f, width) |
Creates an FMOV immediate to vector floating point move instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output vector register. f The source immediate floating point opnd. width The output vector element width. Use either OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_fmsb_sve
| #define INSTR_CREATE_fmsb_sve | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm, | |||
| Za | |||
| ) | INSTR_PRED(instr_create_1dst_4src(dc, OP_fmsb, Zdn, Zdn, Pg, Zm, Za), DR_PRED_MASKED) |
Creates a FMSB instruction.
This macro is used to encode the forms:
* FMSB <Zdn>.<Ts>, <Pg>/M, <Zm>.<Ts>, <Za>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable). Za The third source vector register, Z (Scalable).
◆ INSTR_CREATE_fmsub_scalar
| #define INSTR_CREATE_fmsub_scalar | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| Ra | |||
| ) | instr_create_1dst_3src(dc, OP_fmsub, Rd, Rm, Rn, Ra) |
Creates a FMSUB floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. Ra The third input register.
◆ INSTR_CREATE_fmul_scalar
| #define INSTR_CREATE_fmul_scalar | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_fmul, Rd, Rm, Rn) |
Creates a FMUL floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register.
◆ INSTR_CREATE_fmul_sve
| #define INSTR_CREATE_fmul_sve | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| imm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fmul, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
Creates a FMUL instruction.
This macro is used to encode the forms:
* FMUL <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). imm Floating point constant, either 0.5 or 2.0.
◆ INSTR_CREATE_fmul_sve_idx
| #define INSTR_CREATE_fmul_sve_idx | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm, | |||
| index | |||
| ) | instr_create_1dst_3src(dc, OP_fmul, Zd, Zn, Zm, index) |
Creates a FMUL instruction.
This macro is used to encode the forms:
* FMUL <Zd>.H, <Zn>.H, <Zm>.H[<index>] * FMUL <Zd>.S, <Zn>.S, <Zm>.S[<index>] * FMUL <Zd>.D, <Zn>.D, <Zm>.D[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable). index Second source index constant.
◆ INSTR_CREATE_fmul_sve_pred_vector
| #define INSTR_CREATE_fmul_sve_pred_vector | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fmul, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a FMUL instruction.
This macro is used to encode the forms:
* FMUL <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_fmul_sve_vector
| #define INSTR_CREATE_fmul_sve_vector | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_fmul, Zd, Zn, Zm) |
Creates a FMUL instruction.
This macro is used to encode the forms:
* FMUL <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_fmul_vector
| #define INSTR_CREATE_fmul_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_fmul, Rd, Rm, Rn, width) |
Creates a FMUL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_fmulx
| #define INSTR_CREATE_fmulx | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_fmulx, Rd, Rn, Rm) |
Creates a FMULX instruction.
This macro is used to encode the forms:
* FMULX <Hd>, <Hn>, <Hm> * FMULX <V><d>, <V><n>, <V><m> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits) Rn The second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits) Rm The third source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
◆ INSTR_CREATE_fmulx_sve
| #define INSTR_CREATE_fmulx_sve | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fmulx, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a FMULX instruction.
This macro is used to encode the forms:
* FMULX <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_fmulx_vector
| #define INSTR_CREATE_fmulx_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_3src(dc, OP_fmulx, Rd, Rn, Rm, Rm_elsz) |
Creates a FMULX instruction.
This macro is used to encode the forms:
* FMULX <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts> * FMULX <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm The third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm_elsz The element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_fmulx_vector_idx
| #define INSTR_CREATE_fmulx_vector_idx | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| index, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_4src(dc, OP_fmulx, Rd, Rn, Rm, index, Rm_elsz) |
Creates a FMULX instruction.
This macro is used to encode the forms:
* FMULX <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.H[<index>] * FMULX <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Tb>[<index>] * FMULX <Hd>, <Hn>, <Hm>.H[<index>] * FMULX <V><d>, <V><n>, <Sm>.<Ts>[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register. Can be S (singleword, 32 bits), D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm The third source vector register, Q (quadword, 128 bits) index The immediate index for Rm Rm_elsz The element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_fneg_scalar
| #define INSTR_CREATE_fneg_scalar | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src(dc, OP_fneg, Rd, Rm) |
Creates a FNEG floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register.
◆ INSTR_CREATE_fneg_sve
| #define INSTR_CREATE_fneg_sve | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_fneg, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a FNEG instruction.
This macro is used to encode the forms:
* FNEG <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_fnmad_sve
| #define INSTR_CREATE_fnmad_sve | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm, | |||
| Za | |||
| ) | INSTR_PRED(instr_create_1dst_4src(dc, OP_fnmad, Zdn, Zdn, Pg, Zm, Za), DR_PRED_MASKED) |
Creates a FNMAD instruction.
This macro is used to encode the forms:
* FNMAD <Zdn>.<Ts>, <Pg>/M, <Zm>.<Ts>, <Za>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable). Za The third source vector register, Z (Scalable).
◆ INSTR_CREATE_fnmadd_scalar
| #define INSTR_CREATE_fnmadd_scalar | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| Ra | |||
| ) | instr_create_1dst_3src(dc, OP_fnmadd, Rd, Rm, Rn, Ra) |
Creates a FNMADD floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. Ra The third input register.
◆ INSTR_CREATE_fnmla_sve
| #define INSTR_CREATE_fnmla_sve | ( | dc, | |
| Zda, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_4src(dc, OP_fnmla, Zda, Zda, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a FNMLA instruction.
This macro is used to encode the forms:
* FNMLA <Zda>.<Ts>, <Pg>/M, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_fnmls_sve
| #define INSTR_CREATE_fnmls_sve | ( | dc, | |
| Zda, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_4src(dc, OP_fnmls, Zda, Zda, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a FNMLS instruction.
This macro is used to encode the forms:
* FNMLS <Zda>.<Ts>, <Pg>/M, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_fnmsb_sve_pred
| #define INSTR_CREATE_fnmsb_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm, | |||
| Za | |||
| ) | INSTR_PRED(instr_create_1dst_4src(dc, OP_fnmsb, Zdn, Zdn, Pg, Zm, Za), DR_PRED_MASKED) |
Creates a FNMSB instruction.
This macro is used to encode the forms:
* FNMSB <Zdn>.<Ts>, <Pg>/M, <Zm>.<Ts>, <Za>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable). Za The third source vector register, Z (Scalable).
◆ INSTR_CREATE_fnmsub_scalar
| #define INSTR_CREATE_fnmsub_scalar | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| Ra | |||
| ) | instr_create_1dst_3src(dc, OP_fnmsub, Rd, Rm, Rn, Ra) |
Creates a FNMSUB floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. Ra The third input register.
◆ INSTR_CREATE_fnmul_scalar
| #define INSTR_CREATE_fnmul_scalar | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_fnmul, Rd, Rm, Rn) |
Creates a FNMUL floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register.
◆ INSTR_CREATE_frecpe
| #define INSTR_CREATE_frecpe | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_frecpe, Rd, Rn) |
Creates a FRECPE instruction.
This macro is used to encode the forms:
* FRECPE <Hd>, <Hn> * FRECPE <V><d>, <V><n> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits) Rn The second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
◆ INSTR_CREATE_frecpe_sve
| #define INSTR_CREATE_frecpe_sve | ( | dc, | |
| Zd, | |||
| Zn | |||
| ) | instr_create_1dst_1src(dc, OP_frecpe, Zd, Zn) |
Creates a FRECPE instruction.
This macro is used to encode the forms:
* FRECPE <Zd>.<Ts>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_frecpe_vector
| #define INSTR_CREATE_frecpe_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rn_elsz | |||
| ) | instr_create_1dst_2src(dc, OP_frecpe, Rd, Rn, Rn_elsz) |
Creates a FRECPE instruction.
This macro is used to encode the forms:
* FRECPE <Hd>.<Ts>, <Hn>.<Ts> * FRECPE <Dd>.<Ts>, <Dn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn_elsz The element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_frecps
| #define INSTR_CREATE_frecps | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_frecps, Rd, Rn, Rm) |
Creates a FRECPS instruction.
This macro is used to encode the forms:
* FRECPS <Hd>, <Hn>, <Hm> * FRECPS <V><d>, <V><n>, <V><m> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits) Rn The second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits) Rm The third source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
◆ INSTR_CREATE_frecps_sve
| #define INSTR_CREATE_frecps_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_frecps, Zd, Zn, Zm) |
Creates a FRECPS instruction.
This macro is used to encode the forms:
* FRECPS <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_frecps_vector
| #define INSTR_CREATE_frecps_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_3src(dc, OP_frecps, Rd, Rn, Rm, Rm_elsz) |
Creates a FRECPS instruction.
This macro is used to encode the forms:
* FRECPS <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts> * FRECPS <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm The third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm_elsz The element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_frecpx_sve_pred
| #define INSTR_CREATE_frecpx_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_frecpx, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a FRECPX instruction.
This macro is used to encode the forms:
* FRECPX <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_frint32x
| #define INSTR_CREATE_frint32x | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_frint32x, Rd, Rn) |
Creates a FRINT32X instruction.
This macro is used to encode the forms:
FRINT32X <Dd>, <Dn> FRINT32X <Sd>, <Sn>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register. Can be D (doubleword, 64 bits) or S (singleword, 32 bits). Rn The source register. Can be D (doubleword, 64 bits) or S (singleword, 32 bits).
◆ INSTR_CREATE_frint32x_vector
| #define INSTR_CREATE_frint32x_vector | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_frint32x, Rd, Rn) |
Creates a FRINT32X instruction.
This macro is used to encode the forms:
FRINT32X <Vd>.2S, <Vn>.2S FRINT32X <Vd>.4S, <Vn>.4S FRINT32X <Vd>.2D, <Vn>.2D
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits). Rn The source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits).
◆ INSTR_CREATE_frint32z
| #define INSTR_CREATE_frint32z | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_frint32z, Rd, Rn) |
Creates a FRINT32Z instruction.
This macro is used to encode the forms:
FRINT32Z <Dd>, <Dn> FRINT32Z <Sd>, <Sn>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register. Can be D (doubleword, 64 bits) or S (singleword, 32 bits). Rn The source register. Can be D (doubleword, 64 bits) or S (singleword, 32 bits).
◆ INSTR_CREATE_frint32z_vector
| #define INSTR_CREATE_frint32z_vector | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_frint32z, Rd, Rn) |
Creates a FRINT32Z instruction.
This macro is used to encode the forms:
FRINT32Z <Vd>.2S, <Vn>.2S FRINT32Z <Vd>.4S, <Vn>.4S FRINT32Z <Vd>.2D, <Vn>.2D
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits). Rn The source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits).
◆ INSTR_CREATE_frint64x
| #define INSTR_CREATE_frint64x | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_frint64x, Rd, Rn) |
Creates a FRINT64X instruction.
This macro is used to encode the forms:
FRINT64X <Dd>, <Dn> FRINT64X <Sd>, <Sn>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register. Can be D (doubleword, 64 bits) or S (singleword, 32 bits). Rn The source register. Can be D (doubleword, 64 bits) or S (singleword, 32 bits).
◆ INSTR_CREATE_frint64x_vector
| #define INSTR_CREATE_frint64x_vector | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_frint64x, Rd, Rn) |
Creates a FRINT64X instruction.
This macro is used to encode the forms:
FRINT64X <Vd>.2S, <Vn>.2S FRINT64X <Vd>.4S, <Vn>.4S FRINT64X <Vd>.2D, <Vn>.2D
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits). Rn The source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits).
◆ INSTR_CREATE_frint64z
| #define INSTR_CREATE_frint64z | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_frint64z, Rd, Rn) |
Creates a FRINT64Z instruction.
This macro is used to encode the forms:
FRINT64Z <Dd>, <Dn> FRINT64Z <Sd>, <Sn>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register. Can be D (doubleword, 64 bits) or S (singleword, 32 bits). Rn The source register. Can be D (doubleword, 64 bits) or S (singleword, 32 bits).
◆ INSTR_CREATE_frint64z_vector
| #define INSTR_CREATE_frint64z_vector | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_frint64z, Rd, Rn) |
Creates a FRINT64Z instruction.
This macro is used to encode the forms:
FRINT64Z <Vd>.2S, <Vn>.2S FRINT64Z <Vd>.4S, <Vn>.4S FRINT64Z <Vd>.2D, <Vn>.2D
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits). Rn The source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits).
◆ INSTR_CREATE_frinta_scalar
| #define INSTR_CREATE_frinta_scalar | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src(dc, OP_frinta, Rd, Rm) |
Creates a FRINTA floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register.
◆ INSTR_CREATE_frinta_sve_pred
| #define INSTR_CREATE_frinta_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_frinta, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a FRINTA instruction.
This macro is used to encode the forms:
* FRINTA <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_frinta_vector
| #define INSTR_CREATE_frinta_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| width | |||
| ) | instr_create_1dst_2src(dc, OP_frinta, Rd, Rm, width) |
Creates a FRINTA vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The input vector register. width Immediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_frinti_scalar
| #define INSTR_CREATE_frinti_scalar | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src(dc, OP_frinti, Rd, Rm) |
Creates a FRINTI floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register.
◆ INSTR_CREATE_frinti_sve_pred
| #define INSTR_CREATE_frinti_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_frinti, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a FRINTI instruction.
This macro is used to encode the forms:
* FRINTI <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_frinti_vector
| #define INSTR_CREATE_frinti_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| width | |||
| ) | instr_create_1dst_2src(dc, OP_frinti, Rd, Rm, width) |
Creates a FRINTI vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The input vector register. width Immediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_frintm_scalar
| #define INSTR_CREATE_frintm_scalar | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src(dc, OP_frintm, Rd, Rm) |
Creates a FRINTM floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register.
◆ INSTR_CREATE_frintm_sve_pred
| #define INSTR_CREATE_frintm_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_frintm, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a FRINTM instruction.
This macro is used to encode the forms:
* FRINTM <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_frintm_vector
| #define INSTR_CREATE_frintm_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| width | |||
| ) | instr_create_1dst_2src(dc, OP_frintm, Rd, Rm, width) |
Creates a FRINTM vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The input vector register. width Immediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_frintn_scalar
| #define INSTR_CREATE_frintn_scalar | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src(dc, OP_frintn, Rd, Rm) |
Creates a FRINTN floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register.
◆ INSTR_CREATE_frintn_sve_pred
| #define INSTR_CREATE_frintn_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_frintn, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a FRINTN instruction.
This macro is used to encode the forms:
* FRINTN <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_frintn_vector
| #define INSTR_CREATE_frintn_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| width | |||
| ) | instr_create_1dst_2src(dc, OP_frintn, Rd, Rm, width) |
Creates a FRINTN vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The input vector register. width Immediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_frintp_scalar
| #define INSTR_CREATE_frintp_scalar | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src(dc, OP_frintp, Rd, Rm) |
Creates a FRINTP floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register.
◆ INSTR_CREATE_frintp_sve_pred
| #define INSTR_CREATE_frintp_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_frintp, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a FRINTP instruction.
This macro is used to encode the forms:
* FRINTP <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_frintp_vector
| #define INSTR_CREATE_frintp_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| width | |||
| ) | instr_create_1dst_2src(dc, OP_frintp, Rd, Rm, width) |
Creates a FRINTP vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The input vector register. width Immediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_frintx_scalar
| #define INSTR_CREATE_frintx_scalar | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src(dc, OP_frintx, Rd, Rm) |
Creates a FRINTX floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register.
◆ INSTR_CREATE_frintx_sve_pred
| #define INSTR_CREATE_frintx_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_frintx, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a FRINTX instruction.
This macro is used to encode the forms:
* FRINTX <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_frintx_vector
| #define INSTR_CREATE_frintx_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| width | |||
| ) | instr_create_1dst_2src(dc, OP_frintx, Rd, Rm, width) |
Creates a FRINTX vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The input vector register. width Immediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_frintz_scalar
| #define INSTR_CREATE_frintz_scalar | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src(dc, OP_frintz, Rd, Rm) |
Creates a FRINTZ floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register.
◆ INSTR_CREATE_frintz_sve_pred
| #define INSTR_CREATE_frintz_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_frintz, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a FRINTZ instruction.
This macro is used to encode the forms:
* FRINTZ <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_frintz_vector
| #define INSTR_CREATE_frintz_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| width | |||
| ) | instr_create_1dst_2src(dc, OP_frintz, Rd, Rm, width) |
Creates a FRINTZ vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The input vector register. width Immediate int of the vector element width. Must be OPND_CREATE_HALF() or OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_frsqrte
| #define INSTR_CREATE_frsqrte | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_frsqrte, Rd, Rn) |
Creates a FRSQRTE instruction.
This macro is used to encode the forms:
* FRSQRTE <Hd>, <Hn> * FRSQRTE <V><d>, <V><n> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits) Rn The second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
◆ INSTR_CREATE_frsqrte_sve
| #define INSTR_CREATE_frsqrte_sve | ( | dc, | |
| Zd, | |||
| Zn | |||
| ) | instr_create_1dst_1src(dc, OP_frsqrte, Zd, Zn) |
Creates a FRSQRTE instruction.
This macro is used to encode the forms:
* FRSQRTE <Zd>.<Ts>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_frsqrte_vector
| #define INSTR_CREATE_frsqrte_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rn_elsz | |||
| ) | instr_create_1dst_2src(dc, OP_frsqrte, Rd, Rn, Rn_elsz) |
Creates a FRSQRTE instruction.
This macro is used to encode the forms:
* FRSQRTE <Hd>.<Ts>, <Hn>.<Ts> * FRSQRTE <Dd>.<Ts>, <Dn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn_elsz The element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_frsqrts
| #define INSTR_CREATE_frsqrts | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_frsqrts, Rd, Rn, Rm) |
Creates a FRSQRTS instruction.
This macro is used to encode the forms:
* FRSQRTS <Hd>, <Hn>, <Hm> * FRSQRTS <V><d>, <V><n>, <V><m> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits) Rn The second source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits) Rm The third source register. Can be H (halfword, 16 bits), S (singleword, 32 bits) or D (doubleword, 64 bits)
◆ INSTR_CREATE_frsqrts_sve
| #define INSTR_CREATE_frsqrts_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_frsqrts, Zd, Zn, Zm) |
Creates a FRSQRTS instruction.
This macro is used to encode the forms:
* FRSQRTS <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_frsqrts_vector
| #define INSTR_CREATE_frsqrts_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_3src(dc, OP_frsqrts, Rd, Rn, Rm, Rm_elsz) |
Creates a FRSQRTS instruction.
This macro is used to encode the forms:
* FRSQRTS <Hd>.<Ts>, <Hn>.<Ts>, <Hm>.<Ts> * FRSQRTS <Dd>.<Ts>, <Dn>.<Ts>, <Dm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm The third source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm_elsz The element size for Rm. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_fscale_sve
| #define INSTR_CREATE_fscale_sve | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fscale, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a FSCALE instruction.
This macro is used to encode the forms:
* FSCALE <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_fsqrt_scalar
| #define INSTR_CREATE_fsqrt_scalar | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src(dc, OP_fsqrt, Rd, Rm) |
Creates a FSQRT floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register.
◆ INSTR_CREATE_fsqrt_sve
| #define INSTR_CREATE_fsqrt_sve | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_fsqrt, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a FSQRT instruction.
This macro is used to encode the forms:
* FSQRT <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_fsqrt_vector
| #define INSTR_CREATE_fsqrt_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rn_elsz | |||
| ) | instr_create_1dst_2src(dc, OP_fsqrt, Rd, Rn, Rn_elsz) |
Creates a FSQRT instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn_elsz The element size for Rn. Can be OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_fsub_scalar
| #define INSTR_CREATE_fsub_scalar | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_fsub, Rd, Rm, Rn) |
Creates a FSUB floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register.
◆ INSTR_CREATE_fsub_sve
| #define INSTR_CREATE_fsub_sve | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| imm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fsub, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
Creates a FSUB instruction.
This macro is used to encode the forms:
* FSUB <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). imm Floating point constant, either 0.5 or 1.0.
◆ INSTR_CREATE_fsub_sve_pred
| #define INSTR_CREATE_fsub_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fsub, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a FSUB instruction.
This macro is used to encode the forms:
* FSUB <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_fsub_sve_vector
| #define INSTR_CREATE_fsub_sve_vector | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_fsub, Zd, Zn, Zm) |
Creates a FSUB instruction.
This macro is used to encode the forms:
* FSUB <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_fsub_vector
| #define INSTR_CREATE_fsub_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_fsub, Rd, Rm, Rn, width) |
Creates a FSUB vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_fsubr_sve
| #define INSTR_CREATE_fsubr_sve | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| imm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fsubr, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
Creates a FSUBR instruction.
This macro is used to encode the forms:
* FSUBR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). imm Floating point constant, either 0.5 or 1.0.
◆ INSTR_CREATE_fsubr_sve_vector
| #define INSTR_CREATE_fsubr_sve_vector | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_fsubr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a FSUBR instruction.
This macro is used to encode the forms:
* FSUBR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_ftmad_sve
| #define INSTR_CREATE_ftmad_sve | ( | dc, | |
| Zdn, | |||
| Zm, | |||
| imm | |||
| ) | instr_create_1dst_3src(dc, OP_ftmad, Zdn, Zdn, Zm, imm) |
Creates a FTMAD instruction.
This macro is used to encode the forms:
* FTMAD <Zdn>.<Ts>, <Zdn>.<Ts>, <Zm>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable) Zm The second source vector register, Z (Scalable) imm The immediate imm
◆ INSTR_CREATE_ftsmul_sve
| #define INSTR_CREATE_ftsmul_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_ftsmul, Zd, Zn, Zm) |
Creates a FTSMUL instruction.
This macro is used to encode the forms:
* FTSMUL <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_ftssel_sve
| #define INSTR_CREATE_ftssel_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_ftssel, Zd, Zn, Zm) |
Creates a FTSSEL instruction.
This macro is used to encode the forms:
* FTSSEL <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_gmi
| #define INSTR_CREATE_gmi | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_gmi, Rd, Rn, Rm) |
Creates a GMI instruction.
This macro is used to encode the forms:
GMI <Xd>, <Xn|SP>, <Xm>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register, X (Extended, 64 bits). Rn The first source register, X (Extended, 64 bits). Rm The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_histcnt_sve_pred
| #define INSTR_CREATE_histcnt_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_histcnt, Zd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a HISTCNT instruction.
This macro is used to encode the forms:
HISTCNT <Zd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zn The first source vector register. Can be Z.s or Z.d. Zm The second source vector register. Can be Z.s or Z.d.
◆ INSTR_CREATE_histseg_sve
| #define INSTR_CREATE_histseg_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_histseg, Zd, Zn, Zm) |
Creates a HISTSEG instruction.
This macro is used to encode the forms:
* HISTSEG <Zd>.B, <Zn>.B, <Zm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_incb
| #define INSTR_CREATE_incb | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_incb, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
Creates an INCB instruction.
This macro is used to encode the forms:
* INCB <Xdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register, X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_incd
| #define INSTR_CREATE_incd | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_incd, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
Creates an INCD instruction.
This macro is used to encode the forms:
* INCD <Xdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register, X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_incd_sve
| #define INSTR_CREATE_incd_sve | ( | dc, | |
| Zdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_incd, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
Creates an INCD instruction.
This macro is used to encode the forms:
* INCD <Zdn>.D{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z (Scalable). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_inch
| #define INSTR_CREATE_inch | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_inch, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
Creates an INCH instruction.
This macro is used to encode the forms:
* INCH <Xdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register, X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_inch_sve
| #define INSTR_CREATE_inch_sve | ( | dc, | |
| Zdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_inch, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
Creates an INCH instruction.
This macro is used to encode the forms:
* INCH <Zdn>.H{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z (Scalable). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_incp_sve
| #define INSTR_CREATE_incp_sve | ( | dc, | |
| Rdn, | |||
| Pm | |||
| ) | instr_create_1dst_2src(dc, OP_incp, Rdn, Rdn, Pm) |
Creates an INCP instruction.
This macro is used to encode the forms:
* INCP <Xdn>, <Pm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register, X (Extended, 64 bits). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_incp_sve_vector
| #define INSTR_CREATE_incp_sve_vector | ( | dc, | |
| Zdn, | |||
| Pm | |||
| ) | instr_create_1dst_2src(dc, OP_incp, Zdn, Zdn, Pm) |
Creates an INCP instruction.
This macro is used to encode the forms:
* INCP <Zdn>.<Ts>, <Pm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z (Scalable). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_incw
| #define INSTR_CREATE_incw | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_incw, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
Creates an INCW instruction.
This macro is used to encode the forms:
* INCW <Xdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register, X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_incw_sve
| #define INSTR_CREATE_incw_sve | ( | dc, | |
| Zdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_incw, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
Creates an INCW instruction.
This macro is used to encode the forms:
* INCW <Zdn>.S{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z (Scalable). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_index_sve
| #define INSTR_CREATE_index_sve | ( | dc, | |
| Zd, | |||
| Rn_or_imm, | |||
| Rm_or_imm | |||
| ) | instr_create_1dst_2src(dc, OP_index, Zd, Rn_or_imm, Rm_or_imm) |
Creates an INDEX instruction.
This macro is used to encode the forms:
* INDEX <Zd>.<Ts>, #<imm1>, #<imm2> * INDEX <Zd>.<Ts>, #<imm>, <R><m> * INDEX <Zd>.<Ts>, <R><n>, #<imm> * INDEX <Zd>.<Ts>, <R><n>, <R><m> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Rn_or_imm The first source operand. Can be W (Word, 32 bits) or X (Extended, 64 bits) register or a 5-bit signed immediate in the range -16 to 15. Rm_or_imm The second source operand. Can be W (Word, 32 bits) or X (Extended, 64 bits) register or a 5-bit signed immediate in the range -16 to 15.
◆ INSTR_CREATE_insr_sve_scalar
| #define INSTR_CREATE_insr_sve_scalar | ( | dc, | |
| Zd, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_insr, Zd, Zd, Rm) |
Creates a INSR instruction.
This macro is used to encode the forms:
* INSR <Zdn>.<T>, <R><m> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The second source and destination vector register, Z (Scalable). Rm The source vector register. Can be X (Extended, 64 bits) or W (Word, 32 bits).
◆ INSTR_CREATE_insr_sve_simd_fp
| #define INSTR_CREATE_insr_sve_simd_fp | ( | dc, | |
| Zdn, | |||
| Vm | |||
| ) | instr_create_1dst_2src(dc, OP_insr, Zdn, Zdn, Vm) |
Creates an INSR instruction.
This macro is used to encode the forms:
* INSR <Zdn>.<Ts>, <V><m> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The second source and destination vector register, Z (Scalable). Vm The first source register. Can be S (singleword, 32 bits), B (byte, 8 bits), D (doubleword, 64 bits) or H (halfword, 16 bits).
◆ INSTR_CREATE_irg
| #define INSTR_CREATE_irg | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_irg, Rd, Rn, Rm) |
Creates an IRG instruction.
This macro is used to encode the forms:
IRG <Xd|SP>, <Xn|SP>{, <Xm>}
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register, X (Extended, 64 bits). Rn The first source register, X (Extended, 64 bits). Rm The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_lasta_sve_scalar
| #define INSTR_CREATE_lasta_sve_scalar | ( | dc, | |
| Rd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_lasta, Rd, Pg, Zn), DR_PRED_MASKED) |
Creates a LASTA instruction.
This macro is used to encode the forms:
* LASTA <R><d>, <Pg>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination vector register. Can be W (Word, 32 bits) or X (Extended, 64 bits). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_lasta_sve_simd_fp
| #define INSTR_CREATE_lasta_sve_simd_fp | ( | dc, | |
| Vd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_lasta, Vd, Pg, Zn), DR_PRED_MASKED) |
Creates a LASTA instruction.
This macro is used to encode the forms:
* LASTA <V><d>, <Pg>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vd The destination register. Can be D (doubleword, 64 bits), B (byte, 8 bits), S (singleword, 32 bits) or H (halfword, 16 bits). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_lastb_sve_scalar
| #define INSTR_CREATE_lastb_sve_scalar | ( | dc, | |
| Rd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_lastb, Rd, Pg, Zn), DR_PRED_MASKED) |
Creates a LASTB instruction.
This macro is used to encode the forms:
* LASTB <R><d>, <Pg>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination vector register. Can be W (Word, 32 bits) or X (Extended, 64 bits). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_lastb_sve_simd_fp
| #define INSTR_CREATE_lastb_sve_simd_fp | ( | dc, | |
| Vd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_lastb, Vd, Pg, Zn), DR_PRED_MASKED) |
Creates a LASTB instruction.
This macro is used to encode the forms:
* LASTB <V><d>, <Pg>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vd The destination register. Can be D (doubleword, 64 bits), B (byte, 8 bits), S (singleword, 32 bits) or H (halfword, 16 bits). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_ld1_multi_1
| #define INSTR_CREATE_ld1_multi_1 | ( | dc, | |
| q, | |||
| r, | |||
| s | |||
| ) | instr_create_1dst_2src(dc, OP_ld1, q, r, s) |
Creates an Advanced SIMD (NEON) LD1 instruction to load multiple single element structures to one vector register, e.g. LD1 {V0.4H},[X0].
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. q The destination vector register operand. r The source memory operand. s The size of the vector element.
◆ INSTR_CREATE_ld1b_sve_pred
| #define INSTR_CREATE_ld1b_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1b, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LD1B instruction.
This macro is used to encode the forms:
* LD1B { <Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>]
* LD1B { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>]
* LD1B { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>]
* LD1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>, <Xm>]
* LD1B { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* LD1B { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* LD1B { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* LD1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* LD1B { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
* LD1B { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
* LD1B { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
* LD1B { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend>]
* LD1B { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend>]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>] variant: opnd_create_base_disp_aarch64(Rn, Rm, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_1) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, byte_disp, OPSZ_1) For the [<Zn>.S{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_4, DR_EXTEND_UXTX, 0, imm, 0, OPSZ_1, 0) For the [<Zn>.D{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_8, DR_EXTEND_UXTX, 0, imm, 0, OPSZ_1, 0) For the [<Xn|SP>, <Zm>.D] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_1, 0) For the [<Xn|SP>, <Zm>.D, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, 0, 0, OPSZ_1, 0) For the [<Xn|SP>, <Zm>.S, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_4, extend, 0, 0, OPSZ_1, 0)
◆ INSTR_CREATE_ld1d_sve_pred
| #define INSTR_CREATE_ld1d_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1d, Zt, Zn, Pg), DR_PRED_MASKED) |
Creates a LD1D instruction.
This macro is used to encode the forms:
* LD1D { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
* LD1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #3]
* LD1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
* LD1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend> #3]
* LD1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend>]
* LD1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
* LD1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The first source vector base register with an immediate offset, constructed with the function: For the [<Zn>.D{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_8, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_8, 0) For the [<Xn|SP>, <Zm>.D, LSL #3] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, true, 0, OPSZ_8, 3) For the [<Xn|SP>, <Zm>.D] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_8, 0) For the [<Xn|SP>, <Zm>.D, <extend> #3] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, true, 0, OPSZ_8, 3) For the [<Xn|SP>, <Zm>.D, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, 0, 0, OPSZ_8, 0) For the variant <Xn|SP>, <Xm>, LSL #3]: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_8, 3) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_8)
◆ INSTR_CREATE_ld1h_sve_pred
| #define INSTR_CREATE_ld1h_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1h, Zt, Zn, Pg), DR_PRED_MASKED) |
Creates a LD1H instruction.
This macro is used to encode the forms:
* LD1H { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
* LD1H { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
* LD1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #1]
* LD1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
* LD1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend> #1]
* LD1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend>]
* LD1H { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend> #1]
* LD1H { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend>]
* LD1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
* LD1H { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
* LD1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
* LD1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* LD1H { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* LD1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The first source vector base register with an immediate offset, constructed with the function: For the [<Zn>.S{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_4, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_2, 0) For the [<Zn>.D{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_8, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_2, 0) For the [<Xn|SP>, <Zm>.D, LSL #1] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, true, 0, OPSZ_2, 1) For the [<Xn|SP>, <Zm>.D] variant: opnd_create_vector_base_disp_aarch64(Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_2, 0) For the [<Xn|SP>, <Zm>.D, <extend> #1] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, true, 0, OPSZ_2, 1) For the [<Xn|SP>, <Zm>.D, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, 0, 0, OPSZ_2, 0) For the [<Xn|SP>, <Zm>.S, <extend> #1] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_4, extend, true, 0, OPSZ_2, 1) For the [<Xn|SP>, <Zm>.S, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_4, extend, 0, 0, OPSZ_2, 0) For the [<Xn|SP>, <Xm>, LSL #1] variants: opnd_create_base_disp_shift_aarch64( Xn, Xm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_2, 1) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_2)
◆ INSTR_CREATE_ld1rb_sve
| #define INSTR_CREATE_ld1rb_sve | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rb, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LD1RB instruction.
This macro is used to encode the forms:
* LD1RB { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<pimm>}]
* LD1RB { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<pimm>}]
* LD1RB { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<pimm>}]
* LD1RB { <Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<pimm>}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with an immediate offset, constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm6, OPSZ_1)
◆ INSTR_CREATE_ld1rd_sve
| #define INSTR_CREATE_ld1rd_sve | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rd, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LD1RD instruction.
This macro is used to encode the forms:
* LD1RD { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<pimm>}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with an immediate offset, constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm6, OPSZ_8)
◆ INSTR_CREATE_ld1rh_sve
| #define INSTR_CREATE_ld1rh_sve | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rh, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LD1RH instruction.
This macro is used to encode the forms:
* LD1RH { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<pimm>}]
* LD1RH { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<pimm>}]
* LD1RH { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<pimm>}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with an immediate offset, constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm6, OPSZ_2)
◆ INSTR_CREATE_ld1rob_sve_pred
| #define INSTR_CREATE_ld1rob_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rob, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LD1ROB instruction.
This macro is used to encode the forms:
* LD1ROB { <Zt>.B }, <Pg>/Z, [<Xn|SP>, <Xm>]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: opnd_create_base_disp_aarch64(Rn, Rm, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_1)
◆ INSTR_CREATE_ld1rqb_sve_pred
| #define INSTR_CREATE_ld1rqb_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rqb, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LD1RQB instruction.
This macro is used to encode the forms:
* LD1RQB { <Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
* LD1RQB { <Zt>.B }, <Pg>/Z, [<Xn|SP>, <Xm>]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>{, #<imm>}] variant: opnd_create_base_disp_aarch64( Xn, DR_REG_NULL, DR_EXTEND_UXTX, false, 0, 0, OPSZ_1) For the [<Xn|SP>, <Xm>] variant: opnd_create_base_disp_shift_aarch64( Xn, Xm, DR_EXTEND_UXTX, false, 0, 0, OPSZ_1, 0)
◆ INSTR_CREATE_ld1rqd_sve_pred
| #define INSTR_CREATE_ld1rqd_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rqd, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LD1RQD instruction.
This macro is used to encode the forms:
* LD1RQD { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
* LD1RQD { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>{, #<imm>}] variant: opnd_create_base_disp_aarch64( Xn, DR_REG_NULL, DR_EXTEND_UXTX, false, 0, 0, OPSZ_8) For the [<Xn|SP>, <Xm>, LSL #3] variant: opnd_create_base_disp_shift_aarch64( Xn, Xm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_8, 3)
◆ INSTR_CREATE_ld1rqh_sve_pred
| #define INSTR_CREATE_ld1rqh_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rqh, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LD1RQH instruction.
This macro is used to encode the forms:
* LD1RQH { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
* LD1RQH { <Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>{, #<imm>}] variant: opnd_create_base_disp_aarch64( Xn, DR_REG_NULL, DR_EXTEND_UXTX, false, 0, 0, OPSZ_2) For the [<Xn|SP>, <Xm>, LSL #1] variant: opnd_create_base_disp_shift_aarch64( Xn, Xm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_2, 2)
◆ INSTR_CREATE_ld1rqw_sve_pred
| #define INSTR_CREATE_ld1rqw_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rqw, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LD1RQW instruction.
This macro is used to encode the forms:
* LD1RQW { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
* LD1RQW { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>{, #<imm>}] variant: opnd_create_base_disp_aarch64( Xn, DR_REG_NULL, DR_EXTEND_UXTX, false, 0, 0, OPSZ_4) For the [<Xn|SP>, <Xm>, LSL #2] variant: opnd_create_base_disp_shift_aarch64( Xn, Xm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_4, 4)
◆ INSTR_CREATE_ld1rsb_sve
| #define INSTR_CREATE_ld1rsb_sve | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rsb, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LD1RSB instruction.
This macro is used to encode the forms:
* LD1RSB { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<pimm>}]
* LD1RSB { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<pimm>}]
* LD1RSB { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<pimm>}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with an immediate offset, constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm6, OPSZ_1)
◆ INSTR_CREATE_ld1rsh_sve
| #define INSTR_CREATE_ld1rsh_sve | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rsh, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LD1RSH instruction.
This macro is used to encode the forms:
* LD1RSH { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<pimm>}]
* LD1RSH { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<pimm>}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with an immediate offset, constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm6, OPSZ_2)
◆ INSTR_CREATE_ld1rsw_sve
| #define INSTR_CREATE_ld1rsw_sve | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rsw, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LD1RSW instruction.
This macro is used to encode the forms:
* LD1RSW { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<pimm>}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with an immediate offset, constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm6, OPSZ_4)
◆ INSTR_CREATE_ld1rw_sve
| #define INSTR_CREATE_ld1rw_sve | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rw, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LD1RW instruction.
This macro is used to encode the forms:
* LD1RW { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<pimm>}]
* LD1RW { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<pimm>}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with an immediate offset, constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm6, OPSZ_4)
◆ INSTR_CREATE_ld1sb_sve_pred
| #define INSTR_CREATE_ld1sb_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1sb, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LD1SB instruction.
This macro is used to encode the forms:
* LD1SB { <Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>]
* LD1SB { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>]
* LD1SB { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>]
* LD1SB { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* LD1SB { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* LD1SB { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* LD1SB { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
* LD1SB { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
* LD1SB { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
* LD1SB { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend>]
* LD1SB { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend>]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>] variant: opnd_create_base_disp_aarch64(Rn, Rm, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_1) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, byte_disp, OPSZ_1) For the [<Zn>.S{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_4, DR_EXTEND_UXTX, 0, imm, 0, OPSZ_1, 0) For the [<Zn>.D{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_8, DR_EXTEND_UXTX, 0, imm, 0, OPSZ_1, 0) For the [<Xn|SP>, <Zm>.D] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_1, 0) For the [<Xn|SP>, <Zm>.D, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, 0, 0, OPSZ_1, 0) For the [<Xn|SP>, <Zm>.S, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_4, extend, 0, 0, OPSZ_1, 0)
◆ INSTR_CREATE_ld1sh_sve_pred
| #define INSTR_CREATE_ld1sh_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1sh, Zt, Zn, Pg), DR_PRED_MASKED) |
Creates a LD1SH instruction.
This macro is used to encode the forms:
* LD1SH { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
* LD1SH { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
* LD1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #1]
* LD1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
* LD1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend> #1]
* LD1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend>]
* LD1SH { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend> #1]
* LD1SH { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend>]
* LD1SH { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
* LD1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
* LD1SH { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* LD1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The first source vector base register with an immediate offset, constructed with the function: For the [<Zn>.S{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_4, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_2, 0) For the [<Zn>.D{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_8, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_2, 0) For the [<Xn|SP>, <Zm>.D, LSL #1] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, true, 0, OPSZ_2, 1) For the [<Xn|SP>, <Zm>.D] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_2, 0) For the [<Xn|SP>, <Zm>.D, <extend> #1] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, true, 0, OPSZ_2, 1) For the [<Xn|SP>, <Zm>.D, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, 0, 0, OPSZ_2, 0) For the [<Xn|SP>, <Zm>.S, <extend> #1] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_4, extend, true, 0, OPSZ_2, 1) For the [<Xn|SP>, <Zm>.S, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_4, extend, 0, 0, OPSZ_2, 0) For the [<Xn|SP>, <Xm>, LSL #1] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_2, 1) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_2)
◆ INSTR_CREATE_ld1sw_sve_pred
| #define INSTR_CREATE_ld1sw_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1sw, Zt, Zn, Pg), DR_PRED_MASKED) |
Creates a LD1SW instruction.
This macro is used to encode the forms:
* LD1SW { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
* LD1SW { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
* LD1SW { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The first source vector base register with an immediate offset, constructed with the function: For the [<Zn>.D{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_8, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_4, 0) For the [<Xn|SP>, <Xm>, LSL #2] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_4, 2) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_4)
◆ INSTR_CREATE_ld1w_sve_pred
| #define INSTR_CREATE_ld1w_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Zn | |||
| ) |
Value:
INSTR_PRED( \
INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1w, Zt, Zn, Pg), DR_PRED_MASKED), \
DR_PRED_MASKED)
Creates a LD1W instruction.
This macro is used to encode the forms:
* LD1W { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
* LD1W { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
* LD1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #2]
* LD1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
* LD1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend> #2]
* LD1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend>]
* LD1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend> #2]
* LD1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend>]
* LD1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
* LD1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
* LD1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* LD1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The first source vector base register with an immediate offset, constructed with the function: For the [<Zn>.S{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_4, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_4, 0) For the [<Zn>.D{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_8, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_4, 0) For the [<Xn|SP>, <Zm>.D, LSL #2] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, true, 0, OPSZ_4, 2) For the [<Xn|SP>, <Zm>.D] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_4, 0) For the [<Xn|SP>, <Zm>.D, <extend> #2] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, true, 0, OPSZ_4, 2) For the [<Xn|SP>, <Zm>.D, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, 0, 0, OPSZ_4, 0) For the [<Xn|SP>, <Zm>.S, <extend> #2] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_4, extend, true, 0, OPSZ_4, 2) For the [<Xn|SP>, <Zm>.S, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_4, extend, 0, 0, OPSZ_4, 0) For the [<Xn|SP>, <Xm>, LSL #2] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_4, 2) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_4)
◆ INSTR_CREATE_ld2
| #define INSTR_CREATE_ld2 | ( | dc, | |
| Vt1, | |||
| Vt2, | |||
| Xn, | |||
| index, | |||
| elsz | |||
| ) | instr_create_2dst_3src(dc, OP_ld2, Vt1, Vt2, Xn, index, elsz) |
Creates an Advanced SIMD (NEON) LD2 instruction to load a 2-element structure to the index of two vector registers, e.g. LD2 {V0.4H, V1.4H}[5], [X0].
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vt1 The first destination vector register operand. Vt2 The second destination vector register operand. Xn The stack-pointer or GPR to load into Vt1 and Vt2. index The vector element index. elsz The vector element size
◆ INSTR_CREATE_ld2_2
| #define INSTR_CREATE_ld2_2 | ( | dc, | |
| Vt1, | |||
| Vt2, | |||
| Xn, | |||
| Xnd, | |||
| index, | |||
| offset, | |||
| elsz | |||
| ) | instr_create_3dst_5src(dc, OP_ld2, Vt1, Vt2, Xn, Xnd, index, Xn, offset, elsz) |
Creates an Advanced SIMD (NEON) LD2 instruction to load a 2-element structure to the index of two vector registers with post-indexing, e.g. LD2 {V0.4H, V1.4H}[5], [X0], X1.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vt1 The first destination vector register operand. Vt2 The second destination vector register operand. Xn The stack-pointer or register to load into Vt and Vt2. Xnd The disposition of Xn. index The index of the destination vectors. offset The post-index offset. elsz The vector element size
◆ INSTR_CREATE_ld2_multi_2
| #define INSTR_CREATE_ld2_multi_2 | ( | dc, | |
| Vt1, | |||
| Vt2, | |||
| Xn, | |||
| disp, | |||
| offset, | |||
| elsz | |||
| ) | instr_create_3dst_4src(dc, OP_ld2, Vt1, Vt2, Xn, disp, Xn, offset, elsz) |
Creates an Advanced SIMD (NEON) LD2 instruction to load multiple 2-element structures to two vector registers with post-indexing, e.g. LD2 {V0.4H, V1.4H}, [X0], #32.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vt1 The destination vector register operand. Vt2 The second destination vector register operand. Xn The stack-pointer or GPR to load into Vt1 and Vt2. disp The disposition of Xn. offset The post-index offset. elsz The vector element size
◆ INSTR_CREATE_ld2b_sve_pred
| #define INSTR_CREATE_ld2b_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) |
Value:
Rn, Pg), \
DR_PRED_MASKED)
Creates a LD2B instruction.
This macro is used to encode the forms:
* LD2B { <Zt1>.B, <Zt2>.B }, <Pg>/Z, [<Xn|SP>, <Xm>]
* LD2B { <Zt1>.B, <Zt2>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>] variant: opnd_create_base_disp_aarch64(Rn, Rm, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_1) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_1)
The Zt2 parameter is derived from Zt.
◆ INSTR_CREATE_ld2d_sve_pred
| #define INSTR_CREATE_ld2d_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) |
Value:
Rn, Pg), \
DR_PRED_MASKED)
Creates a LD2D instruction.
This macro is used to encode the forms:
* LD2D { <Zt1>.D, <Zt2>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
* LD2D { <Zt1>.D, <Zt2>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>, LSL #3] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_8, 3) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm4, OPSZ_8)
The Zt2 parameter is derived from Zt.
◆ INSTR_CREATE_ld2h_sve_pred
| #define INSTR_CREATE_ld2h_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) |
Value:
Rn, Pg), \
DR_PRED_MASKED)
Creates a LD2H instruction.
This macro is used to encode the forms:
* LD2H { <Zt1>.H, <Zt2>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
* LD2H { <Zt1>.H, <Zt2>.H }, <Pg>/Z, [<Xn|SP>{, #<simm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>, LSL #1] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_2, 1) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm4, OPSZ_2)
The Zt2 parameter is derived from Zt.
◆ INSTR_CREATE_ld2r
| #define INSTR_CREATE_ld2r | ( | dc, | |
| Vt1, | |||
| Vt2, | |||
| Xn, | |||
| elsz | |||
| ) | instr_create_2dst_2src(dc, OP_ld2r, Vt1, Vt2, Xn, elsz) |
Creates an Advanced SIMD (NEON) LD2R instruction to load and replicate a single 2-element structure to all lanes of two vector registers, e.g. LD2R {V0.4H, V1.4H}, [X0].
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vt1 The first destination vector register operand. Vt2 The second destination vector register operand. Xn The stack-pointer or GPR to load into Vt1 and Vt2. elsz The vector element size
◆ INSTR_CREATE_ld2r_2
| #define INSTR_CREATE_ld2r_2 | ( | dc, | |
| Vt1, | |||
| Vt2, | |||
| Xn, | |||
| Xnd, | |||
| Xm, | |||
| elsz | |||
| ) | instr_create_3dst_4src(dc, OP_ld2r, Vt1, Vt2, Xn, Xnd, Xn, Xm, elsz) |
Creates an Advanced SIMD (NEON) LD2R instruction to load and replicate a single 2-element structure to all lanes of two vector registers with post-indexing , e.g. LD2R {V0.4H, V1.4H}, [X0], X1.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vt1 The destination vector register operand. Vt2 The second destination vector register operand. Xn The stack-pointer or GPR to load into Vt and Vt2. Xnd Disposition of Xn. Xm The post-index offset. elsz The vector element size
◆ INSTR_CREATE_ld2w_sve_pred
| #define INSTR_CREATE_ld2w_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) |
Value:
Rn, Pg), \
DR_PRED_MASKED)
Creates a LD2W instruction.
This macro is used to encode the forms:
* LD2W { <Zt1>.S, <Zt2>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
* LD2W { <Zt1>.S, <Zt2>.S }, <Pg>/Z, [<Xn|SP>{, #<simm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>, LSL #2] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_4, 2) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm4, OPSZ_4)
◆ INSTR_CREATE_ld3
| #define INSTR_CREATE_ld3 | ( | dc, | |
| Vt1, | |||
| Vt2, | |||
| Vt3, | |||
| Xn, | |||
| index, | |||
| elsz | |||
| ) | instr_create_3dst_3src(dc, OP_ld3, Vt1, Vt2, Vt3, Xn, index, elsz) |
Creates an Advanced SIMD (NEON) LD3 instruction to load a single 3-element structure to the index of three vector registers, e.g. LD3 {V0.4H, V1.4H, V2.4H}[15], [X0].
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vt1 The first destination vector register operand. Vt2 The second destination vector register operand. Vt3 The third destination vector register operand. Xn The GPR to load into Vt1, Vt2 and Vt3. index The index of the destination vectors. elsz The vector element size
◆ INSTR_CREATE_ld3_2
| #define INSTR_CREATE_ld3_2 | ( | dc, | |
| Vt1, | |||
| Vt2, | |||
| Vt3, | |||
| Xn, | |||
| Xnd, | |||
| index, | |||
| offset, | |||
| elsz | |||
| ) | instr_create_4dst_5src(dc, OP_ld3, Vt1, Vt2, Vt3, Xn, Xnd, index, Xn, offset, elsz) |
Creates an Advanced SIMD (NEON) LD3 instruction to load a single 3-element structure to the index of three vector registers with post-index offset, e.g. LD3 {V0.4H, V1.4H, V2.4H}[15], [X0], X1.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vt1 The first destination vector register operand. Vt2 The second destination vector register operand. Vt3 The third destination vector register operand. Xn The register to load into Vt, Vt2 and Vt3. index The immediate or GPR post-index offset. Xnd The disposition of Xn. offset The immediate or GPR post-index offset. elsz The vector element size
◆ INSTR_CREATE_ld3_multi
| #define INSTR_CREATE_ld3_multi | ( | dc, | |
| Vt1, | |||
| Vt2, | |||
| Vt3, | |||
| Xn, | |||
| elsz | |||
| ) | instr_create_3dst_2src(dc, OP_ld3, Vt1, Vt2, Vt3, Xn, elsz) |
Creates an Advanced SIMD (NEON) LD3 instruction to load multiple 3-element structures from memory to three vector register, e.g. LD3 {V0.4H, V1.4H, V2.4H}, [X0].
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vt1 The first destination vector register operand. Vt2 The second destination vector register operand. Vt3 The third destination vector register operand. Xn The stack-pointer or GPR to load into Vt1, Vt2 and Vt3. elsz The vector element size
◆ INSTR_CREATE_ld3_multi_2
| #define INSTR_CREATE_ld3_multi_2 | ( | dc, | |
| Vt1, | |||
| Vt2, | |||
| Vt3, | |||
| Xn, | |||
| Xnd, | |||
| Xm, | |||
| elsz | |||
| ) | instr_create_4dst_4src(dc, OP_ld3, Vt1, Vt2, Vt3, Xn, Xnd, Xn, Xm, elsz) |
Creates an Advanced SIMD (NEON) LD3 instruction to load multiple 3-element structures from memory to the index of three vector registers with post-index offset, e.g. LD3 {V0.4H, V1.4H, V2.4H}, [X0], X1.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vt1 The first destination vector register operand. Vt2 The second destination vector register operand. Vt3 The third destination vector register operand. Xn The stack-pointer or GPR to load into Vt1, Vt2 and Vt3. Xnd The disposition of Xn. Xm The post-index offset. elsz The vector element size
◆ INSTR_CREATE_ld3b_sve_pred
| #define INSTR_CREATE_ld3b_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) |
Value:
opnd_create_increment_reg(Zt, 2), Rn, Pg), \
DR_PRED_MASKED)
Creates a LD3B instruction.
This macro is used to encode the forms:
* LD3B { <Zt1>.B, <Zt2>.B, <Zt3>.B }, <Pg>/Z, [<Xn|SP>, <Xm>]
* LD3B { <Zt1>.B, <Zt2>.B, <Zt3>.B }, <Pg>/Z, [<Xn|SP>{, #<simm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>] variant: opnd_create_base_disp_aarch64(Rn, Rm, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_1) For the [<Xn|SP>{, #<simm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm4, OPSZ_1)
The Zt2 and Zt3 parameters are derived from Zt.
◆ INSTR_CREATE_ld3d_sve_pred
| #define INSTR_CREATE_ld3d_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) |
Value:
opnd_create_increment_reg(Zt, 2), Rn, Pg), \
DR_PRED_MASKED)
Creates a LD3D instruction.
This macro is used to encode the forms:
* LD3D { <Zt1>.D, <Zt2>.D, <Zt3>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
* LD3D { <Zt1>.D, <Zt2>.D, <Zt3>.D }, <Pg>/Z, [<Xn|SP>{, #<simm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>, LSL #3] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_8, 3) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm4, OPSZ_8)
The Zt2 and Zt3 parameters are derived from Zt.
◆ INSTR_CREATE_ld3h_sve_pred
| #define INSTR_CREATE_ld3h_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) |
Value:
opnd_create_increment_reg(Zt, 2), Rn, Pg), \
DR_PRED_MASKED)
Creates a LD3H instruction.
This macro is used to encode the forms:
* LD3H { <Zt1>.H, <Zt2>.H, <Zt3>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
* LD3H { <Zt1>.H, <Zt2>.H, <Zt3>.H }, <Pg>/Z, [<Xn|SP>{, #<simm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>, LSL #1] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_2, 1) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm4, OPSZ_2)
The Zt2 and Zt3 parameters are derived from Zt.
◆ INSTR_CREATE_ld3r
| #define INSTR_CREATE_ld3r | ( | dc, | |
| Vt1, | |||
| Vt2, | |||
| Vt3, | |||
| Xn, | |||
| elsz | |||
| ) | instr_create_3dst_2src(dc, OP_ld3r, Vt1, Vt2, Vt3, Xn, elsz) |
Creates an Advanced SIMD (NEON) LD3 instruction to load and replicate a single 3-element structure to the index of three vector registers, e.g. LD3 {V0.4H, V1.4H, V2.4H}[15], [X0].
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vt1 The first destination vector register operand. Vt2 The second destination vector register operand. Vt3 The third destination vector register operand. Xn The stack-pointer or GPR to load into Vt1, Vt2 and Vt3. elsz The vector element size
◆ INSTR_CREATE_ld3r_2
| #define INSTR_CREATE_ld3r_2 | ( | dc, | |
| Vt1, | |||
| Vt2, | |||
| Vt3, | |||
| Xn, | |||
| Xnd, | |||
| offset, | |||
| elsz | |||
| ) | instr_create_4dst_4src(dc, OP_ld3r, Vt1, Vt2, Vt3, Xn, Xnd, Xn, offset, elsz) |
Creates an Advanced SIMD (NEON) LD3 instruction to load and replicate a single 3-element structure to the index of three vector registers with post-index offset, e.g. LD3 {V0.4H, V1.4H, V2.4H}[15], [X0], X1.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vt1 The first destination vector register operand. Vt2 The second destination vector register operand. Vt3 The third destination vector register operand. Xn The stack-pointer or GPR to load into Vt1, Vt2 and Vt3. Xnd The disposition of Xn. offset The immediate or GPR post-index offset elsz The vector element size
◆ INSTR_CREATE_ld3w_sve_pred
| #define INSTR_CREATE_ld3w_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) |
Value:
opnd_create_increment_reg(Zt, 2), Rn, Pg), \
DR_PRED_MASKED)
Creates a LD3W instruction.
This macro is used to encode the forms:
* LD3W { <Zt1>.S, <Zt2>.S, <Zt3>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
* LD3W { <Zt1>.S, <Zt2>.S, <Zt3>.S }, <Pg>/Z, [<Xn|SP>{, #<simm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>, LSL #2] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_4, 2) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm4, OPSZ_4)
The Zt2 and Zt3 parameters are derived from Zt.
◆ INSTR_CREATE_ld4
| #define INSTR_CREATE_ld4 | ( | dc, | |
| Vt1, | |||
| Vt2, | |||
| Vt3, | |||
| Vt4, | |||
| Xn, | |||
| index, | |||
| elsz | |||
| ) | instr_create_4dst_3src(dc, OP_ld4, Vt1, Vt2, Vt3, Vt4, Xn, index, elsz) |
Creates an Advanced SIMD (NEON) LD4 instruction to load single or multiple 4-element structures to four vector registers, e.g. LD4 {V0.4H, V1.4H, V2.4H, V3.4H}, [X0].
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vt1 The first destination vector register operand. Vt2 The second destination vector register operand. Vt3 The third destination vector register operand. Vt4 The fourth destination vector register operand. Xn The stack-pointer or register to load into the destination vectors. index The immediate or GPR post-index offset. elsz The vector element size
◆ INSTR_CREATE_ld4_2
| #define INSTR_CREATE_ld4_2 | ( | dc, | |
| Vt1, | |||
| Vt2, | |||
| Vt3, | |||
| Vt4, | |||
| Xn, | |||
| Xnd, | |||
| index, | |||
| offset, | |||
| elsz | |||
| ) |
Value:
instr_create_5dst_5src(dc, OP_ld4, Vt1, Vt2, Vt3, Vt4, Xn, Xnd, index, Xn, offset, \
elsz)
Creates an Advanced SIMD (NEON) LD4 instruction to load a single 4-element structures to four vector registers with post-index, e.g. LD4 {V0.4H, V1.4H, V2.4H, V3.4H}, [X0], X1.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vt1 The first destination vector register operand. Vt2 The second destination vector register operand. Vt3 The third destination vector register operand. Vt4 The fourth destination vector register operand. Xn The stack-pointer or GPR to load into the destination vectors. Xnd The disposition of Xn. index The index of the destination vectors. offset The post-index offset. elsz The vector element size
◆ INSTR_CREATE_ld4_multi
| #define INSTR_CREATE_ld4_multi | ( | dc, | |
| Vt1, | |||
| Vt2, | |||
| Vt3, | |||
| Vt4, | |||
| Xn, | |||
| elsz | |||
| ) | instr_create_4dst_2src(dc, OP_ld4, Vt1, Vt2, Vt3, Vt4, Xn, elsz) |
Creates an Advanced SIMD (NEON) LD4 instruction to load single or multiple 4-element structures to four vector registers, e.g. LD4 {V0.4H, V1.4H, V2.4H, V3.4H}, [X0].
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vt1 The first destination vector register operand. Vt2 The second destination vector register operand. Vt3 The third destination vector register operand. Vt4 The fourth destination vector register operand. Xn The stack-pointer or register to load into the destination vectors. elsz The vector element size
◆ INSTR_CREATE_ld4_multi_2
| #define INSTR_CREATE_ld4_multi_2 | ( | dc, | |
| Vt1, | |||
| Vt2, | |||
| Vt3, | |||
| Vt4, | |||
| Xn, | |||
| Xnd, | |||
| offset, | |||
| elsz | |||
| ) | instr_create_5dst_4src(dc, OP_ld4, Vt1, Vt2, Vt3, Vt4, Xn, Xnd, Xn, offset, elsz) |
Creates an Advanced SIMD (NEON) LD4 instruction to load multiple 4-element structures to four vector registers with post-index, e.g. LD4 {V0.4H, V1.4H, V2.4H, V3.4H}, [X0], X1.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vt1 The first destination vector register operand. Vt2 The second destination vector register operand. Vt3 The third destination vector register operand. Vt4 The fourth destination vector register operand. Xn The stack-pointer or GPR to load into the destination vectors Xnd The disposition of Xn offset The post-index offset. elsz The vector element size
◆ INSTR_CREATE_ld4b_sve_pred
| #define INSTR_CREATE_ld4b_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) |
Value:
Creates a LD4B instruction.
This macro is used to encode the forms:
* LD4B { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <Pg>/Z, [<Xn|SP>, <Xm>]
* LD4B { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>] variant: opnd_create_base_disp_aarch64(Rn, Rm, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_1) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_1)
The Zt2, Zt3 and Zt4 parameters are derived from Zt.
◆ INSTR_CREATE_ld4d_sve_pred
| #define INSTR_CREATE_ld4d_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) |
Value:
Creates a LD4D instruction.
This macro is used to encode the forms:
* LD4D { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
* LD4D { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <Pg>/Z, [<Xn|SP>{, #<simm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>, LSL #3] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_8, 3) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm4, OPSZ_8)
The Zt2, Zt3 and Zt4 parameters are derived from Zt.
◆ INSTR_CREATE_ld4h_sve_pred
| #define INSTR_CREATE_ld4h_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) |
Value:
Creates a LD4H instruction.
This macro is used to encode the forms:
* LD4H { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
* LD4H { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <Pg>/Z, [<Xn|SP>{, #<simm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>, LSL #1] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_2, 1) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm4, OPSZ_2)
The Zt2, Zt3 and Zt4 parameters are derived from Zt.
◆ INSTR_CREATE_ld4r
| #define INSTR_CREATE_ld4r | ( | dc, | |
| Vt1, | |||
| Vt2, | |||
| Vt3, | |||
| Vt4, | |||
| Xn, | |||
| elsz | |||
| ) | instr_create_4dst_2src(dc, OP_ld4r, Vt1, Vt2, Vt3, Vt4, Xn, elsz) |
Creates an Advanced SIMD (NEON) LD4R instruction to load and replicate a single 4-element structure to four vector registers, e.g. LD4R {V0.4H, V1.4H, V2.4H, V3.4H}, [X0].
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vt1 The first destination vector register operand. Vt2 The second destination vector register operand. Vt3 The third destination vector register operand. Vt4 The fourth destination vector register operand. Xn The stack-pointer or GPR to load into the destination vectors. elsz The vector element size
◆ INSTR_CREATE_ld4r_2
| #define INSTR_CREATE_ld4r_2 | ( | dc, | |
| Vt1, | |||
| Vt2, | |||
| Vt3, | |||
| Vt4, | |||
| Xn, | |||
| Xnd, | |||
| offset, | |||
| elsz | |||
| ) | instr_create_5dst_4src(dc, OP_ld4r, Vt1, Vt2, Vt3, Vt4, Xn, Xnd, Xn, offset, elsz) |
Creates an Advanced SIMD (NEON) LD4R instruction to load and replicate a single 4-element structure to four vector registers with post-indexing, e.g. LD4 {V0.4H, V1.4H, V2.4H, V3.4H}, [X0], X1.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vt1 The first destination vector register operand. Vt2 The second destination vector register operand. Vt3 The third destination vector register operand. Vt4 The fourth destination vector register operand. Xn The stack-pointer or register to load into the destination vectors. Xnd The disposition of Xn. offset The post-index offset. elsz The vector element size
◆ INSTR_CREATE_ld4w_sve_pred
| #define INSTR_CREATE_ld4w_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) |
Value:
Creates a LD4W instruction.
This macro is used to encode the forms:
* LD4W { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
* LD4W { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <Pg>/Z, [<Xn|SP>{, #<simm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>, LSL #2] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_4, 2) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm4, OPSZ_4)
The Zt2, Zt3 and Zt4 parameters are derived from Zt.
◆ INSTR_CREATE_ldapr
| #define INSTR_CREATE_ldapr | ( | dc, | |
| Rt, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_ldapr, (Rt), (mem)) |
Creates a LDAPR load-acquire instruction.
This macro is used to encode the forms:
* LDAPR <Wt>, [<Xn|SP> {,#0}]
* LDAPR <Xt>, [<Xn|SP> {,#0}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The destination register, W (Word, 32 bits) or X (Extended, 64 bits). mem The source memory address operand.
◆ INSTR_CREATE_ldaprb
| #define INSTR_CREATE_ldaprb | ( | dc, | |
| Rt, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_ldaprb, (Rt), (mem)) |
Creates a LDAPRB load-acquire byte instruction.
This macro is used to encode the forms:
* LDAPRB <Wt>, [<Xn|SP> {,#0}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The destination register, W (Word, 32 bits). mem The source memory address operand.
◆ INSTR_CREATE_ldaprh
| #define INSTR_CREATE_ldaprh | ( | dc, | |
| Rt, | |||
| mem | |||
| ) | instr_create_1dst_1src((dc), OP_ldaprh, (Rt), (mem)) |
Creates a LDAPRH load-acquire half-word instruction.
This macro is used to encode the forms:
* LDAPRH <Wt>, [<Xn|SP> {,#0}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The destination register, W (Word, 32 bits). mem The source memory address operand.
◆ INSTR_CREATE_ldapur
| #define INSTR_CREATE_ldapur | ( | dc, | |
| Rt, | |||
| mem | |||
| ) | instr_create_1dst_1src(dc, OP_ldapur, Rt, mem) |
Creates a LDAPUR instruction.
This macro is used to encode the forms:
* LDAPUR <Wt>, [<Xn|SP>{, #<simm>}]
* LDAPUR <Xt>, [<Xn|SP>{, #<simm>}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The destination register, W (Word, 32 bits) or X (Extended, 64 bits). mem The source memory address operand constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, simm, OPSZ_4)
◆ INSTR_CREATE_ldapurb
| #define INSTR_CREATE_ldapurb | ( | dc, | |
| Rt, | |||
| mem | |||
| ) | instr_create_1dst_1src(dc, OP_ldapurb, Rt, mem) |
Creates a LDAPURB instruction.
This macro is used to encode the forms:
* LDAPURB <Wt>, [<Xn|SP>{, #<simm>}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The destination register, W (Word, 32 bits). mem The source memory address operand constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, simm, OPSZ_1)
◆ INSTR_CREATE_ldapurh
| #define INSTR_CREATE_ldapurh | ( | dc, | |
| Rt, | |||
| mem | |||
| ) | instr_create_1dst_1src(dc, OP_ldapurh, Rt, mem) |
Creates a LDAPURH instruction.
This macro is used to encode the forms:
* LDAPURH <Wt>, [<Xn|SP>{, #<simm>}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The destination register, W (Word, 32 bits). mem The source memory address operand constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, simm, OPSZ_2)
◆ INSTR_CREATE_ldapursb
| #define INSTR_CREATE_ldapursb | ( | dc, | |
| Rt, | |||
| mem | |||
| ) | instr_create_1dst_1src(dc, OP_ldapursb, Rt, mem) |
Creates a LDAPURSB instruction.
This macro is used to encode the forms:
* LDAPURSB <Wt>, [<Xn|SP>{, #<simm>}]
* LDAPURSB <Xt>, [<Xn|SP>{, #<simm>}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The destination register, W (Word, 32 bits) or X (Extended, 64 bits). mem The source memory address operand constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, simm, OPSZ_1)
◆ INSTR_CREATE_ldapursh
| #define INSTR_CREATE_ldapursh | ( | dc, | |
| Rt, | |||
| mem | |||
| ) | instr_create_1dst_1src(dc, OP_ldapursh, Rt, mem) |
Creates a LDAPURSB instruction.
This macro is used to encode the forms:
* LDAPURSH <Wt>, [<Xn|SP>{, #<simm>}]
* LDAPURSH <Xt>, [<Xn|SP>{, #<simm>}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The destination register, W (Word, 32 bits) or X (Extended, 64 bits). mem The source memory address operand constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, simm, OPSZ_2)
◆ INSTR_CREATE_ldapursw
| #define INSTR_CREATE_ldapursw | ( | dc, | |
| Rt, | |||
| mem | |||
| ) | instr_create_1dst_1src(dc, OP_ldapursw, Rt, mem) |
Creates a LDAPURSW instruction.
This macro is used to encode the forms:
* LDAPURSW <Xt>, [<Xn|SP>{, #<simm>}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The destination register, X (Extended, 64 bits). mem The source memory address operand constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, simm, OPSZ_4)
◆ INSTR_CREATE_ldff1b_sve_pred
| #define INSTR_CREATE_ldff1b_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1b, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LDFF1B instruction.
This macro is used to encode the forms:
* LDFF1B { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, <Xm>}]
* LDFF1B { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, <Xm>}]
* LDFF1B { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>}]
* LDFF1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>{, <Xm>}]
* LDFF1B { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
* LDFF1B { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
* LDFF1B { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
* LDFF1B { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend>]
* LDFF1B { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend>]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>{, <Xm>}] variant: opnd_create_base_disp_aarch64(Rn, Rm, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_1) For the [<Zn>.S{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_4, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_1, 0) For the [<Zn>.D{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_8, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_1, 0) For the [<Xn|SP>, <Zm>.D] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, DR_EXTEND_UXTX, 0, OPSZ_1, 0) For the [<Xn|SP>, <Zm>.D, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, 0, 0, OPSZ_1, 0) For the [<Xn|SP>, <Zm>.S, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_4, extend, 0, 0, OPSZ_1, 0)
◆ INSTR_CREATE_ldff1d_sve_pred
| #define INSTR_CREATE_ldff1d_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1d, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LDFF1D instruction.
This macro is used to encode the forms:
* LDFF1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #3}]
* LDFF1D { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
* LDFF1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #3]
* LDFF1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
* LDFF1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend> #3]
* LDFF1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend>]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>{, <Xm>, LSL #3}] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, 1, 0, 0, OPSZ_32, 3) For the [<Zn>.D{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_8, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_8, 0) For the [<Xn|SP>, <Zm>.D, LSL #3] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, true, 0, OPSZ_8, 3) For the [<Xn|SP>, <Zm>.D] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_8, 0) For the [<Xn|SP>, <Zm>.D, <extend> #3] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, true, 0, OPSZ_8, 3) For the [<Xn|SP>, <Zm>.D, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, 0, 0, OPSZ_8, 0)
◆ INSTR_CREATE_ldff1h_sve_pred
| #define INSTR_CREATE_ldff1h_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1h, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LDFF1H instruction.
This macro is used to encode the forms:
* LDFF1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #1}]
* LDFF1H { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #1}]
* LDFF1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #1}]
* LDFF1H { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
* LDFF1H { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
* LDFF1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #1]
* LDFF1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
* LDFF1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend> #1]
* LDFF1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend>]
* LDFF1H { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend> #1]
* LDFF1H { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend>]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>{, <Xm>, LSL #1}] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, 1, 0, 0, OPSZ_2, 1) For the [<Zn>.S{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_4, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_2, 0) For the [<Zn>.D{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_8, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_2, 0) For the [<Xn|SP>, <Zm>.D, LSL #1] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, true, 0, OPSZ_2, 1) For the [<Xn|SP>, <Zm>.D] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_2, 0) For the [<Xn|SP>, <Zm>.D, <extend> #1] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, true, 0, OPSZ_2, 1) For the [<Xn|SP>, <Zm>.D, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, 0, 0, OPSZ_2, 0) For the [<Xn|SP>, <Zm>.S, <extend> #1] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_4, extend, true, 0, OPSZ_2, 1) For the [<Xn|SP>, <Zm>.S, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_4, extend, 0, 0, OPSZ_2, 0)
◆ INSTR_CREATE_ldff1sb_sve_pred
| #define INSTR_CREATE_ldff1sb_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1sb, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LDFF1SB instruction.
This macro is used to encode the forms:
* LDFF1SB { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, <Xm>}]
* LDFF1SB { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, <Xm>}]
* LDFF1SB { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>}]
* LDFF1SB { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
* LDFF1SB { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
* LDFF1SB { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
* LDFF1SB { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend>]
* LDFF1SB { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend>]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>{, <Xm>}] variant: opnd_create_base_disp_aarch64( Rn, Rm, DR_EXTEND_UXTX, false, 0, 0, OPSZ_1) For the [<Zn>.S{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_4, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_1, 0) For the [<Zn>.D{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_8, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_1, 0) For the [<Xn|SP>, <Zm>.D] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_1, 0) For the [<Xn|SP>, <Zm>.D, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, 0, 0, OPSZ_1, 0) For the [<Xn|SP>, <Zm>.S, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_4, extend, 0, 0, OPSZ_1, 0)
◆ INSTR_CREATE_ldff1sh_sve_pred
| #define INSTR_CREATE_ldff1sh_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1sh, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LDFF1SH instruction.
This macro is used to encode the forms:
* LDFF1SH { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #1}]
* LDFF1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #1}]
* LDFF1SH { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
* LDFF1SH { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
* LDFF1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #1]
* LDFF1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
* LDFF1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend> #1]
* LDFF1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend>]
* LDFF1SH { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend> #1]
* LDFF1SH { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend>]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>{, <Xm>, LSL #1}] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, 1, 0, 0, OPSZ_2, 1) For the [<Zn>.S{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_4, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_2, 0) For the [<Zn>.D{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_8, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_2, 0) For the [<Xn|SP>, <Zm>.D, LSL #1] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, true, 0, OPSZ_2, 1) For the [<Xn|SP>, <Zm>.D] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_2, 0) For the [<Xn|SP>, <Zm>.D, <extend> #1] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, true, 0, OPSZ_2, 1) For the [<Xn|SP>, <Zm>.D, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, 0, 0, OPSZ_2, 0) For the [<Xn|SP>, <Zm>.S, <extend> #1] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_4, extend, true, 0, OPSZ_2, 1) For the [<Xn|SP>, <Zm>.S, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_4, extend, 0, 0, OPSZ_2, 0)
◆ INSTR_CREATE_ldff1sw_sve_pred
| #define INSTR_CREATE_ldff1sw_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1sw, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LDFF1SW instruction.
This macro is used to encode the forms:
* LDFF1SW { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #2}]
* LDFF1SW { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
* LDFF1SW { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #2]
* LDFF1SW { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
* LDFF1SW { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend> #2]
* LDFF1SW { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend>]
* LDFF1SW { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend> #2]
* LDFF1SW { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend>]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>{, <Xm>, LSL #2}] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, 1, 0, 0, OPSZ_16, 2) For the [<Zn>.D{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_8, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_4, 0) For the [<Xn|SP>, <Zm>.D, LSL #2] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, true, 0, OPSZ_4, 2) For the [<Xn|SP>, <Zm>.D] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_4, 0) For the [<Xn|SP>, <Zm>.D, <extend> #2] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, true, 0, OPSZ_4, 2) For the [<Xn|SP>, <Zm>.D, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, 0, 0, OPSZ_4, 0) For the [<Xn|SP>, <Zm>.S, <extend> #2] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_4, extend, true, 0, OPSZ_4, 2) For the [<Xn|SP>, <Zm>.S, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_4, extend, 0, 0, OPSZ_4, 0)
◆ INSTR_CREATE_ldff1w_sve_pred
| #define INSTR_CREATE_ldff1w_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1w, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LDFF1W instruction.
This macro is used to encode the forms:
* LDFF1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #2}]
* LDFF1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #2}]
* LDFF1W { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
* LDFF1W { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>{, <Xm>, LSL #2}] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, 1, 0, 0, OPSZ_4, 2) For the [<Zn>.S{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_4, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_4, 0) For the [<Zn>.D{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_8, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_4, 0)
◆ INSTR_CREATE_ldg
| #define INSTR_CREATE_ldg | ( | dc, | |
| Rt, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_ldg, Rt, Rt, Rn) |
Creates a LDG instruction.
This macro is used to encode the forms:
LDG <Xt>, [<Xn|SP>, #<simm>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The source and destination register, X (Extended, 64 bits). Rn The source base register with an immediate offset, constructed with the function: opnd_create_base_disp_aarch64(Rn, DR_REG_NULL, DR_EXTEND_UXTX, 0, simm, 0, OPSZ_0)
◆ INSTR_CREATE_ldgm
| #define INSTR_CREATE_ldgm | ( | dc, | |
| Rt, | |||
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_ldgm, Rt, Rn) |
Creates an LDGM instruction.
This macro is used to encode the forms:
LDGM <Xt>, [<Xn|SP>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The source register, X (Extended, 64 bits). Rn The source base register, constructed with the function: opnd_create_base_disp_aarch64(Rn, DR_REG_NULL, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_0) Note that memory tag accesses are not treated as real/data memory accesses by DynamoRIO, similar to prefetch and PC-relative address manipulation instructions.
◆ INSTR_CREATE_ldlar
| #define INSTR_CREATE_ldlar | ( | dc, | |
| Rt, | |||
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_ldlar, Rt, Rn) |
Creates a LDLAR instruction.
This macro is used to encode the forms:
* LDLAR <Wt>, [<Xn|SP>] * LDLAR <Xt>, [<Xn|SP>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The first destination register. Can be W (Word, 32 bits) or X (Extended, 64 bits) Rn The second source register. Can be X (Extended, 64 bits)
◆ INSTR_CREATE_ldlarb
| #define INSTR_CREATE_ldlarb | ( | dc, | |
| Rt, | |||
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_ldlarb, Rt, Rn) |
Creates a LDLARB instruction.
This macro is used to encode the forms:
* LDLARB <Wt>, [<Xn|SP>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The first destination register, W (Word, 32 bits) Rn The second source register, X (Extended, 64 bits)
◆ INSTR_CREATE_ldlarh
| #define INSTR_CREATE_ldlarh | ( | dc, | |
| Rt, | |||
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_ldlarh, Rt, Rn) |
Creates a LDLARH instruction.
This macro is used to encode the forms:
* LDLARH <Wt>, [<Xn|SP>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The first destination register, W (Word, 32 bits) Rn The second source register, X (Extended, 64 bits)
◆ INSTR_CREATE_ldnf1b_sve_pred
| #define INSTR_CREATE_ldnf1b_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1b, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LDNF1B instruction.
This macro is used to encode the forms:
* LDNF1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* LDNF1B { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* LDNF1B { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* LDNF1B { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with an immediate offset, constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_1)
◆ INSTR_CREATE_ldnf1d_sve_pred
| #define INSTR_CREATE_ldnf1d_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1d, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LDNF1D instruction.
This macro is used to encode the forms:
* LDNF1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with an immediate offset, constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_8)
◆ INSTR_CREATE_ldnf1h_sve_pred
| #define INSTR_CREATE_ldnf1h_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1h, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LDNF1H instruction.
This macro is used to encode the forms:
* LDNF1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* LDNF1H { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* LDNF1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with an immediate offset, constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_2)
◆ INSTR_CREATE_ldnf1sb_sve_pred
| #define INSTR_CREATE_ldnf1sb_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1sb, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LDNF1SB instruction.
This macro is used to encode the forms:
* LDNF1SB { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* LDNF1SB { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* LDNF1SB { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with an immediate offset, constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_1)
◆ INSTR_CREATE_ldnf1sh_sve_pred
| #define INSTR_CREATE_ldnf1sh_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1sh, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LDNF1SH instruction.
This macro is used to encode the forms:
* LDNF1SH { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* LDNF1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with an immediate offset, constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_2)
◆ INSTR_CREATE_ldnf1sw_sve_pred
| #define INSTR_CREATE_ldnf1sw_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1sw, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LDNF1SW instruction.
This macro is used to encode the forms:
* LDNF1SW { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with an immediate offset, constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_4)
◆ INSTR_CREATE_ldnf1w_sve_pred
| #define INSTR_CREATE_ldnf1w_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1w, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LDNF1W instruction.
This macro is used to encode the forms:
* LDNF1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* LDNF1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with an immediate offset, constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_4)
◆ INSTR_CREATE_ldnt1b_sve_pred
| #define INSTR_CREATE_ldnt1b_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1b, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LDNT1B instruction.
This macro is used to encode the forms:
* LDNT1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>, <Xm>]
* LDNT1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* LDNT1B { <Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]
* LDNT1B { <Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>] variant: opnd_create_base_disp_aarch64( Rn, Rm, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_1) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_1) For the [<Zn>.D{, <Xm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, Xm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_1, 0) For the [<Zn>.S{, <Xm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, Xm, OPSZ_4, DR_EXTEND_UXTX, 0, 0, OPSZ_1, 0)
◆ INSTR_CREATE_ldnt1d_sve_pred
| #define INSTR_CREATE_ldnt1d_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1d, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LDNT1D instruction.
This macro is used to encode the forms:
* LDNT1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
* LDNT1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* LDNT1D { <Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>, LSL #3] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_8, 3) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_8) For the [<Zn>.D{, <Xm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, Xm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_8, 0)
◆ INSTR_CREATE_ldnt1h_sve_pred
| #define INSTR_CREATE_ldnt1h_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1h, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LDNT1H instruction.
This macro is used to encode the forms:
* LDNT1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
* LDNT1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* LDNT1H { <Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]
* LDNT1H { <Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>, LSL #1] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_2, 1) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_2) For the [<Zn>.D{, <Xm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, Xm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_2, 0) For the [<Zn>.S{, <Xm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, Xm, OPSZ_4, DR_EXTEND_UXTX, 0, 0, OPSZ_2, 0)
◆ INSTR_CREATE_ldnt1sb_sve_pred
| #define INSTR_CREATE_ldnt1sb_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1sb, Zt, Zn, Pg), DR_PRED_MASKED) |
Creates a LDNT1SB instruction.
This macro is used to encode the forms:
LDNT1SB { <Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]
LDNT1SB { <Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register. Can be Z.d or Z.s. Pg The governing predicate register, P (Predicate). Zn The first source vector base register with a register offset, constructed with the function: For the [<Zn>.D{, <Xm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, Xm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_1, 0) For the [<Zn>.S{, <Xm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, Xm, OPSZ_4, DR_EXTEND_UXTX, 0, 0, OPSZ_1, 0)
◆ INSTR_CREATE_ldnt1sh_sve_pred
| #define INSTR_CREATE_ldnt1sh_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1sh, Zt, Zn, Pg), DR_PRED_MASKED) |
Creates a LDNT1SH instruction.
This macro is used to encode the forms:
LDNT1SH { <Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]
LDNT1SH { <Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register. Can be Z.d or Z.s. Pg The governing predicate register, P (Predicate). Zn The first source vector base register with a register offset, constructed with the function: For the [<Zn>.D{, <Xm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, Xm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_2, 0) For the [<Zn>.S{, <Xm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, Xm, OPSZ_4, DR_EXTEND_UXTX, 0, 0, OPSZ_2, 0)
◆ INSTR_CREATE_ldnt1sw_sve_pred
| #define INSTR_CREATE_ldnt1sw_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1sw, Zt, Zn, Pg), DR_PRED_MASKED) |
Creates a LDNT1SW instruction.
This macro is used to encode the forms:
LDNT1SW { <Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z.d. Pg The governing predicate register, P (Predicate). Zn The first source vector base register with a register offset, constructed with the function: opnd_create_vector_base_disp_aarch64( Zn, Xm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_4, 0)
◆ INSTR_CREATE_ldnt1w_sve_pred
| #define INSTR_CREATE_ldnt1w_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1w, Zt, Rn, Pg), DR_PRED_MASKED) |
Creates a LDNT1W instruction.
This macro is used to encode the forms:
* LDNT1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
* LDNT1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
* LDNT1W { <Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]
* LDNT1W { <Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The first source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>, LSL #2] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_4, 2) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_4) For the [<Zn>.D{, <Xm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, Xm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_4, 0) For the [<Zn>.S{, <Xm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, Xm, OPSZ_4, DR_EXTEND_UXTX, 0, 0, OPSZ_4, 0)
◆ INSTR_CREATE_ldpsw
| #define INSTR_CREATE_ldpsw | ( | dc, | |
| Xt1, | |||
| Xt2, | |||
| Xn, | |||
| Xr, | |||
| imm | |||
| ) | instr_create_3dst_3src(dc, OP_ldpsw, Xt1, Xt2, Xn, Xr, Xn, imm) |
Creates a LDPSW floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Xt1 The first GPR output register. Xt2 The second GPR output register. Xn The input Stack-pointer or GPR register. Xr The disposition of the input Stack-pointer or GPR register. imm The immediate integer offset.
◆ INSTR_CREATE_ldpsw_2
| #define INSTR_CREATE_ldpsw_2 | ( | dc, | |
| Xt1, | |||
| Xt2, | |||
| Xn | |||
| ) | instr_create_2dst_1src(dc, OP_ldpsw, Xt1, Xt2, Xn) |
Creates a LDPSW floating point instruction.
- Parameters
-
dc dc Xt1 The first GPR output register. Xt2 The second GPR output register. Xn The disposition of the input register.
◆ INSTR_CREATE_ldr_imm
| #define INSTR_CREATE_ldr_imm | ( | dc, | |
| Rt, | |||
| Xn, | |||
| Rn, | |||
| imm | |||
| ) | instr_create_2dst_3src(dc, OP_ldr, Rt, Xn, Rn, Xn, imm) |
Creates an LDR immediate instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The output register. Xn The input register or stack pointer. Rn The input memory disposition. imm Immediate int of the input register offset
◆ INSTR_CREATE_ldraa
| #define INSTR_CREATE_ldraa | ( | dc, | |
| Rt, | |||
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_ldraa, Rt, Rn) |
Creates a LDRAA instruction.
This macro is used to encode the forms:
* LDRAA <Xt>, [<Xn|SP>, #<simm>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The destination register, X (Extended, 64 bits). Rn The first source base register with an immediate offset, constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, simm, OPSZ_8)
◆ INSTR_CREATE_ldraa_imm
| #define INSTR_CREATE_ldraa_imm | ( | dc, | |
| Rt, | |||
| Xn, | |||
| Rn, | |||
| simm | |||
| ) | instr_create_2dst_3src(dc, OP_ldraa, Rt, Xn, Rn, Xn, simm) |
Creates a LDRAA instruction.
This macro is used to encode the forms:
* LDRAA <Xt>, [<Xn|SP>, #<simm>]! *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The destination register, X (Extended, 64 bits). Xn The base register. Rn The base register with an immediate offset, constructed with the function: opnd_create_base_disp(Xn, DR_REG_NULL, 0, simm, OPSZ_8) simm The immediate offset.
◆ INSTR_CREATE_ldrab
| #define INSTR_CREATE_ldrab | ( | dc, | |
| Rt, | |||
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_ldrab, Rt, Rn) |
Creates a LDRAB instruction.
This macro is used to encode the forms:
* LDRAB <Xt>, [<Xn|SP>, #<simm>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The destination register, X (Extended, 64 bits). Rn The first source base register with an immediate offset, constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, simm, OPSZ_8)
◆ INSTR_CREATE_ldrab_imm
| #define INSTR_CREATE_ldrab_imm | ( | dc, | |
| Rt, | |||
| Xn, | |||
| Rn, | |||
| simm | |||
| ) | instr_create_2dst_3src(dc, OP_ldrab, Rt, Xn, Rn, Xn, simm) |
Creates a LDRAB instruction.
This macro is used to encode the forms:
* LDRAB <Xt>, [<Xn|SP>, #<simm>]! *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The destination register, X (Extended, 64 bits). Xn The base register. Rn The base register with an immediate offset, constructed with the function: opnd_create_base_disp(Xn, DR_REG_NULL, 0, simm, OPSZ_8) simm The immediate offset.
◆ INSTR_CREATE_lsl_sve
| #define INSTR_CREATE_lsl_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_2src(dc, OP_lsl, Zd, Zn, imm) |
Creates a LSL instruction.
This macro is used to encode the forms:
* LSL <Zd>.<Ts>, <Zn>.<Ts>, #<const> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). imm The immediate imm.
◆ INSTR_CREATE_lsl_sve_pred
| #define INSTR_CREATE_lsl_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_lsl, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a LSL instruction.
This macro is used to encode the forms:
* LSL <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_lsl_sve_pred_wide
| #define INSTR_CREATE_lsl_sve_pred_wide | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_lsl, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a LSL instruction.
This macro is used to encode the forms:
* LSL <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_lsl_sve_wide
| #define INSTR_CREATE_lsl_sve_wide | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_lsl, Zd, Zn, Zm) |
Creates a LSL instruction.
This macro is used to encode the forms:
* LSL <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_lslr_sve_pred
| #define INSTR_CREATE_lslr_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_lslr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a LSLR instruction.
This macro is used to encode the forms:
* LSLR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_lsr_sve
| #define INSTR_CREATE_lsr_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_2src(dc, OP_lsr, Zd, Zn, imm) |
Creates a LSR instruction.
This macro is used to encode the forms:
* LSR <Zd>.<Ts>, <Zn>.<Ts>, #<const> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). imm The immediate imm, one indexed.
◆ INSTR_CREATE_lsr_sve_pred
| #define INSTR_CREATE_lsr_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_lsr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a LSR instruction.
This macro is used to encode the forms:
* LSR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_lsr_sve_pred_wide
| #define INSTR_CREATE_lsr_sve_pred_wide | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_lsr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a LSR instruction.
This macro is used to encode the forms:
* LSR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_lsr_sve_wide
| #define INSTR_CREATE_lsr_sve_wide | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_lsr, Zd, Zn, Zm) |
Creates a LSR instruction.
This macro is used to encode the forms:
* LSR <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_lsrr_sve_pred
| #define INSTR_CREATE_lsrr_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_lsrr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a LSRR instruction.
This macro is used to encode the forms:
* LSRR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_mad_sve_pred
| #define INSTR_CREATE_mad_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm, | |||
| Za | |||
| ) | INSTR_PRED(instr_create_1dst_4src(dc, OP_mad, Zdn, Zdn, Pg, Zm, Za), DR_PRED_MASKED) |
Creates a MAD instruction.
This macro is used to encode the forms:
* MAD <Zdn>.<Ts>, <Pg>/M, <Zm>.<Ts>, <Za>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable). Za The third source vector register, Z (Scalable).
◆ INSTR_CREATE_match_sve_pred
| #define INSTR_CREATE_match_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_match, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a MATCH instruction.
This macro is used to encode the forms:
MATCH <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register. Can be P.b or P.h. Pg The governing predicate register, P (Predicate). Zn The first source vector register. Can be Z.b or Z.h. Zm The second source vector register. Can be Z.b or Z.h.
◆ INSTR_CREATE_mla_sve_pred
| #define INSTR_CREATE_mla_sve_pred | ( | dc, | |
| Zda, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_4src(dc, OP_mla, Zda, Zda, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a MLA instruction.
This macro is used to encode the forms:
* MLA <Zda>.<Ts>, <Pg>/M, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_mla_vector
| #define INSTR_CREATE_mla_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_4src(dc, OP_mla, Rd, Rd, Rm, Rn, width) |
Creates a MLA vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. The instruction also reads this register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_mls_sve_pred
| #define INSTR_CREATE_mls_sve_pred | ( | dc, | |
| Zda, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_4src(dc, OP_mls, Zda, Zda, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a MLS instruction.
This macro is used to encode the forms:
* MLS <Zda>.<Ts>, <Pg>/M, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_mls_vector
| #define INSTR_CREATE_mls_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_4src(dc, OP_mls, Rd, Rd, Rm, Rn, width) |
Creates a MLS vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. The instruction also reads this register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_mov_sve_pred
| #define INSTR_CREATE_mov_sve_pred | ( | dc, | |
| Pd, | |||
| Pn | |||
| ) |
Value:
INSTR_PRED( \
DR_PRED_MASKED)
Creates an MOV instruction.
This macro is used to encode the forms:
* MOV <Pd>.B, <Pn>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pn The first source predicate register, P (Predicate).
◆ INSTR_CREATE_movprfx_sve_pred
| #define INSTR_CREATE_movprfx_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_movprfx, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a MOVPRFX instruction.
This macro is used to encode the forms:
* MOVPRFX <Zd>.<Ts>, <Pg>/<ZM>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_movprfx_vector
| #define INSTR_CREATE_movprfx_vector | ( | dc, | |
| Zd, | |||
| Zn | |||
| ) | instr_create_1dst_1src(dc, OP_movprfx, Zd, Zn) |
Creates a MOVPRFX instruction.
This macro is used to encode the forms:
* MOVPRFX <Zd>, <Zn> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The first destination vector register, Z (Scalable) Zn The second source vector register, Z (Scalable)
◆ INSTR_CREATE_movs_sve_pred
| #define INSTR_CREATE_movs_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_ands, Pd, Pg, Pn, Pn), DR_PRED_MASKED) |
Creates an MOVS instruction.
This macro is used to encode the forms:
* MOVS <Pd>.B, <Pg>/Z, <Pn>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate).
◆ INSTR_CREATE_msb_sve_pred
| #define INSTR_CREATE_msb_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm, | |||
| Za | |||
| ) | INSTR_PRED(instr_create_1dst_4src(dc, OP_msb, Zdn, Zdn, Pg, Zm, Za), DR_PRED_MASKED) |
Creates a MSB instruction.
This macro is used to encode the forms:
* MSB <Zdn>.<Ts>, <Pg>/M, <Zm>.<Ts>, <Za>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable). Za The third source vector register, Z (Scalable).
◆ INSTR_CREATE_mul_sve_idx
| #define INSTR_CREATE_mul_sve_idx | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm, | |||
| index | |||
| ) | instr_create_1dst_3src(dc, OP_mul, Zd, Zn, Zm, index) |
Creates a MUL instruction.
This macro is used to encode the forms:
MUL <Zd>.D, <Zn>.D, <Zm>.D[<index>] MUL <Zd>.H, <Zn>.H, <Zm>.H[<index>] MUL <Zd>.S, <Zn>.S, <Zm>.S[<index>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z.d. Zn The first source vector register, Z.d. Zm The second source vector register, Z.d. index The immediate index for Zm.
◆ INSTR_CREATE_mul_sve_imm
| #define INSTR_CREATE_mul_sve_imm | ( | dc, | |
| Zdn, | |||
| simm | |||
| ) | instr_create_1dst_2src(dc, OP_mul, Zdn, Zdn, simm) |
Creates a MUL instruction.
This macro is used to encode the forms:
* MUL <Zdn>.<Ts>, <Zdn>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable) simm The signed immediate imm
◆ INSTR_CREATE_mul_sve_pred
| #define INSTR_CREATE_mul_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_mul, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a MUL instruction.
This macro is used to encode the forms:
* MUL <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_mul_sve_vector
| #define INSTR_CREATE_mul_sve_vector | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_mul, Zd, Zn, Zm) |
Creates a MUL instruction.
This macro is used to encode the forms:
MUL <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h, Z.s or Z.d. Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_mul_vector
| #define INSTR_CREATE_mul_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_mul, Rd, Rm, Rn, width) |
Creates a MUL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_nand_sve_pred
| #define INSTR_CREATE_nand_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_nand, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates a NAND instruction.
This macro is used to encode the forms:
* NAND <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_nands_sve_pred
| #define INSTR_CREATE_nands_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_nands, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates a NANDS instruction.
This macro is used to encode the forms:
* NANDS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_nbsl_sve
| #define INSTR_CREATE_nbsl_sve | ( | dc, | |
| Zdn, | |||
| Zm, | |||
| Zk | |||
| ) | instr_create_1dst_3src(dc, OP_nbsl, Zdn, Zdn, Zm, Zk) |
Creates a NBSL instruction.
This macro is used to encode the forms:
* NBSL <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Zm The second source vector register, Z (Scalable). Zk The third source vector register, Z (Scalable).
◆ INSTR_CREATE_neg_sve_pred
| #define INSTR_CREATE_neg_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_neg, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a NEG instruction.
This macro is used to encode the forms:
* NEG <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable)
◆ INSTR_CREATE_nmatch_sve_pred
| #define INSTR_CREATE_nmatch_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_nmatch, Pd, Pg, Zn, Zm), DR_PRED_MASKED) |
Creates a NMATCH instruction.
This macro is used to encode the forms:
NMATCH <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register. Can be P.b or P.h. Pg The governing predicate register, P (Predicate). Zn The first source vector register. Can be Z.b or Z.h. Zm The second source vector register. Can be Z.b or Z.h.
◆ INSTR_CREATE_nor_sve_pred
| #define INSTR_CREATE_nor_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_nor, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates a NOR instruction.
This macro is used to encode the forms:
* NOR <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_nors_sve_pred
| #define INSTR_CREATE_nors_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_nors, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates a NORS instruction.
This macro is used to encode the forms:
* NORS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_not_sve_pred_b
| #define INSTR_CREATE_not_sve_pred_b | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn | |||
| ) |
Value:
Creates a NOT instruction.
This macro is used to encode the forms:
* NOT <Pd>.B, <Pg>/Z, <Pn>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate).
◆ INSTR_CREATE_not_sve_pred_vec
| #define INSTR_CREATE_not_sve_pred_vec | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_not, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a NOT instruction.
This macro is used to encode the forms:
* NOT <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_orn_sve_imm
| #define INSTR_CREATE_orn_sve_imm | ( | dc, | |
| Zdn, | |||
| imm | |||
| ) | instr_create_1dst_2src(dc, OP_orr, Zdn, Zdn, opnd_invert_immed_int(imm)) |
Creates an ORN instruction.
This macro is used to encode the forms:
* ORN <Zdn>.<T>, <Zdn>.<T>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). imm The immediate logicalImm. The 13 bit immediate defining a 64, 32, 16 or 8 bit mask of 2, 4, 8, 16, 32 or 64 bit fields.
◆ INSTR_CREATE_orn_sve_pred
| #define INSTR_CREATE_orn_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_orn, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates an ORN instruction.
This macro is used to encode the forms:
* ORN <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_orn_vector
| #define INSTR_CREATE_orn_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_orn, Rd, Rm, Rn) |
Creates a ORN vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register.
◆ INSTR_CREATE_orns_sve_pred
| #define INSTR_CREATE_orns_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_orns, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates an ORNS instruction.
This macro is used to encode the forms:
* ORNS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_orr
| #define INSTR_CREATE_orr | ( | dc, | |
| rd, | |||
| rn, | |||
| rm_or_imm | |||
| ) |
Value:
(opnd_is_immed(rm_or_imm) \
? instr_create_1dst_2src((dc), OP_orr, (rd), (rn), (rm_or_imm)) \
: INSTR_CREATE_orr_shift(dc, rd, rn, rm_or_imm, OPND_CREATE_LSL(), \
OPND_CREATE_INT(0)))
Creates an ORR instruction with one output and two inputs.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. rd The output register. rn The first input register. rm_or_imm The second input register or immediate.
◆ INSTR_CREATE_orr_sve
| #define INSTR_CREATE_orr_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_orr, Zd, Zn, Zm) |
Creates an ORR instruction.
This macro is used to encode the forms:
* ORR <Zd>.D, <Zn>.D, <Zm>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_orr_sve_imm
| #define INSTR_CREATE_orr_sve_imm | ( | dc, | |
| Zdn, | |||
| imm | |||
| ) | instr_create_1dst_2src(dc, OP_orr, Zdn, Zdn, imm) |
Creates an ORR instruction.
This macro is used to encode the forms:
* ORR <Zdn>.<T>, <Zdn>.<T>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). imm The immediate logicalImm. The 13 bit immediate defining a 64, 32, 16 or 8 bit mask of 2, 4, 8, 16, 32 or 64 bit fields.
◆ INSTR_CREATE_orr_sve_pred
| #define INSTR_CREATE_orr_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_orr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an ORR instruction.
This macro is used to encode the forms:
* ORR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_orr_sve_pred_b
| #define INSTR_CREATE_orr_sve_pred_b | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_orr, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates an ORR instruction.
This macro is used to encode the forms:
* ORR <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_orr_vector
| #define INSTR_CREATE_orr_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_orr, Rd, Rm, Rn) |
Creates a ORR vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register.
◆ INSTR_CREATE_orrs_sve_pred
| #define INSTR_CREATE_orrs_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_orrs, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates an ORRS instruction.
This macro is used to encode the forms:
* ORRS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_orv_sve_pred
| #define INSTR_CREATE_orv_sve_pred | ( | dc, | |
| Vd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_orv, Vd, Pg, Zn), DR_PRED_MASKED) |
Creates an ORV instruction.
This macro is used to encode the forms:
* ORV <V><d>, <Pg>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vd The destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits), B (byte, 8 bits) or D (doubleword, 64 bits). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_pacda
| #define INSTR_CREATE_pacda | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_pacda, Rd, Rd, Rn) |
Creates a PACDA instruction.
This macro is used to encode the forms:
* PACDA <Xd>, <Xn|SP> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination register, X (Extended, 64 bits). Rn The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_pacdb
| #define INSTR_CREATE_pacdb | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_pacdb, Rd, Rd, Rn) |
Creates a PACDB instruction.
This macro is used to encode the forms:
* PACDB <Xd>, <Xn|SP> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination register, X (Extended, 64 bits). Rn The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_pacdza
| #define INSTR_CREATE_pacdza | ( | dc, | |
| Rd | |||
| ) | instr_create_1dst_1src(dc, OP_pacdza, Rd, Rd) |
Creates a PACDZA instruction.
This macro is used to encode the forms:
* PACDZA <Xd> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination register, X (Extended, 64 bits).
◆ INSTR_CREATE_pacdzb
| #define INSTR_CREATE_pacdzb | ( | dc, | |
| Rd | |||
| ) | instr_create_1dst_1src(dc, OP_pacdzb, Rd, Rd) |
Creates a PACDZB instruction.
This macro is used to encode the forms:
* PACDZB <Xd> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination register, X (Extended, 64 bits).
◆ INSTR_CREATE_pacga
| #define INSTR_CREATE_pacga | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_pacga, Rd, Rn, Rm) |
Creates a PACGA instruction.
This macro is used to encode the forms:
* PACGA <Xd>, <Xn>, <Xm|SP> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register, X (Extended, 64 bits). Rn The first source register, X (Extended, 64 bits). Rm The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_pacia
| #define INSTR_CREATE_pacia | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_pacia, Rd, Rd, Rn) |
Creates a PACIA instruction.
This macro is used to encode the forms:
* PACIA <Xd>, <Xn|SP> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination register, X (Extended, 64 bits). Rn The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_pacia1716
| #define INSTR_CREATE_pacia1716 | ( | dc | ) |
Value:
instr_create_1dst_2src(dc, OP_pacia1716, opnd_create_reg(DR_REG_X17), \
opnd_create_reg(DR_REG_X17), opnd_create_reg(DR_REG_X16))
Creates a PACIA1716 instruction.
This macro is used to encode the forms:
* PACIA1716 *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_paciasp
| #define INSTR_CREATE_paciasp | ( | dc | ) |
Value:
instr_create_1dst_2src(dc, OP_paciasp, opnd_create_reg(DR_REG_X30), \
Creates a PACIASP instruction.
This macro is used to encode the forms:
* PACIASP *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_paciaz
| #define INSTR_CREATE_paciaz | ( | dc | ) |
Value:
instr_create_1dst_1src(dc, OP_paciaz, opnd_create_reg(DR_REG_X30), \
opnd_create_reg(DR_REG_X30))
Creates a PACIAZ instruction.
This macro is used to encode the forms:
* PACIAZ *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_pacib
| #define INSTR_CREATE_pacib | ( | dc, | |
| Rd, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_pacib, Rd, Rd, Rn) |
Creates a PACIB instruction.
This macro is used to encode the forms:
* PACIB <Xd>, <Xn|SP> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination register, X (Extended, 64 bits). Rn The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_pacib1716
| #define INSTR_CREATE_pacib1716 | ( | dc | ) |
Value:
instr_create_1dst_2src(dc, OP_pacib1716, opnd_create_reg(DR_REG_X17), \
opnd_create_reg(DR_REG_X17), opnd_create_reg(DR_REG_X16))
Creates a PACIB1716 instruction.
This macro is used to encode the forms:
* PACIB1716 *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_pacibsp
| #define INSTR_CREATE_pacibsp | ( | dc | ) |
Value:
instr_create_1dst_2src(dc, OP_pacibsp, opnd_create_reg(DR_REG_X30), \
Creates a PACIBSP instruction.
This macro is used to encode the forms:
* PACIBSP *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_pacibz
| #define INSTR_CREATE_pacibz | ( | dc | ) |
Value:
instr_create_1dst_1src(dc, OP_pacibz, opnd_create_reg(DR_REG_X30), \
opnd_create_reg(DR_REG_X30))
Creates a PACIBZ instruction.
This macro is used to encode the forms:
* PACIBZ *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_paciza
| #define INSTR_CREATE_paciza | ( | dc, | |
| Rd | |||
| ) | instr_create_1dst_1src(dc, OP_paciza, Rd, Rd) |
Creates a PACIZA instruction.
This macro is used to encode the forms:
* PACIZA <Xd> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination register, X (Extended, 64 bits).
◆ INSTR_CREATE_pacizb
| #define INSTR_CREATE_pacizb | ( | dc, | |
| Rd | |||
| ) | instr_create_1dst_1src(dc, OP_pacizb, Rd, Rd) |
Creates a PACIZB instruction.
This macro is used to encode the forms:
* PACIZB <Xd> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination register, X (Extended, 64 bits).
◆ INSTR_CREATE_pfalse_sve
| #define INSTR_CREATE_pfalse_sve | ( | dc, | |
| Pd | |||
| ) | instr_create_1dst_0src(dc, OP_pfalse, Pd) |
Creates a PFALSE instruction.
This macro is used to encode the forms:
* PFALSE <Pd>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate).
◆ INSTR_CREATE_pfirst_sve
| #define INSTR_CREATE_pfirst_sve | ( | dc, | |
| Pdn, | |||
| Pg | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_pfirst, Pdn, Pg, Pdn), DR_PRED_MASKED) |
Creates a PFIRST instruction.
This macro is used to encode the forms:
* PFIRST <Pdn>.B, <Pg>, <Pdn>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pdn The source and destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate).
◆ INSTR_CREATE_pmul_sve
| #define INSTR_CREATE_pmul_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_pmul, Zd, Zn, Zm) |
Creates a PMUL instruction.
This macro is used to encode the forms:
* PMUL <Zd>.B, <Zn>.B, <Zm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_pmul_vector
| #define INSTR_CREATE_pmul_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_pmul, Rd, Rm, Rn, width) |
Creates a PMUL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use OPND_CREATE_BYTE().
◆ INSTR_CREATE_pmull2_vector
| #define INSTR_CREATE_pmull2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_pmull2, Rd, Rm, Rn, width) |
Creates a PMULL2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_pmull_vector
| #define INSTR_CREATE_pmull_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_pmull, Rd, Rm, Rn, width) |
Creates a PMULL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_pmullb_sve
| #define INSTR_CREATE_pmullb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_pmullb, Zd, Zn, Zm) |
Creates a PMULLB instruction.
This macro is used to encode the forms:
PMULLB <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h or Z.d. Zn The first source vector register. Can be Z.b or Z.s. Zm The second source vector register. Can be Z.b or Z.s.
◆ INSTR_CREATE_pmullt_sve
| #define INSTR_CREATE_pmullt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_pmullt, Zd, Zn, Zm) |
Creates a PMULLT instruction.
This macro is used to encode the forms:
PMULLT <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h or Z.d. Zn The first source vector register. Can be Z.b or Z.s. Zm The second source vector register. Can be Z.b or Z.s.
◆ INSTR_CREATE_pnext_sve
| #define INSTR_CREATE_pnext_sve | ( | dc, | |
| Pdn, | |||
| Pv | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_pnext, Pdn, Pv, Pdn), DR_PRED_MASKED) |
Creates a PNEXT instruction.
This macro is used to encode the forms:
* PNEXT <Pdn>.<Ts>, <Pv>, <Pdn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pdn The second source and destination predicate register, P (Predicate). Pv The first source predicate register, P (Predicate).
◆ INSTR_CREATE_prfb_sve_pred
| #define INSTR_CREATE_prfb_sve_pred | ( | dc, | |
| prfop, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_0dst_3src(dc, OP_prfb, prfop, Pg, Rn), DR_PRED_MASKED) |
Creates a PRFB instruction.
This macro is used to encode the forms:
* PRFB <prfop>, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
* PRFB <prfop>, <Pg>, [<Zn>.D{, #<imm>}]
* PRFB <prfop>, <Pg>, [<Zn>.S{, #<imm>}]
* PRFB <prfop>, <Pg>, [<Xn|SP>, <Zm>.D]
* PRFB <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <extend>]
* PRFB <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <extend>]
* PRFB <prfop>, <Pg>, [<Xn|SP>, <Xm>]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. prfop The prefetch operation. Pg The governing predicate register, P (Predicate). Rn The second source base register with an immediate offset, constructed with the function: For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm6, OPSZ_0) For the [<Zn>.S{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64(Zn, DR_REG_NULL, OPSZ_4, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_0, 0) For the [<Zn>.D{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64(Zn, DR_REG_NULL, OPSZ_8, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_0, 0) For the [<Xn|SP>, <Zm>.D] variant: opnd_create_vector_base_disp_aarch64(Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_0, 0) For the [<Xn|SP>, <Zm>.D, <extend>] variant: opnd_create_vector_base_disp_aarch64(Xn, Zm, OPSZ_8, extend, 0, 0, OPSZ_0, 0) For the [<Xn|SP>, <Zm>.S, <extend>] variant: opnd_create_vector_base_disp_aarch64(Xn, Zm, OPSZ_4, extend, 0, 0, OPSZ_0, 0) For the [<Xn|SP>, <Xm>] variant: opnd_create_base_disp_shift_aarch64(Xn, Xm, DR_EXTEND_UXTX, false, 0, 0, OPSZ_0, 0)
◆ INSTR_CREATE_prfd_sve_pred
| #define INSTR_CREATE_prfd_sve_pred | ( | dc, | |
| prfop, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_0dst_3src(dc, OP_prfd, prfop, Pg, Rn), DR_PRED_MASKED) |
Creates a PRFD instruction.
This macro is used to encode the forms:
* PRFD <prfop>, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
* PRFD <prfop>, <Pg>, [<Zn>.D{, #<imm>}]
* PRFD <prfop>, <Pg>, [<Zn>.S{, #<imm>}]
* PRFD <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, LSL #3]
* PRFD <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <extend> #3]
* PRFD <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <extend> #3]
* PRFD <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. prfop The prefetch operation. Pg The governing predicate register, P (Predicate). Rn The second source base register with an immediate offset, constructed with the function: For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm6, OPSZ_0) For the [<Zn>.S{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64(Zn, DR_REG_NULL, OPSZ_4, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_0, 0) For the [<Zn>.D{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64(Zn, DR_REG_NULL, OPSZ_8, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_0, 0) For the [<Xn|SP>, <Zm>.D] variant: opnd_create_vector_base_disp_aarch64(Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, true, 0, OPSZ_0, 3) For the [<Xn|SP>, <Zm>.D, <extend>] variant: opnd_create_vector_base_disp_aarch64(Xn, Zm, OPSZ_8, extend, true, 0, OPSZ_0, 3) For the [<Xn|SP>, <Zm>.S, <extend>] variant: opnd_create_vector_base_disp_aarch64(Xn, Zm, OPSZ_4, extend, true, 0, OPSZ_0, 3) For the [<Xn|SP>, <Xm>] variant: opnd_create_base_disp_shift_aarch64(Xn, Xm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_0, 3)
◆ INSTR_CREATE_prfh_sve_pred
| #define INSTR_CREATE_prfh_sve_pred | ( | dc, | |
| prfop, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_0dst_3src(dc, OP_prfh, prfop, Pg, Rn), DR_PRED_MASKED) |
Creates a PRFH instruction.
This macro is used to encode the forms:
* PRFH <prfop>, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
* PRFH <prfop>, <Pg>, [<Zn>.D{, #<imm>}]
* PRFH <prfop>, <Pg>, [<Zn>.S{, #<imm>}]
* PRFH <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, LSL #1]
* PRFH <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <extend> #1]
* PRFH <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <extend> #1]
* PRFH <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. prfop The prefetch operation. Pg The governing predicate register, P (Predicate). Rn The second source base register with an immediate offset, constructed with the function: For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm6, OPSZ_0) For the [<Zn>.S{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64(Zn, DR_REG_NULL, OPSZ_4, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_0, 0) For the [<Zn>.D{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64(Zn, DR_REG_NULL, OPSZ_8, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_0, 0) For the [<Xn|SP>, <Zm>.D] variant: opnd_create_vector_base_disp_aarch64(Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, true, 0, OPSZ_0, 1) For the [<Xn|SP>, <Zm>.D, <extend>] variant: opnd_create_vector_base_disp_aarch64(Xn, Zm, OPSZ_8, extend, true, 0, OPSZ_0, 1) For the [<Xn|SP>, <Zm>.S, <extend>] variant: opnd_create_vector_base_disp_aarch64(Xn, Zm, OPSZ_4, extend, true, 0, OPSZ_0, 1) For the [<Xn|SP>, <Xm>] variant: opnd_create_base_disp_shift_aarch64(Xn, Xm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_0, 1)
◆ INSTR_CREATE_prfw_sve_pred
| #define INSTR_CREATE_prfw_sve_pred | ( | dc, | |
| prfop, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_0dst_3src(dc, OP_prfw, prfop, Pg, Rn), DR_PRED_MASKED) |
Creates a PRFW instruction.
This macro is used to encode the forms:
* PRFW <prfop>, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
* PRFW <prfop>, <Pg>, [<Zn>.D{, #<imm>}]
* PRFW <prfop>, <Pg>, [<Zn>.S{, #<imm>}]
* PRFW <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, LSL #2]
* PRFW <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <extend> #2]
* PRFW <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <extend> #2]
* PRFW <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. prfop The prefetch operation. Pg The governing predicate register, P (Predicate). Rn The second source base register with an immediate offset, constructed with the function: For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm6, OPSZ_0) For the [<Zn>.S{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64(Zn, DR_REG_NULL, OPSZ_4, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_0, 0) For the [<Zn>.D{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64(Zn, DR_REG_NULL, OPSZ_8, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_0, 0) For the [<Xn|SP>, <Zm>.D] variant: opnd_create_vector_base_disp_aarch64(Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, true, 0, OPSZ_0, 2) For the [<Xn|SP>, <Zm>.D, <extend>] variant: opnd_create_vector_base_disp_aarch64(Xn, Zm, OPSZ_8, extend, true, 0, OPSZ_0, 2) For the [<Xn|SP>, <Zm>.S, <extend>] variant: opnd_create_vector_base_disp_aarch64(Xn, Zm, OPSZ_4, extend, true, 0, OPSZ_0, 2) For the [<Xn|SP>, <Xm>, LSL #2] variant: opnd_create_base_disp_shift_aarch64(Xn, Xm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_0, 2)
◆ INSTR_CREATE_psb_csync
| #define INSTR_CREATE_psb_csync | ( | dc | ) | instr_create_0dst_0src(dc, OP_psb) |
Creates a PSB instruction.
This macro is used to encode the forms:
* PSB CSYNC *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_ptest_sve_pred
| #define INSTR_CREATE_ptest_sve_pred | ( | dc, | |
| Pg, | |||
| Pn | |||
| ) | INSTR_PRED(instr_create_0dst_2src(dc, OP_ptest, Pg, Pn), DR_PRED_MASKED) |
Creates a PTEST instruction.
This macro is used to encode the forms:
* PTEST <Pg>, <Pn>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pg The governing predicate register, P (Predicate) Pn The first source predicate register, P (Predicate)
◆ INSTR_CREATE_ptrue_sve
| #define INSTR_CREATE_ptrue_sve | ( | dc, | |
| Pd, | |||
| pattern | |||
| ) | instr_create_1dst_1src(dc, OP_ptrue, Pd, pattern) |
Creates a PTRUE instruction.
This macro is used to encode the forms:
* PTRUE <Pd>.<Ts>{, <pattern>}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). pattern The predicate constraint, see dr_pred_constr_type_t.
◆ INSTR_CREATE_ptrues_sve
| #define INSTR_CREATE_ptrues_sve | ( | dc, | |
| Pd, | |||
| pattern | |||
| ) | instr_create_1dst_1src(dc, OP_ptrues, Pd, pattern) |
Creates a PTRUES instruction.
This macro is used to encode the forms:
* PTRUES <Pd>.<Ts>{, <pattern>}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). pattern The predicate constraint, see dr_pred_constr_type_t.
◆ INSTR_CREATE_punpkhi_sve
| #define INSTR_CREATE_punpkhi_sve | ( | dc, | |
| Pd, | |||
| Pn | |||
| ) | instr_create_1dst_1src(dc, OP_punpkhi, Pd, Pn) |
Creates a PUNPKHI instruction.
This macro is used to encode the forms:
* PUNPKHI <Pd>.H, <Pn>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pn The source predicate register, P (Predicate).
◆ INSTR_CREATE_punpklo_sve
| #define INSTR_CREATE_punpklo_sve | ( | dc, | |
| Pd, | |||
| Pn | |||
| ) | instr_create_1dst_1src(dc, OP_punpklo, Pd, Pn) |
Creates a PUNPKLO instruction.
This macro is used to encode the forms:
* PUNPKLO <Pd>.H, <Pn>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pn The source predicate register, P (Predicate).
◆ INSTR_CREATE_raddhn2_vector
| #define INSTR_CREATE_raddhn2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_raddhn2, Rd, Rm, Rn, width) |
Creates a RADDHN2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_raddhn_vector
| #define INSTR_CREATE_raddhn_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_raddhn, Rd, Rm, Rn, width) |
Creates a RADDHN vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_raddhnb_sve
| #define INSTR_CREATE_raddhnb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_raddhnb, Zd, Zn, Zm) |
Creates a RADDHNB instruction.
This macro is used to encode the forms:
RADDHNB <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.b, Z.h or Z.s. Zn The first source vector register. Can be Z.h, Z.s or Z.d. Zm The second source vector register. Can be Z.h, Z.s or Z.d.
◆ INSTR_CREATE_raddhnt_sve
| #define INSTR_CREATE_raddhnt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_raddhnt, Zd, Zd, Zn, Zm) |
Creates a RADDHNT instruction.
This macro is used to encode the forms:
RADDHNT <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The source and destination vector register. Can be Z.b, Z.h or Z.s. Zn The second source vector register. Can be Z.h, Z.s or Z.d. Zm The third source vector register. Can be Z.h, Z.s or Z.d.
◆ INSTR_CREATE_rax1
| #define INSTR_CREATE_rax1 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_3src(dc, OP_rax1, Rd, Rn, Rm, OPND_CREATE_DOUBLE()) |
Creates a RAX1 instruction.
This macro is used to encode the forms:
* RAX1 <Dd>.2D, <Dn>.2D, <Dm>.2D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register, Q (quadword, 128 bits) Rn The second source vector register, Q (quadword, 128 bits) Rm The third source vector register, Q (quadword, 128 bits)
◆ INSTR_CREATE_rax1_sve
| #define INSTR_CREATE_rax1_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_rax1, Zd, Zn, Zm) |
Creates a RAX1 instruction.
This macro is used to encode the forms:
* RAX1 <Zd>.D, <Zn>.D, <Zm>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_rbit_sve_pred
| #define INSTR_CREATE_rbit_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_rbit, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a RBIT instruction.
This macro is used to encode the forms:
* RBIT <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_rdffr_sve
| #define INSTR_CREATE_rdffr_sve | ( | dc, | |
| Pd | |||
| ) | instr_create_1dst_0src(dc, OP_rdffr, Pd) |
Creates a RDFFR instruction.
This macro is used to encode the forms:
* RDFFR <Pd>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate)
◆ INSTR_CREATE_rdffr_sve_pred
| #define INSTR_CREATE_rdffr_sve_pred | ( | dc, | |
| Pd, | |||
| Pg | |||
| ) | INSTR_PRED(instr_create_1dst_1src(dc, OP_rdffr, Pd, Pg), DR_PRED_MASKED) |
Creates a RDFFR instruction.
This macro is used to encode the forms:
* RDFFR <Pd>.B, <Pg>/Z *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate)
◆ INSTR_CREATE_rdffrs_sve_pred
| #define INSTR_CREATE_rdffrs_sve_pred | ( | dc, | |
| Pd, | |||
| Pg | |||
| ) | INSTR_PRED(instr_create_1dst_1src(dc, OP_rdffrs, Pd, Pg), DR_PRED_MASKED) |
Creates a RDFFRS instruction.
This macro is used to encode the forms:
* RDFFRS <Pd>.B, <Pg>/Z *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate) Pg The governing predicate register, P (Predicate)
◆ INSTR_CREATE_rdvl
| #define INSTR_CREATE_rdvl | ( | dc, | |
| Rd, | |||
| simm | |||
| ) | instr_create_1dst_1src(dc, OP_rdvl, Rd, simm) |
Creates a RDVL instruction.
This macro is used to encode the forms:
* RDVL <Xd>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register, X (Extended, 64 bits). simm The signed immediate imm.
◆ INSTR_CREATE_retaa
| #define INSTR_CREATE_retaa | ( | dc | ) |
Value:
instr_create_0dst_2src(dc, OP_retaa, opnd_create_reg(DR_REG_X30), \
Creates a RETAA instruction.
This macro is used to encode the forms:
* RETAA *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_retab
| #define INSTR_CREATE_retab | ( | dc | ) |
Value:
instr_create_0dst_2src(dc, OP_retab, opnd_create_reg(DR_REG_X30), \
Creates a RETAB instruction.
This macro is used to encode the forms:
* RETAB *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_rev_sve
| #define INSTR_CREATE_rev_sve | ( | dc, | |
| Zd, | |||
| Zn | |||
| ) | instr_create_1dst_1src(dc, OP_rev, Zd, Zn) |
Creates a REV instruction.
This macro is used to encode the forms:
* REV <Zd>.<Ts>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_rev_sve_pred
| #define INSTR_CREATE_rev_sve_pred | ( | dc, | |
| Pd, | |||
| Pn | |||
| ) | instr_create_1dst_1src(dc, OP_rev, Pd, Pn) |
Creates a REV instruction.
This macro is used to encode the forms:
* REV <Pd>.<Ts>, <Pn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pn The source predicate register, P (Predicate).
◆ INSTR_CREATE_revb_sve
| #define INSTR_CREATE_revb_sve | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_revb, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a REVB instruction.
This macro is used to encode the forms:
* REVB <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_revh_sve
| #define INSTR_CREATE_revh_sve | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_revh, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a REVH instruction.
This macro is used to encode the forms:
* REVH <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_revw_sve
| #define INSTR_CREATE_revw_sve | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_revw, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a REVW instruction.
This macro is used to encode the forms:
* REVW <Zd>.D, <Pg>/M, <Zn>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_rmif
| #define INSTR_CREATE_rmif | ( | dc, | |
| Rn, | |||
| shift, | |||
| mask | |||
| ) | instr_create_0dst_3src(dc, OP_rmif, Rn, shift, mask) |
Creates a RMIF instruction.
This macro is used to encode the forms:
* RMIF <Xn>, #<shift>, #<mask> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The source register, X (Extended, 64 bits). shift The immediate shift. mask The immediate mask.
◆ INSTR_CREATE_rshrnb_sve
| #define INSTR_CREATE_rshrnb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_2src(dc, OP_rshrnb, Zd, Zn, imm) |
Creates a RSHRNB instruction.
This macro is used to encode the forms:
RSHRNB <Zd>.<Ts>, <Zn>.<Tb>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.b, Z.h or Z.s. Zn The first source vector register. Can be Z.h, Z.s or Z.d. imm The immediate imm1.
◆ INSTR_CREATE_rshrnt_sve
| #define INSTR_CREATE_rshrnt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_3src(dc, OP_rshrnt, Zd, Zd, Zn, imm) |
Creates a RSHRNT instruction.
This macro is used to encode the forms:
RSHRNT <Zd>.<Ts>, <Zn>.<Tb>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The source and destination vector register. Can be Z.b, Z.h or Z.s. Zn The second source vector register. Can be Z.h, Z.s or Z.d. imm The immediate imm1.
◆ INSTR_CREATE_rsubhn2_vector
| #define INSTR_CREATE_rsubhn2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_rsubhn2, Rd, Rm, Rn, width) |
Creates a RSUBHN2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_rsubhn_vector
| #define INSTR_CREATE_rsubhn_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_rsubhn, Rd, Rm, Rn, width) |
Creates a RSUBHN vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_rsubhnb_sve
| #define INSTR_CREATE_rsubhnb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_rsubhnb, Zd, Zn, Zm) |
Creates a RSUBHNB instruction.
This macro is used to encode the forms:
RSUBHNB <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.b, Z.h or Z.s. Zn The first source vector register. Can be Z.h, Z.s or Z.d. Zm The second source vector register. Can be Z.h, Z.s or Z.d.
◆ INSTR_CREATE_rsubhnt_sve
| #define INSTR_CREATE_rsubhnt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_rsubhnt, Zd, Zd, Zn, Zm) |
Creates a RSUBHNT instruction.
This macro is used to encode the forms:
RSUBHNT <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The source and destination vector register. Can be Z.b, Z.h or Z.s. Zn The second source vector register. Can be Z.h, Z.s or Z.d. Zm The third source vector register. Can be Z.h, Z.s or Z.d.
◆ INSTR_CREATE_saba_sve
| #define INSTR_CREATE_saba_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_saba, Zda, Zda, Zn, Zm) |
Creates a SABA instruction.
This macro is used to encode the forms:
* SABA <Zda>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_saba_vector
| #define INSTR_CREATE_saba_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_saba, Rd, Rm, Rn, width) |
Creates a SABA vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_sabal2_vector
| #define INSTR_CREATE_sabal2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_sabal2, Rd, Rm, Rn, width) |
Creates a SABAL2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_sabal_vector
| #define INSTR_CREATE_sabal_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_sabal, Rd, Rm, Rn, width) |
Creates a SABAL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_sabalb_sve
| #define INSTR_CREATE_sabalb_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_sabalb, Zda, Zda, Zn, Zm) |
Creates a SABALB instruction.
This macro is used to encode the forms:
SABALB <Zda>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h or Z.s. Zm The third source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_sabalt_sve
| #define INSTR_CREATE_sabalt_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_sabalt, Zda, Zda, Zn, Zm) |
Creates a SABALT instruction.
This macro is used to encode the forms:
SABALT <Zda>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h or Z.s. Zm The third source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_sabd_sve_pred
| #define INSTR_CREATE_sabd_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_sabd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a SABD instruction.
This macro is used to encode the forms:
* SABD <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_sabd_vector
| #define INSTR_CREATE_sabd_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_sabd, Rd, Rm, Rn, width) |
Creates a SABD vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_sabdl2_vector
| #define INSTR_CREATE_sabdl2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_sabdl2, Rd, Rm, Rn, width) |
Creates a SABDL2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_sabdl_vector
| #define INSTR_CREATE_sabdl_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_sabdl, Rd, Rm, Rn, width) |
Creates a SABDL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_sabdlb_sve
| #define INSTR_CREATE_sabdlb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_sabdlb, Zd, Zn, Zm) |
Creates a SABDLB instruction.
This macro is used to encode the forms:
SABDLB <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h or Z.s. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_sabdlt_sve
| #define INSTR_CREATE_sabdlt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_sabdlt, Zd, Zn, Zm) |
Creates a SABDLT instruction.
This macro is used to encode the forms:
SABDLT <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h or Z.s. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_sadalp_sve_pred
| #define INSTR_CREATE_sadalp_sve_pred | ( | dc, | |
| Zda, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_sadalp, Zda, Zda, Pg, Zn), DR_PRED_MASKED) |
Creates a SADALP instruction.
This macro is used to encode the forms:
SADALP <Zda>.<Ts>, <Pg>/M, <Zn>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zn The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_saddl2_vector
| #define INSTR_CREATE_saddl2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_saddl2, Rd, Rm, Rn, width) |
Creates a SADDL2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_saddl_vector
| #define INSTR_CREATE_saddl_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_saddl, Rd, Rm, Rn, width) |
Creates a SADDL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_saddlb_sve
| #define INSTR_CREATE_saddlb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_saddlb, Zd, Zn, Zm) |
Creates a SADDLB instruction.
This macro is used to encode the forms:
SADDLB <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h or Z.s. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_saddlbt_sve
| #define INSTR_CREATE_saddlbt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_saddlbt, Zd, Zn, Zm) |
Creates a SADDLBT instruction.
This macro is used to encode the forms:
SADDLBT <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h or Z.s. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_saddlt_sve
| #define INSTR_CREATE_saddlt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_saddlt, Zd, Zn, Zm) |
Creates a SADDLT instruction.
This macro is used to encode the forms:
SADDLT <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h or Z.s. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_saddv_sve_pred
| #define INSTR_CREATE_saddv_sve_pred | ( | dc, | |
| Vd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_saddv, Vd, Pg, Zn), DR_PRED_MASKED) |
Creates a SADDV instruction.
This macro is used to encode the forms:
* SADDV <Dd>, <Pg>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vd The destination register, D (doubleword, 64 bits). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_saddw2_vector
| #define INSTR_CREATE_saddw2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_saddw2, Rd, Rm, Rn, width) |
Creates a SADDW2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_saddw_vector
| #define INSTR_CREATE_saddw_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_saddw, Rd, Rm, Rn, width) |
Creates a SADDW vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_saddwb_sve
| #define INSTR_CREATE_saddwb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_saddwb, Zd, Zn, Zm) |
Creates a SADDWB instruction.
This macro is used to encode the forms:
SADDWB <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.h, Z.s or Z.d. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_saddwt_sve
| #define INSTR_CREATE_saddwt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_saddwt, Zd, Zn, Zm) |
Creates a SADDWT instruction.
This macro is used to encode the forms:
SADDWT <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.h, Z.s or Z.d. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_sbclb_sve
| #define INSTR_CREATE_sbclb_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_sbclb, Zda, Zda, Zn, Zm) |
Creates a SBCLB instruction.
This macro is used to encode the forms:
* SBCLB <Zda>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_sbclt_sve
| #define INSTR_CREATE_sbclt_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_sbclt, Zda, Zda, Zn, Zm) |
Creates a SBCLT instruction.
This macro is used to encode the forms:
* SBCLT <Zda>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_scvtf_scalar
| #define INSTR_CREATE_scvtf_scalar | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src(dc, OP_scvtf, Rd, Rm) |
Creates an SCVTF floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd Floating-point output register. Rm Integer input register.
◆ INSTR_CREATE_scvtf_scalar_fixed
| #define INSTR_CREATE_scvtf_scalar_fixed | ( | dc, | |
| Rd, | |||
| Rm, | |||
| fbits | |||
| ) | instr_create_1dst_2src(dc, OP_scvtf, Rd, Rm, fbits) |
Creates an SCVTF scalar floating-point to fixed-point convert instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd Floating-point output register. Rm Integer input register. fbits The number of bits after the binary point in the fixed-point input.
◆ INSTR_CREATE_scvtf_sve_pred
| #define INSTR_CREATE_scvtf_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_scvtf, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a SCVTF instruction.
This macro is used to encode the forms:
* SCVTF <Zd>.H, <Pg>/M, <Zn>.H * SCVTF <Zd>.D, <Pg>/M, <Zn>.S * SCVTF <Zd>.H, <Pg>/M, <Zn>.S * SCVTF <Zd>.S, <Pg>/M, <Zn>.S * SCVTF <Zd>.D, <Pg>/M, <Zn>.D * SCVTF <Zd>.H, <Pg>/M, <Zn>.D * SCVTF <Zd>.S, <Pg>/M, <Zn>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_scvtf_vector
| #define INSTR_CREATE_scvtf_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| width | |||
| ) | instr_create_1dst_2src(dc, OP_scvtf, Rd, Rm, width) |
Creates an SCVTF vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. width Immediate int of the vector element width. Must be OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE() or OPND_CREATE_HALF().
◆ INSTR_CREATE_scvtf_vector_fixed
| #define INSTR_CREATE_scvtf_vector_fixed | ( | dc, | |
| Rd, | |||
| Rm, | |||
| width, | |||
| fbits | |||
| ) | instr_create_1dst_3src(dc, OP_scvtf, Rd, Rm, width, fbits) |
Creates an SCVTF vector floating-point to fixed-point convert instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The input register. width The vector element width. Must be OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE() or OPND_CREATE_HALF(). fbits The number of bits after the binary point in the fixed-point destination element.
◆ INSTR_CREATE_sdiv_sve_pred
| #define INSTR_CREATE_sdiv_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_sdiv, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a SDIV instruction.
This macro is used to encode the forms:
* SDIV <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_sdivr_sve_pred
| #define INSTR_CREATE_sdivr_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_sdivr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a SDIVR instruction.
This macro is used to encode the forms:
* SDIVR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_sdot_sve
| #define INSTR_CREATE_sdot_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_sdot, Zda, Zda, Zn, Zm) |
Creates a SDOT instruction.
This macro is used to encode the forms:
* SDOT <Zda>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_sdot_sve_idx
| #define INSTR_CREATE_sdot_sve_idx | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| index | |||
| ) | instr_create_1dst_4src(dc, OP_sdot, Zda, Zda, Zn, Zm, index) |
Creates a SDOT instruction.
This macro is used to encode the forms:
* SDOT <Zda>.D, <Zn>.H, <Zm>.H[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable). index The immediate index for Zm. In the range 0-1 for the 64-bit (D) variant or 0-3 for the 32-bit (S) variant.
◆ INSTR_CREATE_sdot_vector
| #define INSTR_CREATE_sdot_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_4src(dc, OP_sdot, Rd, Rd, Rn, Rm, OPND_CREATE_BYTE()) |
Creates a SDOT instruction.
This macro is used to encode the forms:
* SDOT <Sd>.<Ts>, <Bn>.<Tb>, <Bm>.<Tb> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm The third source vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits)
◆ INSTR_CREATE_sdot_vector_indexed
| #define INSTR_CREATE_sdot_vector_indexed | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| index | |||
| ) | instr_create_1dst_5src(dc, OP_sdot, Rd, Rd, Rn, Rm, index, OPND_CREATE_BYTE()) |
Creates a SDOT instruction.
This macro is used to encode the forms:
* SDOT <Sd>.<Ts>, <Bn>.<Tb>, <Bm>.4B[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm The third source vector register, Q (quadword, 128 bits) index The immediate index for Rm
◆ INSTR_CREATE_sel_sve_pred
| #define INSTR_CREATE_sel_sve_pred | ( | dc, | |
| Pd, | |||
| Pg, | |||
| Pn, | |||
| Pm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_sel, Pd, Pg, Pn, Pm), DR_PRED_MASKED) |
Creates a SEL instruction.
This macro is used to encode the forms:
* SEL <Pd>.B, <Pg>, <Pn>.B, <Pm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pg The governing predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_sel_sve_vector
| #define INSTR_CREATE_sel_sve_vector | ( | dc, | |
| Zd, | |||
| Pv, | |||
| Zn, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_sel, Zd, Pv, Zn, Zm), DR_PRED_MASKED) |
Creates a SEL instruction.
This macro is used to encode the forms:
* SEL <Zd>.<Ts>, <Pv>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pv The governing predicate register, P (Predicate). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_setf16
| #define INSTR_CREATE_setf16 | ( | dc, | |
| Rn | |||
| ) | instr_create_0dst_1src(dc, OP_setf16, Rn) |
Creates a SETF16 instruction.
This macro is used to encode the forms:
* SETF16 <Wn> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The source register, W (Word, 32 bits).
◆ INSTR_CREATE_setf8
| #define INSTR_CREATE_setf8 | ( | dc, | |
| Rn | |||
| ) | instr_create_0dst_1src(dc, OP_setf8, Rn) |
Creates a SETF8 instruction.
This macro is used to encode the forms:
* SETF8 <Wn> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The source register, W (Word, 32 bits).
◆ INSTR_CREATE_setffr_sve
| #define INSTR_CREATE_setffr_sve | ( | dc | ) | instr_create_0dst_0src(dc, OP_setffr) |
Creates a SETFFR instruction.
This macro is used to encode the forms:
* SETFFR *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_sha512h
| #define INSTR_CREATE_sha512h | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_4src(dc, OP_sha512h, Rd, Rd, Rn, Rm, Rm_elsz) |
Creates a SHA512H instruction.
This macro is used to encode the forms:
* SHA512H <Qd>, <Qn>, <Dm>.2D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination register, Q (quadword, 128 bits) Rn The second source register, Q (quadword, 128 bits) Rm The third source vector register, Q (quadword, 128 bits) Rm_elsz The element size for Rm, OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_sha512h2
| #define INSTR_CREATE_sha512h2 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_4src(dc, OP_sha512h2, Rd, Rd, Rn, Rm, Rm_elsz) |
Creates a SHA512H2 instruction.
This macro is used to encode the forms:
* SHA512H2 <Qd>, <Qn>, <Dm>.2D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination register, Q (quadword, 128 bits) Rn The second source register, Q (quadword, 128 bits) Rm The third source vector register, Q (quadword, 128 bits) Rm_elsz The element size for Rm, OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_sha512su0
| #define INSTR_CREATE_sha512su0 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rn_elsz | |||
| ) | instr_create_1dst_3src(dc, OP_sha512su0, Rd, Rd, Rn, Rn_elsz) |
Creates a SHA512SU0 instruction.
This macro is used to encode the forms:
* SHA512SU0 <Dd>.2D, <Dn>.2D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination vector register, Q (quadword, 128 bits) Rn The second source vector register, Q (quadword, 128 bits) Rn_elsz The element size for Rn, OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_sha512su1
| #define INSTR_CREATE_sha512su1 | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_4src(dc, OP_sha512su1, Rd, Rd, Rn, Rm, Rm_elsz) |
Creates a SHA512SU1 instruction.
This macro is used to encode the forms:
* SHA512SU1 <Dd>.2D, <Dn>.2D, <Dm>.2D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination vector register, Q (quadword, 128 bits) Rn The second source vector register, Q (quadword, 128 bits) Rm The third source vector register, Q (quadword, 128 bits) Rm_elsz The element size for Rm, OPND_CREATE_DOUBLE()
◆ INSTR_CREATE_shadd_sve_pred
| #define INSTR_CREATE_shadd_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_shadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a SHADD instruction.
This macro is used to encode the forms:
SHADD <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_shadd_vector
| #define INSTR_CREATE_shadd_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_shadd, Rd, Rm, Rn, width) |
Creates a SHADD vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_shrnb_sve
| #define INSTR_CREATE_shrnb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_2src(dc, OP_shrnb, Zd, Zn, imm) |
Creates a SHRNB instruction.
This macro is used to encode the forms:
SHRNB <Zd>.<Ts>, <Zn>.<Tb>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.b, Z.h or Z.s. Zn The first source vector register. Can be Z.h, Z.s or Z.d. imm The immediate imm1.
◆ INSTR_CREATE_shrnt_sve
| #define INSTR_CREATE_shrnt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_3src(dc, OP_shrnt, Zd, Zd, Zn, imm) |
Creates a SHRNT instruction.
This macro is used to encode the forms:
SHRNT <Zd>.<Ts>, <Zn>.<Tb>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The source and destination vector register. Can be Z.b, Z.h or Z.s. Zn The second source vector register. Can be Z.h, Z.s or Z.d. imm The immediate imm1.
◆ INSTR_CREATE_shsub_sve_pred
| #define INSTR_CREATE_shsub_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_shsub, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a SHSUB instruction.
This macro is used to encode the forms:
SHSUB <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_shsub_vector
| #define INSTR_CREATE_shsub_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_shsub, Rd, Rm, Rn, width) |
Creates a SHSUB vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_shsubr_sve_pred
| #define INSTR_CREATE_shsubr_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_shsubr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a SHSUBR instruction.
This macro is used to encode the forms:
SHSUBR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_sli_sve
| #define INSTR_CREATE_sli_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_3src(dc, OP_sli, Zd, Zd, Zn, imm) |
Creates a SLI instruction.
This macro is used to encode the forms:
SLI <Zd>.<Ts>, <Zn>.<Ts>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. imm The immediate imm.
◆ INSTR_CREATE_sli_vector
| #define INSTR_CREATE_sli_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| width, | |||
| shift | |||
| ) | instr_create_1dst_3src(dc, OP_sli, Rd, Rn, width, shift) |
Creates an SLI shift left and insert instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rn The input register. width The output vector element width. Use OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE(). shift The number of bits to shift the result by.
◆ INSTR_CREATE_sm3partw1_vector
| #define INSTR_CREATE_sm3partw1_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_3src(dc, OP_sm3partw1, Rd, Rn, Rm, Rm_elsz) |
Creates a SM3PARTW1 instruction.
This macro is used to encode the forms:
* SM3PARTW1 <Sd>.4S, <Sn>.4S, <Sm>.4S *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register, Q (quadword, 128 bits) Rn The second source vector register, Q (quadword, 128 bits) Rm The third source vector register, Q (quadword, 128 bits) Rm_elsz The element size for Rm, OPND_CREATE_SINGLE()
◆ INSTR_CREATE_sm3partw2_vector
| #define INSTR_CREATE_sm3partw2_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_3src(dc, OP_sm3partw2, Rd, Rn, Rm, Rm_elsz) |
Creates a SM3PARTW2 instruction.
This macro is used to encode the forms:
* SM3PARTW2 <Sd>.4S, <Sn>.4S, <Sm>.4S *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register, Q (quadword, 128 bits) Rn The second source vector register, Q (quadword, 128 bits) Rm The third source vector register, Q (quadword, 128 bits) Rm_elsz The element size for Rm, OPND_CREATE_SINGLE()
◆ INSTR_CREATE_sm3ss1_vector
| #define INSTR_CREATE_sm3ss1_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Ra, | |||
| Ra_elsz | |||
| ) | instr_create_1dst_4src(dc, OP_sm3ss1, Rd, Rn, Rm, Ra, Ra_elsz) |
Creates a SM3SS1 instruction.
This macro is used to encode the forms:
* SM3SS1 <Sd>.4S, <Sn>.4S, <Sm>.4S, <Sa>.4S *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register, Q (quadword, 128 bits) Rn The second source vector register, Q (quadword, 128 bits) Rm The third source vector register, Q (quadword, 128 bits) Ra The fourth source vector register, Q (quadword, 128 bits) Ra_elsz The element size for Ra, OPND_CREATE_SINGLE()
◆ INSTR_CREATE_sm3tt1a_vector_indexed
| #define INSTR_CREATE_sm3tt1a_vector_indexed | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| imm2, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_4src(dc, OP_sm3tt1a, Rd, Rn, Rm, imm2, Rm_elsz) |
Creates a SM3TT1A instruction.
This macro is used to encode the forms:
* SM3TT1A <Sd>.4S, <Sn>.4S, <Sm>.S[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register, Q (quadword, 128 bits) Rn The second source vector register, Q (quadword, 128 bits) Rm The third source vector register, Q (quadword, 128 bits) imm2 The immediate index for Rm Rm_elsz The element size for Rm, OPND_CREATE_SINGLE()
◆ INSTR_CREATE_sm3tt1b_vector_indexed
| #define INSTR_CREATE_sm3tt1b_vector_indexed | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| imm2, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_4src(dc, OP_sm3tt1b, Rd, Rn, Rm, imm2, Rm_elsz) |
Creates a SM3TT1B instruction.
This macro is used to encode the forms:
* SM3TT1B <Sd>.4S, <Sn>.4S, <Sm>.S[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register, Q (quadword, 128 bits) Rn The second source vector register, Q (quadword, 128 bits) Rm The third source vector register, Q (quadword, 128 bits) imm2 The immediate index for Rm Rm_elsz The element size for Rm, OPND_CREATE_SINGLE()
◆ INSTR_CREATE_sm3tt2a_vector_indexed
| #define INSTR_CREATE_sm3tt2a_vector_indexed | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| imm2, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_4src(dc, OP_sm3tt2a, Rd, Rn, Rm, imm2, Rm_elsz) |
Creates a SM3TT2A instruction.
This macro is used to encode the forms:
* SM3TT2A <Sd>.4S, <Sn>.4S, <Sm>.S[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register, Q (quadword, 128 bits) Rn The second source vector register, Q (quadword, 128 bits) Rm The third source vector register, Q (quadword, 128 bits) imm2 The immediate index for Rm Rm_elsz The element size for Rm, OPND_CREATE_SINGLE()
◆ INSTR_CREATE_sm3tt2b_vector_indexed
| #define INSTR_CREATE_sm3tt2b_vector_indexed | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| imm2, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_4src(dc, OP_sm3tt2b, Rd, Rn, Rm, imm2, Rm_elsz) |
Creates a SM3TT2B instruction.
This macro is used to encode the forms:
* SM3TT2B <Sd>.4S, <Sn>.4S, <Sm>.S[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register, Q (quadword, 128 bits) Rn The second source vector register, Q (quadword, 128 bits) Rm The third source vector register, Q (quadword, 128 bits) imm2 The immediate index for Rm Rm_elsz The element size for Rm, OPND_CREATE_SINGLE()
◆ INSTR_CREATE_sm4e_sve
| #define INSTR_CREATE_sm4e_sve | ( | dc, | |
| Zdn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_sm4e, Zdn, Zdn, Zm) |
Creates a SM4E instruction.
This macro is used to encode the forms:
* SM4E <Zdn>.S, <Zdn>.S, <Zm>.S *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_sm4e_vector
| #define INSTR_CREATE_sm4e_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rn_elsz | |||
| ) | instr_create_1dst_2src(dc, OP_sm4e, Rd, Rn, Rn_elsz) |
Creates a SM4E instruction.
This macro is used to encode the forms:
* SM4E <Sd>.4S, <Sn>.4S *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register, Q (quadword, 128 bits) Rn The second source vector register, Q (quadword, 128 bits) Rn_elsz The element size for Rn, OPND_CREATE_SINGLE()
◆ INSTR_CREATE_sm4ekey_sve
| #define INSTR_CREATE_sm4ekey_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_sm4ekey, Zd, Zn, Zm) |
Creates a SM4EKEY instruction.
This macro is used to encode the forms:
* SM4EKEY <Zd>.S, <Zn>.S, <Zm>.S *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_sm4ekey_vector
| #define INSTR_CREATE_sm4ekey_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| Rm_elsz | |||
| ) | instr_create_1dst_3src(dc, OP_sm4ekey, Rd, Rn, Rm, Rm_elsz) |
Creates a SM4EKEY instruction.
This macro is used to encode the forms:
* SM4EKEY <Sd>.4S, <Sn>.4S, <Sm>.4S *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register, Q (quadword, 128 bits) Rn The second source vector register, Q (quadword, 128 bits) Rm The third source vector register, Q (quadword, 128 bits) Rm_elsz The element size for Rm, OPND_CREATE_SINGLE()
◆ INSTR_CREATE_smax_sve
| #define INSTR_CREATE_smax_sve | ( | dc, | |
| Zdn, | |||
| simm | |||
| ) | instr_create_1dst_2src(dc, OP_smax, Zdn, Zdn, simm) |
Creates a SMAX instruction.
This macro is used to encode the forms:
* SMAX <Zdn>.<Ts>, <Zdn>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable) simm The signed immediate imm
◆ INSTR_CREATE_smax_sve_pred
| #define INSTR_CREATE_smax_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_smax, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a SMAX instruction.
This macro is used to encode the forms:
* SMAX <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_smax_vector
| #define INSTR_CREATE_smax_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_smax, Rd, Rm, Rn, width) |
Creates a SMAX vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_smaxp_sve_pred
| #define INSTR_CREATE_smaxp_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_smaxp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a SMAXP instruction.
This macro is used to encode the forms:
SMAXP <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_smaxp_vector
| #define INSTR_CREATE_smaxp_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_smaxp, Rd, Rm, Rn, width) |
Creates a SMAXP vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_smaxv_sve_pred
| #define INSTR_CREATE_smaxv_sve_pred | ( | dc, | |
| Vd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_smaxv, Vd, Pg, Zn), DR_PRED_MASKED) |
Creates a SMAXV instruction.
This macro is used to encode the forms:
* SMAXV <V><d>, <Pg>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vd The destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits), B (byte, 8 bits) or D (doubleword, 64 bits). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_smin_sve
| #define INSTR_CREATE_smin_sve | ( | dc, | |
| Zdn, | |||
| simm | |||
| ) | instr_create_1dst_2src(dc, OP_smin, Zdn, Zdn, simm) |
Creates a SMIN instruction.
This macro is used to encode the forms:
* SMIN <Zdn>.<Ts>, <Zdn>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable) simm The signed immediate imm
◆ INSTR_CREATE_smin_sve_pred
| #define INSTR_CREATE_smin_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_smin, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a SMIN instruction.
This macro is used to encode the forms:
* SMIN <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_smin_vector
| #define INSTR_CREATE_smin_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_smin, Rd, Rm, Rn, width) |
Creates a SMIN vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_sminp_sve_pred
| #define INSTR_CREATE_sminp_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_sminp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a SMINP instruction.
This macro is used to encode the forms:
SMINP <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_sminp_vector
| #define INSTR_CREATE_sminp_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_sminp, Rd, Rm, Rn, width) |
Creates a SMINP vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_sminv_sve_pred
| #define INSTR_CREATE_sminv_sve_pred | ( | dc, | |
| Vd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_sminv, Vd, Pg, Zn), DR_PRED_MASKED) |
Creates a SMINV instruction.
This macro is used to encode the forms:
* SMINV <V><d>, <Pg>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vd The destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits), B (byte, 8 bits) or D (doubleword, 64 bits). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_smlal2_vector
| #define INSTR_CREATE_smlal2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_smlal2, Rd, Rm, Rn, width) |
Creates a SMLAL2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_smlal_vector
| #define INSTR_CREATE_smlal_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_smlal, Rd, Rm, Rn, width) |
Creates a SMLAL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_smlalb_sve
| #define INSTR_CREATE_smlalb_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_smlalb, Zda, Zda, Zn, Zm) |
Creates a SMLALB instruction.
This macro is used to encode the forms:
SMLALB <Zda>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h or Z.s. Zm The third source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_smlalb_sve_idx_vector
| #define INSTR_CREATE_smlalb_sve_idx_vector | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| i2 | |||
| ) | instr_create_1dst_4src(dc, OP_smlalb, Zda, Zda, Zn, Zm, i2) |
Creates a SMLALB instruction.
This macro is used to encode the forms:
SMLALB <Zda>.D, <Zn>.S, <Zm>.S[<index>] SMLALB <Zda>.S, <Zn>.H, <Zm>.H[<index>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.d or Z.s. Zn The second source vector register. Can be Z.s or Z.h. Zm The third source vector register. Can be Z.s or Z.h. i2 The immediate index for Zm.
◆ INSTR_CREATE_smlalt_sve
| #define INSTR_CREATE_smlalt_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_smlalt, Zda, Zda, Zn, Zm) |
Creates a SMLALT instruction.
This macro is used to encode the forms:
SMLALT <Zda>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h or Z.s. Zm The third source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_smlalt_sve_idx_vector
| #define INSTR_CREATE_smlalt_sve_idx_vector | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| i2 | |||
| ) | instr_create_1dst_4src(dc, OP_smlalt, Zda, Zda, Zn, Zm, i2) |
Creates a SMLALT instruction.
This macro is used to encode the forms:
SMLALT <Zda>.D, <Zn>.S, <Zm>.S[<index>] SMLALT <Zda>.S, <Zn>.H, <Zm>.H[<index>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.d or Z.s. Zn The second source vector register. Can be Z.s or Z.h. Zm The third source vector register. Can be Z.s or Z.h. i2 The immediate index for Zm.
◆ INSTR_CREATE_smlsl2_vector
| #define INSTR_CREATE_smlsl2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_smlsl2, Rd, Rm, Rn, width) |
Creates a SMLSL2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_smlsl_vector
| #define INSTR_CREATE_smlsl_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_smlsl, Rd, Rm, Rn, width) |
Creates a SMLSL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_smlslb_sve
| #define INSTR_CREATE_smlslb_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_smlslb, Zda, Zda, Zn, Zm) |
Creates a SMLSLB instruction.
This macro is used to encode the forms:
SMLSLB <Zda>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h or Z.s. Zm The third source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_smlslb_sve_idx_vector
| #define INSTR_CREATE_smlslb_sve_idx_vector | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| i2 | |||
| ) | instr_create_1dst_4src(dc, OP_smlslb, Zda, Zda, Zn, Zm, i2) |
Creates a SMLSLB instruction.
This macro is used to encode the forms:
SMLSLB <Zda>.D, <Zn>.S, <Zm>.S[<index>] SMLSLB <Zda>.S, <Zn>.H, <Zm>.H[<index>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.d or Z.s. Zn The second source vector register. Can be Z.s or Z.h. Zm The third source vector register. Can be Z.s or Z.h. i2 The immediate index for Zm.
◆ INSTR_CREATE_smlslt_sve
| #define INSTR_CREATE_smlslt_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_smlslt, Zda, Zda, Zn, Zm) |
Creates a SMLSLT instruction.
This macro is used to encode the forms:
SMLSLT <Zda>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h or Z.s. Zm The third source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_smlslt_sve_idx_vector
| #define INSTR_CREATE_smlslt_sve_idx_vector | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| i2 | |||
| ) | instr_create_1dst_4src(dc, OP_smlslt, Zda, Zda, Zn, Zm, i2) |
Creates a SMLSLT instruction.
This macro is used to encode the forms:
SMLSLT <Zda>.D, <Zn>.S, <Zm>.S[<index>] SMLSLT <Zda>.S, <Zn>.H, <Zm>.H[<index>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.d or Z.s. Zn The second source vector register. Can be Z.s or Z.h. Zm The third source vector register. Can be Z.s or Z.h. i2 The immediate index for Zm.
◆ INSTR_CREATE_smmla_sve
| #define INSTR_CREATE_smmla_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_smmla, Zda, Zda, Zn, Zm) |
Creates a SMMLA instruction.
This macro is used to encode the forms:
* SMMLA <Zda>.S, <Zn>.B, <Zm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_smmla_vector
| #define INSTR_CREATE_smmla_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_4src(dc, OP_smmla, Rd, Rd, Rn, Rm, OPND_CREATE_BYTE()) |
Creates a SMMLA instruction.
This macro is used to encode the forms:
* SMMLA <Vd>.4S, <Vn>.16B, <Vm>.16B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The third source and destination vector register, Q (quadword, 128 bits). Rn The first source vector register, Q (quadword, 128 bits). Rm The second source vector register, Q (quadword, 128 bits).
◆ INSTR_CREATE_smulh_sve_pred
| #define INSTR_CREATE_smulh_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_smulh, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a SMULH instruction.
This macro is used to encode the forms:
* SMULH <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_smull2_vector
| #define INSTR_CREATE_smull2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_smull2, Rd, Rm, Rn, width) |
Creates a SMULL2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_smull_vector
| #define INSTR_CREATE_smull_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_smull, Rd, Rm, Rn, width) |
Creates a SMULL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_smullb_sve
| #define INSTR_CREATE_smullb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_smullb, Zd, Zn, Zm) |
Creates a SMULLB instruction.
This macro is used to encode the forms:
SMULLB <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h or Z.s. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_smullb_sve_idx_vector
| #define INSTR_CREATE_smullb_sve_idx_vector | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm, | |||
| i2 | |||
| ) | instr_create_1dst_3src(dc, OP_smullb, Zd, Zn, Zm, i2) |
Creates a SMULLB instruction.
This macro is used to encode the forms:
SMULLB <Zd>.D, <Zn>.S, <Zm>.S[<index>] SMULLB <Zd>.S, <Zn>.H, <Zm>.H[<index>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.d or Z.s. Zn The first source vector register. Can be Z.s or Z.h. Zm The second source vector register. Can be Z.s or Z.h. i2 The immediate index for Zm.
◆ INSTR_CREATE_smullt_sve
| #define INSTR_CREATE_smullt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_smullt, Zd, Zn, Zm) |
Creates a SMULLT instruction.
This macro is used to encode the forms:
SMULLT <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h or Z.s. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_smullt_sve_idx_vector
| #define INSTR_CREATE_smullt_sve_idx_vector | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm, | |||
| i2 | |||
| ) | instr_create_1dst_3src(dc, OP_smullt, Zd, Zn, Zm, i2) |
Creates a SMULLT instruction.
This macro is used to encode the forms:
SMULLT <Zd>.D, <Zn>.S, <Zm>.S[<index>] SMULLT <Zd>.S, <Zn>.H, <Zm>.H[<index>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.d or Z.s. Zn The first source vector register. Can be Z.s or Z.h. Zm The second source vector register. Can be Z.s or Z.h. i2 The immediate index for Zm.
◆ INSTR_CREATE_splice_sve_con
| #define INSTR_CREATE_splice_sve_con | ( | dc, | |
| Zd, | |||
| Pv, | |||
| Zn | |||
| ) |
Value:
INSTR_PRED(instr_create_1dst_3src(dc, OP_splice, Zd, Pv, Zn, \
opnd_create_increment_reg(Zn, 1)), \
DR_PRED_MASKED)
Creates a SPLICE instruction.
This macro is used to encode the form:
SPLICE <Zd>.<Ts>, <Pv>, { <Zn1>.<Ts>, <Zn2>.<Ts> }
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pv The governing predicate register, P (Predicate). Zn The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
The Zn2 parameter is derived from Zn.
◆ INSTR_CREATE_splice_sve_des
| #define INSTR_CREATE_splice_sve_des | ( | dc, | |
| Zdn, | |||
| Pv, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_splice, Zdn, Pv, Zdn, Zm), DR_PRED_MASKED) |
Creates a SPLICE instruction (destructive).
This macro is used to encode the form:
* SPLICE <Zdn>.<Ts>, <Pv>, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The second source and destination vector register, Z (Scalable). Pv The governing predicate register, P (Predicate). Zm The last source vector register, Z (Scalable).
◆ INSTR_CREATE_sqabs_sve_pred
| #define INSTR_CREATE_sqabs_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_sqabs, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a SQABS instruction.
This macro is used to encode the forms:
SQABS <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zn The source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_sqadd_sve
| #define INSTR_CREATE_sqadd_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_sqadd, Zd, Zn, Zm) |
Creates a SQADD instruction.
This macro is used to encode the forms:
* SQADD <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The first destination vector register, Z (Scalable) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_sqadd_sve_shift
| #define INSTR_CREATE_sqadd_sve_shift | ( | dc, | |
| Zdn, | |||
| imm, | |||
| shift | |||
| ) | instr_create_1dst_4src(dc, OP_sqadd, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift) |
Creates a SQADD instruction.
This macro is used to encode the forms:
* SQADD <Zdn>.<Ts>, <Zdn>.<Ts>, #<imm>, <shift> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and first destination vector register, Z (Scalable) imm The immediate imm shift The immediate shiftOp for imm8
◆ INSTR_CREATE_sqadd_vector
| #define INSTR_CREATE_sqadd_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_sqadd, Rd, Rm, Rn, width) |
Creates a SQADD vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_sqcadd_sve
| #define INSTR_CREATE_sqcadd_sve | ( | dc, | |
| Zdn, | |||
| Zm, | |||
| rot | |||
| ) | instr_create_1dst_3src(dc, OP_sqcadd, Zdn, Zdn, Zm, rot) |
Creates a SQCADD instruction.
This macro is used to encode the forms:
SQCADD <Zdn>.<Ts>, <Zdn>.<Ts>, <Zm>.<Ts>, <const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. rot The immediate imm.
◆ INSTR_CREATE_sqdecb
| #define INSTR_CREATE_sqdecb | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_sqdecb, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
Creates a SQDECB instruction.
This macro is used to encode the forms:
* SQDECB <Xdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register, X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_sqdecb_wide
| #define INSTR_CREATE_sqdecb_wide | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) |
Value:
instr_create_1dst_4src(dc, OP_sqdecb, Rdn, \
opnd_create_reg(opnd_get_reg(Rdn) - DR_REG_X0 + DR_REG_W0), \
pattern, OPND_CREATE_MUL(), imm)
Creates a SQDECB instruction.
This macro is used to encode the forms:
* SQDECB <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register, X (Extended, 64 bits). The 32 bit result from the source register is sign extended to 64 bits. pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_sqdecd
| #define INSTR_CREATE_sqdecd | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_sqdecd, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
Creates a SQDECD instruction.
This macro is used to encode the forms:
* SQDECD <Xdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register, X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_sqdecd_sve
| #define INSTR_CREATE_sqdecd_sve | ( | dc, | |
| Zdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_sqdecd, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
Creates a SQDECD instruction.
This macro is used to encode the forms:
* SQDECD <Zdn>.D{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z (Scalable). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_sqdecd_wide
| #define INSTR_CREATE_sqdecd_wide | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) |
Value:
instr_create_1dst_4src(dc, OP_sqdecd, Rdn, \
opnd_create_reg(opnd_get_reg(Rdn) - DR_REG_X0 + DR_REG_W0), \
pattern, OPND_CREATE_MUL(), imm)
Creates a SQDECD instruction.
This macro is used to encode the forms:
* SQDECD <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register, X (Extended, 64 bits). The 32 bit result from the source register is sign extended to 64 bits. pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_sqdech
| #define INSTR_CREATE_sqdech | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_sqdech, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
Creates a SQDECH instruction.
This macro is used to encode the forms:
* SQDECH <Xdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register, X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_sqdech_sve
| #define INSTR_CREATE_sqdech_sve | ( | dc, | |
| Zdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_sqdech, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
Creates a SQDECH instruction.
This macro is used to encode the forms:
* SQDECH <Zdn>.H{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z (Scalable). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_sqdech_wide
| #define INSTR_CREATE_sqdech_wide | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) |
Value:
instr_create_1dst_4src(dc, OP_sqdech, Rdn, \
opnd_create_reg(opnd_get_reg(Rdn) - DR_REG_X0 + DR_REG_W0), \
pattern, OPND_CREATE_MUL(), imm)
Creates a SQDECH instruction.
This macro is used to encode the forms:
* SQDECH <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register, X (Extended, 64 bits). The 32 bit result from the source register is sign extended to 64 bits. pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_sqdecp_sve
| #define INSTR_CREATE_sqdecp_sve | ( | dc, | |
| Rdn, | |||
| Pm | |||
| ) | instr_create_1dst_2src(dc, OP_sqdecp, Rdn, Rdn, Pm) |
Creates a SQDECP instruction.
This macro is used to encode the forms:
* SQDECP <Xdn>, <Pm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register, X (Extended, 64 bits). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_sqdecp_sve_vector
| #define INSTR_CREATE_sqdecp_sve_vector | ( | dc, | |
| Zdn, | |||
| Pm | |||
| ) | instr_create_1dst_2src(dc, OP_sqdecp, Zdn, Zdn, Pm) |
Creates a SQDECP instruction.
This macro is used to encode the forms:
* SQDECP <Zdn>.<Ts>, <Pm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z (Scalable). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_sqdecp_sve_wide
| #define INSTR_CREATE_sqdecp_sve_wide | ( | dc, | |
| Rdn, | |||
| Pm | |||
| ) |
Value:
instr_create_1dst_2src(dc, OP_sqdecp, Rdn, Pm, \
opnd_create_reg(opnd_get_reg(Rdn) - DR_REG_X0 + DR_REG_W0))
Creates a SQDECP instruction.
This macro is used to encode the forms:
* SQDECP <Xdn>, <Pm>.<Ts>, <Wdn> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The second source and destination register, X (Extended, 64 bits). Pm The first source predicate register, P (Predicate).
◆ INSTR_CREATE_sqdecw
| #define INSTR_CREATE_sqdecw | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_sqdecw, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
Creates a SQDECW instruction.
This macro is used to encode the forms:
* SQDECW <Xdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register, X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_sqdecw_sve
| #define INSTR_CREATE_sqdecw_sve | ( | dc, | |
| Zdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_sqdecw, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
Creates a SQDECW instruction.
This macro is used to encode the forms:
* SQDECW <Zdn>.S{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z (Scalable). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_sqdecw_wide
| #define INSTR_CREATE_sqdecw_wide | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) |
Value:
instr_create_1dst_4src(dc, OP_sqdecw, Rdn, \
opnd_create_reg(opnd_get_reg(Rdn) - DR_REG_X0 + DR_REG_W0), \
pattern, OPND_CREATE_MUL(), imm)
Creates a SQDECW instruction.
This macro is used to encode the forms:
* SQDECW <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register, X (Extended, 64 bits). The 32 bit result from the source register is sign extended to 64 bits. pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_sqdmlal2_vector
| #define INSTR_CREATE_sqdmlal2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_sqdmlal2, Rd, Rm, Rn, width) |
Creates a SQDMLAL2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_sqdmlal_vector
| #define INSTR_CREATE_sqdmlal_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_sqdmlal, Rd, Rm, Rn, width) |
Creates a SQDMLAL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_sqdmlalb_sve
| #define INSTR_CREATE_sqdmlalb_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_sqdmlalb, Zda, Zda, Zn, Zm) |
Creates a SQDMLALB instruction.
This macro is used to encode the forms:
SQDMLALB <Zda>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h or Z.s. Zm The third source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_sqdmlalb_sve_idx_vector
| #define INSTR_CREATE_sqdmlalb_sve_idx_vector | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| i2 | |||
| ) | instr_create_1dst_4src(dc, OP_sqdmlalb, Zda, Zda, Zn, Zm, i2) |
Creates a SQDMLALB instruction.
This macro is used to encode the forms:
SQDMLALB <Zda>.D, <Zn>.S, <Zm>.S[<index>] SQDMLALB <Zda>.S, <Zn>.H, <Zm>.H[<index>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.d or Z.s. Zn The second source vector register. Can be Z.s or Z.h. Zm The third source vector register. Can be Z.s or Z.h. i2 The immediate index for Zm.
◆ INSTR_CREATE_sqdmlalbt_sve
| #define INSTR_CREATE_sqdmlalbt_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_sqdmlalbt, Zda, Zda, Zn, Zm) |
Creates a SQDMLALBT instruction.
This macro is used to encode the forms:
SQDMLALBT <Zda>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h or Z.s. Zm The third source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_sqdmlalt_sve
| #define INSTR_CREATE_sqdmlalt_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_sqdmlalt, Zda, Zda, Zn, Zm) |
Creates a SQDMLALT instruction.
This macro is used to encode the forms:
SQDMLALT <Zda>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h or Z.s. Zm The third source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_sqdmlalt_sve_idx_vector
| #define INSTR_CREATE_sqdmlalt_sve_idx_vector | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| i2 | |||
| ) | instr_create_1dst_4src(dc, OP_sqdmlalt, Zda, Zda, Zn, Zm, i2) |
Creates a SQDMLALT instruction.
This macro is used to encode the forms:
SQDMLALT <Zda>.D, <Zn>.S, <Zm>.S[<index>] SQDMLALT <Zda>.S, <Zn>.H, <Zm>.H[<index>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.d or Z.s. Zn The second source vector register. Can be Z.s or Z.h. Zm The third source vector register. Can be Z.s or Z.h. i2 The immediate index for Zm.
◆ INSTR_CREATE_sqdmlsl2_vector
| #define INSTR_CREATE_sqdmlsl2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_sqdmlsl2, Rd, Rm, Rn, width) |
Creates a SQDMLSL2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_sqdmlsl_vector
| #define INSTR_CREATE_sqdmlsl_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_sqdmlsl, Rd, Rm, Rn, width) |
Creates a SQDMLSL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_sqdmlslb_sve
| #define INSTR_CREATE_sqdmlslb_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_sqdmlslb, Zda, Zda, Zn, Zm) |
Creates a SQDMLSLB instruction.
This macro is used to encode the forms:
SQDMLSLB <Zda>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h or Z.s. Zm The third source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_sqdmlslb_sve_idx_vector
| #define INSTR_CREATE_sqdmlslb_sve_idx_vector | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| i2 | |||
| ) | instr_create_1dst_4src(dc, OP_sqdmlslb, Zda, Zda, Zn, Zm, i2) |
Creates a SQDMLSLB instruction.
This macro is used to encode the forms:
SQDMLSLB <Zda>.D, <Zn>.S, <Zm>.S[<index>] SQDMLSLB <Zda>.S, <Zn>.H, <Zm>.H[<index>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.d or Z.s. Zn The second source vector register. Can be Z.s or Z.h. Zm The third source vector register. Can be Z.s or Z.h. i2 The immediate index for Zm.
◆ INSTR_CREATE_sqdmlslbt_sve
| #define INSTR_CREATE_sqdmlslbt_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_sqdmlslbt, Zda, Zda, Zn, Zm) |
Creates a SQDMLSLBT instruction.
This macro is used to encode the forms:
SQDMLSLBT <Zda>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h or Z.s. Zm The third source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_sqdmlslt_sve
| #define INSTR_CREATE_sqdmlslt_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_sqdmlslt, Zda, Zda, Zn, Zm) |
Creates a SQDMLSLT instruction.
This macro is used to encode the forms:
SQDMLSLT <Zda>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h or Z.s. Zm The third source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_sqdmlslt_sve_idx_vector
| #define INSTR_CREATE_sqdmlslt_sve_idx_vector | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| i2 | |||
| ) | instr_create_1dst_4src(dc, OP_sqdmlslt, Zda, Zda, Zn, Zm, i2) |
Creates a SQDMLSLT instruction.
This macro is used to encode the forms:
SQDMLSLT <Zda>.D, <Zn>.S, <Zm>.S[<index>] SQDMLSLT <Zda>.S, <Zn>.H, <Zm>.H[<index>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.d or Z.s. Zn The second source vector register. Can be Z.s or Z.h. Zm The third source vector register. Can be Z.s or Z.h. i2 The immediate index for Zm.
◆ INSTR_CREATE_sqdmulh_sve
| #define INSTR_CREATE_sqdmulh_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_sqdmulh, Zd, Zn, Zm) |
Creates a SQDMULH instruction.
This macro is used to encode the forms:
* SQDMULH <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_sqdmulh_sve_idx
| #define INSTR_CREATE_sqdmulh_sve_idx | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm, | |||
| i1 | |||
| ) | instr_create_1dst_3src(dc, OP_sqdmulh, Zd, Zn, Zm, i1) |
Creates a SQDMULH instruction.
This macro is used to encode the forms:
SQDMULH <Zd>.D, <Zn>.D, <Zm>.D[<index>] SQDMULH <Zd>.S, <Zn>.S, <Zm>.S[<index>] SQDMULH <Zd>.H, <Zn>.H, <Zm>.H[<index>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.d, Z.s or Z.h. Zn The first source vector register. Can be Z.d, Z.s or Z.h. Zm The second source vector register. Can be Z.d, Z.s or Z.h. i1 The immediate index for Zm.
◆ INSTR_CREATE_sqdmulh_vector
| #define INSTR_CREATE_sqdmulh_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_sqdmulh, Rd, Rm, Rn, width) |
Creates a SQDMULH vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_sqdmull2_vector
| #define INSTR_CREATE_sqdmull2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_sqdmull2, Rd, Rm, Rn, width) |
Creates a SQDMULL2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_sqdmull_vector
| #define INSTR_CREATE_sqdmull_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_sqdmull, Rd, Rm, Rn, width) |
Creates a SQDMULL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_sqdmullb_sve
| #define INSTR_CREATE_sqdmullb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_sqdmullb, Zd, Zn, Zm) |
Creates a SQDMULLB instruction.
This macro is used to encode the forms:
SQDMULLB <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h or Z.s. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_sqdmullb_sve_idx_vector
| #define INSTR_CREATE_sqdmullb_sve_idx_vector | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm, | |||
| i2 | |||
| ) | instr_create_1dst_3src(dc, OP_sqdmullb, Zd, Zn, Zm, i2) |
Creates a SQDMULLB instruction.
This macro is used to encode the forms:
SQDMULLB <Zd>.D, <Zn>.S, <Zm>.S[<index>] SQDMULLB <Zd>.S, <Zn>.H, <Zm>.H[<index>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.d or Z.s. Zn The first source vector register. Can be Z.s or Z.h. Zm The second source vector register. Can be Z.s or Z.h. i2 The immediate index for Zm.
◆ INSTR_CREATE_sqdmullt_sve
| #define INSTR_CREATE_sqdmullt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_sqdmullt, Zd, Zn, Zm) |
Creates a SQDMULLT instruction.
This macro is used to encode the forms:
SQDMULLT <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h or Z.s. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_sqdmullt_sve_idx_vector
| #define INSTR_CREATE_sqdmullt_sve_idx_vector | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm, | |||
| i2 | |||
| ) | instr_create_1dst_3src(dc, OP_sqdmullt, Zd, Zn, Zm, i2) |
Creates a SQDMULLT instruction.
This macro is used to encode the forms:
SQDMULLT <Zd>.D, <Zn>.S, <Zm>.S[<index>] SQDMULLT <Zd>.S, <Zn>.H, <Zm>.H[<index>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.d or Z.s. Zn The first source vector register. Can be Z.s or Z.h. Zm The second source vector register. Can be Z.s or Z.h. i2 The immediate index for Zm.
◆ INSTR_CREATE_sqincb
| #define INSTR_CREATE_sqincb | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_sqincb, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
Creates a SQINCB instruction.
This macro is used to encode the forms:
* SQINCB <Xdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register, X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_sqincb_wide
| #define INSTR_CREATE_sqincb_wide | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) |
Value:
instr_create_1dst_4src(dc, OP_sqincb, Rdn, \
opnd_create_reg(opnd_get_reg(Rdn) - DR_REG_X0 + DR_REG_W0), \
pattern, OPND_CREATE_MUL(), imm)
Creates a SQINCB instruction.
This macro is used to encode the forms:
* SQINCB <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register, X (Extended, 64 bits). The 32 bit result from the source register is sign extended to 64 bits. pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_sqincd
| #define INSTR_CREATE_sqincd | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_sqincd, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
Creates a SQINCD instruction.
This macro is used to encode the forms:
* SQINCD <Xdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register, X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_sqincd_sve
| #define INSTR_CREATE_sqincd_sve | ( | dc, | |
| Zdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_sqincd, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
Creates a SQINCD instruction.
This macro is used to encode the forms:
* SQINCD <Zdn>.D{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z (Scalable). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_sqincd_wide
| #define INSTR_CREATE_sqincd_wide | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) |
Value:
instr_create_1dst_4src(dc, OP_sqincd, Rdn, \
opnd_create_reg(opnd_get_reg(Rdn) - DR_REG_X0 + DR_REG_W0), \
pattern, OPND_CREATE_MUL(), imm)
Creates a SQINCD instruction.
This macro is used to encode the forms:
* SQINCD <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register, X (Extended, 64 bits). The 32 bit result from the source register is sign extended to 64 bits. pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_sqinch
| #define INSTR_CREATE_sqinch | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_sqinch, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
Creates a SQINCH instruction.
This macro is used to encode the forms:
* SQINCH <Xdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register, X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_sqinch_sve
| #define INSTR_CREATE_sqinch_sve | ( | dc, | |
| Zdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_sqinch, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
Creates a SQINCH instruction.
This macro is used to encode the forms:
* SQINCH <Zdn>.H{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z (Scalable). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_sqinch_wide
| #define INSTR_CREATE_sqinch_wide | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) |
Value:
instr_create_1dst_4src(dc, OP_sqinch, Rdn, \
opnd_create_reg(opnd_get_reg(Rdn) - DR_REG_X0 + DR_REG_W0), \
pattern, OPND_CREATE_MUL(), imm)
Creates a SQINCH instruction.
This macro is used to encode the forms:
* SQINCH <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register, X (Extended, 64 bits). The 32 bit result from the source register is sign extended to 64 bits. pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_sqincp_sve
| #define INSTR_CREATE_sqincp_sve | ( | dc, | |
| Rdn, | |||
| Pm | |||
| ) | instr_create_1dst_2src(dc, OP_sqincp, Rdn, Rdn, Pm) |
Creates a SQINCP instruction.
This macro is used to encode the forms:
* SQINCP <Xdn>, <Pm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register, X (Extended, 64 bits). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_sqincp_sve_vector
| #define INSTR_CREATE_sqincp_sve_vector | ( | dc, | |
| Zdn, | |||
| Pm | |||
| ) | instr_create_1dst_2src(dc, OP_sqincp, Zdn, Zdn, Pm) |
Creates a SQINCP instruction.
This macro is used to encode the forms:
* SQINCP <Zdn>.<Ts>, <Pm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z (Scalable). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_sqincp_sve_wide
| #define INSTR_CREATE_sqincp_sve_wide | ( | dc, | |
| Rdn, | |||
| Pm | |||
| ) |
Value:
instr_create_1dst_2src(dc, OP_sqincp, Rdn, Pm, \
opnd_create_reg(opnd_get_reg(Rdn) - DR_REG_X0 + DR_REG_W0))
Creates a SQINCP instruction.
This macro is used to encode the forms:
* SQINCP <Xdn>, <Pm>.<Ts>, <Wdn> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The second source and destination register, X (Extended, 64 bits). The 32 bit result from the source register is sign extended to 64 bits. Pm The first source predicate register, P (Predicate).
◆ INSTR_CREATE_sqincw
| #define INSTR_CREATE_sqincw | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_sqincw, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
Creates a SQINCW instruction.
This macro is used to encode the forms:
* SQINCW <Xdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register, X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_sqincw_sve
| #define INSTR_CREATE_sqincw_sve | ( | dc, | |
| Zdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_sqincw, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
Creates a SQINCW instruction.
This macro is used to encode the forms:
* SQINCW <Zdn>.S{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z (Scalable). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_sqincw_wide
| #define INSTR_CREATE_sqincw_wide | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) |
Value:
instr_create_1dst_4src(dc, OP_sqincw, Rdn, \
opnd_create_reg(opnd_get_reg(Rdn) - DR_REG_X0 + DR_REG_W0), \
pattern, OPND_CREATE_MUL(), imm)
Creates a SQINCW instruction.
This macro is used to encode the forms:
* SQINCW <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register, X (Extended, 64 bits). The 32 bit result from the source register is sign extended to 64 bits. pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_sqneg_sve_pred
| #define INSTR_CREATE_sqneg_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_sqneg, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a SQNEG instruction.
This macro is used to encode the forms:
SQNEG <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zn The source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_sqrdcmlah_sve
| #define INSTR_CREATE_sqrdcmlah_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| rot | |||
| ) | instr_create_1dst_4src(dc, OP_sqrdcmlah, Zda, Zda, Zn, Zm, rot) |
Creates a SQRDCMLAH instruction.
This macro is used to encode the forms:
SQRDCMLAH <Zda>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts>, <const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. Zm The third source vector register. Can be Z.b, Z.h, Z.s or Z.d. rot The immediate rotation which must be 0, 90, 180 or 270.
◆ INSTR_CREATE_sqrdcmlah_sve_idx_imm_vector
| #define INSTR_CREATE_sqrdcmlah_sve_idx_imm_vector | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| i1, | |||
| rot | |||
| ) | instr_create_1dst_5src(dc, OP_sqrdcmlah, Zda, Zda, Zn, Zm, i1, rot) |
Creates a SQRDCMLAH instruction.
This macro is used to encode the forms:
SQRDCMLAH <Zda>.S, <Zn>.S, <Zm>.S[<imm>], <const> SQRDCMLAH <Zda>.H, <Zn>.H, <Zm>.H[<imm>], <const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.s or Z.h. Zn The second source vector register. Can be Z.s or Z.h. Zm The third source vector register. Can be Z.s or Z.h. i1 The immediate index for Zm. rot The immediate rotation which must be 0, 90, 180 or 270.
◆ INSTR_CREATE_sqrdmlah_sve
| #define INSTR_CREATE_sqrdmlah_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_sqrdmlah, Zda, Zda, Zn, Zm) |
Creates a SQRDMLAH instruction.
This macro is used to encode the forms:
* SQRDMLAH <Zda>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_sqrdmlah_sve_idx
| #define INSTR_CREATE_sqrdmlah_sve_idx | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| i1 | |||
| ) | instr_create_1dst_4src(dc, OP_sqrdmlah, Zda, Zda, Zn, Zm, i1) |
Creates a SQRDMLAH instruction.
This macro is used to encode the forms:
SQRDMLAH <Zda>.D, <Zn>.D, <Zm>.D[<index>] SQRDMLAH <Zda>.S, <Zn>.S, <Zm>.S[<index>] SQRDMLAH <Zda>.H, <Zn>.H, <Zm>.H[<index>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.d, Z.s or Z.h. Zn The second source vector register. Can be Z.d, Z.s or Z.h. Zm The third source vector register. Can be Z.d, Z.s or Z.h. i1 The immediate index for Zm.
◆ INSTR_CREATE_sqrdmlsh_scalar
| #define INSTR_CREATE_sqrdmlsh_scalar | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_3src(dc, OP_sqrdmlsh, Rd, Rd, Rm, Rn) |
Creates a SQRDMLSH scalar instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register.
◆ INSTR_CREATE_sqrdmlsh_scalar_idx
| #define INSTR_CREATE_sqrdmlsh_scalar_idx | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| index, | |||
| elsz | |||
| ) | instr_create_1dst_5src(dc, OP_sqrdmlsh, Rd, Rd, Rm, Rn, index, elsz) |
Creates a SQRDMLSH scalar indexed instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. index The first input register's vector element index. elsz The vector element size. Use either OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_sqrdmlsh_sve
| #define INSTR_CREATE_sqrdmlsh_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_sqrdmlsh, Zda, Zda, Zn, Zm) |
Creates a SQRDMLSH instruction.
This macro is used to encode the forms:
* SQRDMLSH <Zda>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_sqrdmlsh_sve_idx
| #define INSTR_CREATE_sqrdmlsh_sve_idx | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| i1 | |||
| ) | instr_create_1dst_4src(dc, OP_sqrdmlsh, Zda, Zda, Zn, Zm, i1) |
Creates a SQRDMLSH instruction.
This macro is used to encode the forms:
SQRDMLSH <Zda>.D, <Zn>.D, <Zm>.D[<index>] SQRDMLSH <Zda>.S, <Zn>.S, <Zm>.S[<index>] SQRDMLSH <Zda>.H, <Zn>.H, <Zm>.H[<index>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.d, Z.s or Z.h. Zn The second source vector register. Can be Z.d, Z.s or Z.h. Zm The third source vector register. Can be Z.d, Z.s or Z.h. i1 The immediate index for Zm.
◆ INSTR_CREATE_sqrdmlsh_vector
| #define INSTR_CREATE_sqrdmlsh_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| elsz | |||
| ) | instr_create_1dst_4src(dc, OP_sqrdmlsh, Rd, Rd, Rm, Rn, elsz) |
Creates a SQRDMLSH vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. elsz The vector element size. Use either OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_sqrdmlsh_vector_idx
| #define INSTR_CREATE_sqrdmlsh_vector_idx | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| index, | |||
| elsz | |||
| ) | instr_create_1dst_5src(dc, OP_sqrdmlsh, Rd, Rd, Rm, Rn, index, elsz) |
Creates a SQRDMLSH vector indexed instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. index The first input register's vector element index. elsz The vector element size. Use either OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_sqrdmulh_sve
| #define INSTR_CREATE_sqrdmulh_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_sqrdmulh, Zd, Zn, Zm) |
Creates a SQRDMULH instruction.
This macro is used to encode the forms:
* SQRDMULH <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_sqrdmulh_sve_idx
| #define INSTR_CREATE_sqrdmulh_sve_idx | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm, | |||
| i1 | |||
| ) | instr_create_1dst_3src(dc, OP_sqrdmulh, Zd, Zn, Zm, i1) |
Creates a SQRDMULH instruction.
This macro is used to encode the forms:
SQRDMULH <Zd>.D, <Zn>.D, <Zm>.D[<index>] SQRDMULH <Zd>.S, <Zn>.S, <Zm>.S[<index>] SQRDMULH <Zd>.H, <Zn>.H, <Zm>.H[<index>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.d, Z.s or Z.h. Zn The first source vector register. Can be Z.d, Z.s or Z.h. Zm The second source vector register. Can be Z.d, Z.s or Z.h. i1 The immediate index for Zm.
◆ INSTR_CREATE_sqrdmulh_vector
| #define INSTR_CREATE_sqrdmulh_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_sqrdmulh, Rd, Rm, Rn, width) |
Creates a SQRDMULH vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_sqrshl_sve_pred
| #define INSTR_CREATE_sqrshl_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_sqrshl, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a SQRSHL instruction.
This macro is used to encode the forms:
SQRSHL <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_sqrshl_vector
| #define INSTR_CREATE_sqrshl_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_sqrshl, Rd, Rm, Rn, width) |
Creates a SQRSHL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_sqrshlr_sve_pred
| #define INSTR_CREATE_sqrshlr_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_sqrshlr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a SQRSHLR instruction.
This macro is used to encode the forms:
SQRSHLR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_sqrshrnb_sve
| #define INSTR_CREATE_sqrshrnb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_2src(dc, OP_sqrshrnb, Zd, Zn, imm) |
Creates a SQRSHRNB instruction.
This macro is used to encode the forms:
SQRSHRNB <Zd>.<Ts>, <Zn>.<Tb>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.b, Z.h or Z.s. Zn The first source vector register. Can be Z.h, Z.s or Z.d. imm The immediate imm1.
◆ INSTR_CREATE_sqrshrnt_sve
| #define INSTR_CREATE_sqrshrnt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_3src(dc, OP_sqrshrnt, Zd, Zd, Zn, imm) |
Creates a SQRSHRNT instruction.
This macro is used to encode the forms:
SQRSHRNT <Zd>.<Ts>, <Zn>.<Tb>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The source and destination vector register. Can be Z.b, Z.h or Z.s. Zn The second source vector register. Can be Z.h, Z.s or Z.d. imm The immediate imm1.
◆ INSTR_CREATE_sqrshrunb_sve
| #define INSTR_CREATE_sqrshrunb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_2src(dc, OP_sqrshrunb, Zd, Zn, imm) |
Creates a SQRSHRUNB instruction.
This macro is used to encode the forms:
SQRSHRUNB <Zd>.<Ts>, <Zn>.<Tb>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.b, Z.h or Z.s. Zn The first source vector register. Can be Z.h, Z.s or Z.d. imm The immediate imm1.
◆ INSTR_CREATE_sqrshrunt_sve
| #define INSTR_CREATE_sqrshrunt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_3src(dc, OP_sqrshrunt, Zd, Zd, Zn, imm) |
Creates a SQRSHRUNT instruction.
This macro is used to encode the forms:
SQRSHRUNT <Zd>.<Ts>, <Zn>.<Tb>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The source and destination vector register. Can be Z.b, Z.h or Z.s. Zn The second source vector register. Can be Z.h, Z.s or Z.d. imm The immediate imm1.
◆ INSTR_CREATE_sqshl_sve_pred
| #define INSTR_CREATE_sqshl_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm_imm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_sqshl, Zdn, Pg, Zdn, Zm_imm), DR_PRED_MASKED) |
Creates a SQSHL instruction.
This macro is used to encode the forms:
SQSHL <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> SQSHL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm_imm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d or an immediate
◆ INSTR_CREATE_sqshl_vector
| #define INSTR_CREATE_sqshl_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_sqshl, Rd, Rm, Rn, width) |
Creates a SQSHL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_sqshlr_sve_pred
| #define INSTR_CREATE_sqshlr_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_sqshlr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a SQSHLR instruction.
This macro is used to encode the forms:
SQSHLR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_sqshlu_sve_pred
| #define INSTR_CREATE_sqshlu_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| imm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_sqshlu, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
Creates a SQSHLU instruction.
This macro is used to encode the forms:
SQSHLU <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). imm The immediate imm.
◆ INSTR_CREATE_sqshrnb_sve
| #define INSTR_CREATE_sqshrnb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_2src(dc, OP_sqshrnb, Zd, Zn, imm) |
Creates a SQSHRNB instruction.
This macro is used to encode the forms:
SQSHRNB <Zd>.<Ts>, <Zn>.<Tb>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.b, Z.h or Z.s. Zn The first source vector register. Can be Z.h, Z.s or Z.d. imm The immediate imm1.
◆ INSTR_CREATE_sqshrnt_sve
| #define INSTR_CREATE_sqshrnt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_3src(dc, OP_sqshrnt, Zd, Zd, Zn, imm) |
Creates a SQSHRNT instruction.
This macro is used to encode the forms:
SQSHRNT <Zd>.<Ts>, <Zn>.<Tb>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The source and destination vector register. Can be Z.b, Z.h or Z.s. Zn The second source vector register. Can be Z.h, Z.s or Z.d. imm The immediate imm1.
◆ INSTR_CREATE_sqshrunb_sve
| #define INSTR_CREATE_sqshrunb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_2src(dc, OP_sqshrunb, Zd, Zn, imm) |
Creates a SQSHRUNB instruction.
This macro is used to encode the forms:
SQSHRUNB <Zd>.<Ts>, <Zn>.<Tb>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.b, Z.h or Z.s. Zn The first source vector register. Can be Z.h, Z.s or Z.d. imm The immediate imm1.
◆ INSTR_CREATE_sqshrunt_sve
| #define INSTR_CREATE_sqshrunt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_3src(dc, OP_sqshrunt, Zd, Zd, Zn, imm) |
Creates a SQSHRUNT instruction.
This macro is used to encode the forms:
SQSHRUNT <Zd>.<Ts>, <Zn>.<Tb>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The source and destination vector register. Can be Z.b, Z.h or Z.s. Zn The second source vector register. Can be Z.h, Z.s or Z.d. imm The immediate imm1.
◆ INSTR_CREATE_sqsub_sve
| #define INSTR_CREATE_sqsub_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_sqsub, Zd, Zn, Zm) |
Creates a SQSUB instruction.
This macro is used to encode the forms:
* SQSUB <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The first destination vector register, Z (Scalable) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_sqsub_sve_shift
| #define INSTR_CREATE_sqsub_sve_shift | ( | dc, | |
| Zdn, | |||
| imm, | |||
| shift | |||
| ) | instr_create_1dst_4src(dc, OP_sqsub, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift) |
Creates a SQSUB instruction.
This macro is used to encode the forms:
* SQSUB <Zdn>.<Ts>, <Zdn>.<Ts>, #<imm>, <shift> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and first destination vector register, Z (Scalable) imm The immediate imm shift The immediate shiftOp for imm8
◆ INSTR_CREATE_sqsub_vector
| #define INSTR_CREATE_sqsub_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_sqsub, Rd, Rm, Rn, width) |
Creates a SQSUB vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_sqsubr_sve_pred
| #define INSTR_CREATE_sqsubr_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_sqsubr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a SQSUBR instruction.
This macro is used to encode the forms:
SQSUBR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_sqxtnb_sve
| #define INSTR_CREATE_sqxtnb_sve | ( | dc, | |
| Zd, | |||
| Zn | |||
| ) | instr_create_1dst_1src(dc, OP_sqxtnb, Zd, Zn) |
Creates a SQXTNB instruction.
This macro is used to encode the forms:
SQXTNB <Zd>.<Ts>, <Zn>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.b, Z.h or Z.s. Zn The source vector register. Can be Z.h, Z.s or Z.d.
◆ INSTR_CREATE_sqxtnt_sve
| #define INSTR_CREATE_sqxtnt_sve | ( | dc, | |
| Zd, | |||
| Zn | |||
| ) | instr_create_1dst_2src(dc, OP_sqxtnt, Zd, Zd, Zn) |
Creates a SQXTNT instruction.
This macro is used to encode the forms:
SQXTNT <Zd>.<Ts>, <Zn>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The source and destination vector register. Can be Z.b, Z.h or Z.s. Zn The second source vector register. Can be Z.h, Z.s or Z.d.
◆ INSTR_CREATE_sqxtunb_sve
| #define INSTR_CREATE_sqxtunb_sve | ( | dc, | |
| Zd, | |||
| Zn | |||
| ) | instr_create_1dst_1src(dc, OP_sqxtunb, Zd, Zn) |
Creates a SQXTUNB instruction.
This macro is used to encode the forms:
SQXTUNB <Zd>.<Ts>, <Zn>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.b, Z.h or Z.s. Zn The source vector register. Can be Z.h, Z.s or Z.d.
◆ INSTR_CREATE_sqxtunt_sve
| #define INSTR_CREATE_sqxtunt_sve | ( | dc, | |
| Zd, | |||
| Zn | |||
| ) | instr_create_1dst_2src(dc, OP_sqxtunt, Zd, Zd, Zn) |
Creates a SQXTUNT instruction.
This macro is used to encode the forms:
SQXTUNT <Zd>.<Ts>, <Zn>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The source and destination vector register. Can be Z.b, Z.h or Z.s. Zn The second source vector register. Can be Z.h, Z.s or Z.d.
◆ INSTR_CREATE_srhadd_sve_pred
| #define INSTR_CREATE_srhadd_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_srhadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a SRHADD instruction.
This macro is used to encode the forms:
SRHADD <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_srhadd_vector
| #define INSTR_CREATE_srhadd_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_srhadd, Rd, Rm, Rn, width) |
Creates a SRHADD vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_sri_sve
| #define INSTR_CREATE_sri_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_3src(dc, OP_sri, Zd, Zd, Zn, imm) |
Creates a SRI instruction.
This macro is used to encode the forms:
SRI <Zd>.<Ts>, <Zn>.<Ts>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. imm The immediate imm1.
◆ INSTR_CREATE_srshl_sve_pred
| #define INSTR_CREATE_srshl_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_srshl, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a SRSHL instruction.
This macro is used to encode the forms:
SRSHL <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_srshl_vector
| #define INSTR_CREATE_srshl_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_srshl, Rd, Rm, Rn, width) |
Creates a SRSHL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_srshlr_sve_pred
| #define INSTR_CREATE_srshlr_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_srshlr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a SRSHLR instruction.
This macro is used to encode the forms:
SRSHLR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_srshr_sve_pred
| #define INSTR_CREATE_srshr_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| imm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_srshr, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
Creates a SRSHR instruction.
This macro is used to encode the forms:
SRSHR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). imm The immediate imm1.
◆ INSTR_CREATE_srsra_sve
| #define INSTR_CREATE_srsra_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_3src(dc, OP_srsra, Zda, Zda, Zn, imm) |
Creates a SRSRA instruction.
This macro is used to encode the forms:
SRSRA <Zda>.<Ts>, <Zn>.<Ts>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. imm The immediate imm1.
◆ INSTR_CREATE_sshl_vector
| #define INSTR_CREATE_sshl_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_sshl, Rd, Rm, Rn, width) |
Creates a SSHL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_sshllb_sve
| #define INSTR_CREATE_sshllb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_2src(dc, OP_sshllb, Zd, Zn, imm) |
Creates a SSHLLB instruction.
This macro is used to encode the forms:
SSHLLB <Zd>.<Ts>, <Zn>.<Tb>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h or Z.s. imm The immediate imm.
◆ INSTR_CREATE_sshllt_sve
| #define INSTR_CREATE_sshllt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_2src(dc, OP_sshllt, Zd, Zn, imm) |
Creates a SSHLLT instruction.
This macro is used to encode the forms:
SSHLLT <Zd>.<Ts>, <Zn>.<Tb>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h or Z.s. imm The immediate imm.
◆ INSTR_CREATE_ssra_sve
| #define INSTR_CREATE_ssra_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_3src(dc, OP_ssra, Zda, Zda, Zn, imm) |
Creates a SSRA instruction.
This macro is used to encode the forms:
SSRA <Zda>.<Ts>, <Zn>.<Ts>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. imm The immediate imm1.
◆ INSTR_CREATE_ssubl2_vector
| #define INSTR_CREATE_ssubl2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_ssubl2, Rd, Rm, Rn, width) |
Creates a SSUBL2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_ssubl_vector
| #define INSTR_CREATE_ssubl_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_ssubl, Rd, Rm, Rn, width) |
Creates a SSUBL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_ssublb_sve
| #define INSTR_CREATE_ssublb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_ssublb, Zd, Zn, Zm) |
Creates a SSUBLB instruction.
This macro is used to encode the forms:
SSUBLB <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h or Z.s. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_ssublbt_sve
| #define INSTR_CREATE_ssublbt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_ssublbt, Zd, Zn, Zm) |
Creates a SSUBLBT instruction.
This macro is used to encode the forms:
SSUBLBT <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h or Z.s. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_ssublt_sve
| #define INSTR_CREATE_ssublt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_ssublt, Zd, Zn, Zm) |
Creates a SSUBLT instruction.
This macro is used to encode the forms:
SSUBLT <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h or Z.s. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_ssubltb_sve
| #define INSTR_CREATE_ssubltb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_ssubltb, Zd, Zn, Zm) |
Creates a SSUBLTB instruction.
This macro is used to encode the forms:
SSUBLTB <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h or Z.s. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_ssubw2_vector
| #define INSTR_CREATE_ssubw2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_ssubw2, Rd, Rm, Rn, width) |
Creates a SSUBW2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_ssubw_vector
| #define INSTR_CREATE_ssubw_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_ssubw, Rd, Rm, Rn, width) |
Creates a SSUBW vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_ssubwb_sve
| #define INSTR_CREATE_ssubwb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_ssubwb, Zd, Zn, Zm) |
Creates a SSUBWB instruction.
This macro is used to encode the forms:
SSUBWB <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.h, Z.s or Z.d. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_ssubwt_sve
| #define INSTR_CREATE_ssubwt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_ssubwt, Zd, Zn, Zm) |
Creates a SSUBWT instruction.
This macro is used to encode the forms:
SSUBWT <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.h, Z.s or Z.d. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_st1_multi_1
| #define INSTR_CREATE_st1_multi_1 | ( | dc, | |
| r, | |||
| q, | |||
| s | |||
| ) | instr_create_1dst_2src(dc, OP_st1, r, q, s) |
Creates an Advanced SIMD (NEON) ST1 instruction to store multiple single element structures from one vector register, e.g. ST1 {V1.2S},[X1].
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. r The destination memory operand. q The source vector register operand. s The size of the vector element.
◆ INSTR_CREATE_st1b_sve_pred
| #define INSTR_CREATE_st1b_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_st1b, Rn, Zt, Pg), DR_PRED_MASKED) |
Creates a ST1B instruction.
This macro is used to encode the forms:
* ST1B { <Zt>.<Ts> }, <Pg>, [<Xn|SP>, <Xm>]
* ST1B { <Zt>.<Ts> }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
* ST1B { <Zt>.S }, <Pg>, [<Zn>.S{, #<imm>}]
* ST1B { <Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
* ST1B { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D]
* ST1B { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <extend>]
* ST1B { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <extend>]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The first source vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The second source base register with a register offset, constructed with the function: opnd_create_base_disp_aarch64(Rn, Rm, For the [<Xn|SP>, <Xm>] variant: DR_EXTEND_UXTX, 0, 0, 0, OPSZ_1) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_1) For the [<Zn>.S{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_4, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_1, 0) For the [<Zn>.D{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_8, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_1, 0) For the [<Xn|SP>, <Zm>.D] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_1, 0) For the [<Xn|SP>, <Zm>.D, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, 0, 0, OPSZ_1, 0) For the [<Xn|SP>, <Zm>.S, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_4, extend, 0, 0, OPSZ_1, 0)
◆ INSTR_CREATE_st1d_sve_pred
| #define INSTR_CREATE_st1d_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_st1d, Zn, Zt, Pg), DR_PRED_MASKED) |
Creates a ST1D instruction.
This macro is used to encode the forms:
* ST1D { <Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
* ST1D { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, LSL #3]
* ST1D { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D]
* ST1D { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <extend> #3]
* ST1D { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <extend>]
* ST1D { <Zt>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
* ST1D { <Zt>.D }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The first source vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The second source vector base register with an immediate offset, constructed with the function: For the [<Zn>.D{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_8, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_8, 0) For the [<Xn|SP>, <Zm>.D, LSL #3] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, true, 0, OPSZ_8, 3) For the [<Xn|SP>, <Zm>.D] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_8, 0) For the [<Xn|SP>, <Zm>.D, <extend> #3] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, true, 0, OPSZ_8, 3) For the [<Xn|SP>, <Zm>.D, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, 0, 0, OPSZ_8, 0) For the [<Xn|SP>, <Xm>, LSL #3] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_8, 3) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_8)
◆ INSTR_CREATE_st1h_sve_pred
| #define INSTR_CREATE_st1h_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_st1h, Zn, Zt, Pg), DR_PRED_MASKED) |
Creates a ST1H instruction.
This macro is used to encode the forms:
* ST1H { <Zt>.S }, <Pg>, [<Zn>.S{, #<imm>}]
* ST1H { <Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
* ST1H { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, LSL #1]
* ST1H { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D]
* ST1H { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <extend> #1]
* ST1H { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <extend>]
* ST1H { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <extend> #1]
* ST1H { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <extend>]
* ST1H { <Zt>.<Ts> }, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
* ST1H { <Zt>.<Ts> }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The first source vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The second source vector base register with an immediate offset, constructed with the function: For the [<Zn>.S{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_4, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_2, 0) For the [<Zn>.D{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_8, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_2, 0) For the [<Xn|SP>, <Zm>.D, LSL #1] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, true, 0, OPSZ_2, 1) For the [<Xn|SP>, <Zm>.D] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_2, 0) For the [<Xn|SP>, <Zm>.D, <extend> #1] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, true, 0, OPSZ_2, 1) For the [<Xn|SP>, <Zm>.D, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, 0, 0, OPSZ_2, 0) For the [<Xn|SP>, <Zm>.S, <extend> #1] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_4, extend, true, 0, OPSZ_2, 1) For the [<Xn|SP>, <Zm>.S, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_4, extend, 0, 0, OPSZ_2, 0) For the [<Xn|SP>, <Xm>, LSL #1] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_2, 1) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_2)
◆ INSTR_CREATE_st1w_sve_pred
| #define INSTR_CREATE_st1w_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_st1w, Zn, Zt, Pg), DR_PRED_MASKED) |
Creates a ST1W instruction.
This macro is used to encode the forms:
* ST1W { <Zt>.S }, <Pg>, [<Zn>.S{, #<imm>}]
* ST1W { <Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
* ST1W { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, LSL #2]
* ST1W { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D]
* ST1W { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <extend> #2]
* ST1W { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <extend>]
* ST1W { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <extend> #2]
* ST1W { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <extend>]
* ST1W { <Zt>.<Ts> }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
* ST1W { <Zt>.<Ts> }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The first source vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The second source vector base register with an immediate offset, constructed with the function: For the [<Zn>.S{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_4, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_4, 0) For the [<Zn>.D{, #<imm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, DR_REG_NULL, OPSZ_8, DR_EXTEND_UXTX, 0, imm5, 0, OPSZ_4, 0) For the [<Xn|SP>, <Zm>.D, LSL #2] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, true, 0, OPSZ_4, 2) For the [<Xn|SP>, <Zm>.D] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_4, 0) For the [<Xn|SP>, <Zm>.D, <extend> #2] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, true, 0, OPSZ_4, 2) For the [<Xn|SP>, <Zm>.D, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_8, extend, 0, 0, OPSZ_4, 0) For the [<Xn|SP>, <Zm>.S, <extend> #2] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_4, extend, true, 0, OPSZ_4, 2) For the [<Xn|SP>, <Zm>.S, <extend>] variant: opnd_create_vector_base_disp_aarch64( Xn, Zm, OPSZ_4, extend, 0, 0, OPSZ_4, 0) For the [<Xn|SP>, <Xm>, LSL #2] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_4, 2) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_4)
◆ INSTR_CREATE_st2b_sve_pred
| #define INSTR_CREATE_st2b_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) |
Value:
INSTR_PRED(instr_create_1dst_3src(dc, OP_st2b, Rn, Zt, \
opnd_create_increment_reg(Zt, 1), Pg), \
DR_PRED_MASKED)
Creates a ST2B instruction.
This macro is used to encode the forms:
* ST2B { <Zt1>.B, <Zt2>.B }, <Pg>, [<Xn|SP>, <Xm>]
* ST2B { <Zt1>.B, <Zt2>.B }, <Pg>, [<Xn|SP>{, #<simm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The first source vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The second source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>] variant: opnd_create_base_disp_aarch64(Rn, Rm, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_1) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm4, OPSZ_1)
The Zt2 parameter is derived from Zt.
◆ INSTR_CREATE_st2d_sve_pred
| #define INSTR_CREATE_st2d_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) |
Value:
INSTR_PRED(instr_create_1dst_3src(dc, OP_st2d, Rn, Zt, \
opnd_create_increment_reg(Zt, 1), Pg), \
DR_PRED_MASKED)
Creates a ST2D instruction.
This macro is used to encode the forms:
* ST2D { <Zt1>.D, <Zt2>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
* ST2D { <Zt1>.D, <Zt2>.D }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The first source vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The second source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>, LSL #3] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_8, 3) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm4, OPSZ_8)
The Zt2 parameter is derived from Zt.
◆ INSTR_CREATE_st2g_offset
| #define INSTR_CREATE_st2g_offset | ( | dc, | |
| Rn, | |||
| Rt | |||
| ) | instr_create_1dst_1src(dc, OP_st2g, Rn, Rt) |
Creates a ST2G instruction.
This macro is used to encode the forms:
ST2G <Xt>, [<Xn|SP>, #<simm>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The second source and destination base register with an immediate offset, constructed with the function: opnd_create_base_disp_aarch64(Rn, DR_REG_NULL, DR_EXTEND_UXTX, 0, simm, 0, OPSZ_0) Rt The first source register, X (Extended, 64 bits).
◆ INSTR_CREATE_st2g_post
| #define INSTR_CREATE_st2g_post | ( | dc, | |
| Rn, | |||
| Rt, | |||
| simm | |||
| ) |
Value:
opnd_create_reg(opnd_get_base(Rn)), simm)
Creates a ST2G instruction.
This macro is used to encode the forms:
ST2G <Xt>, [<Xn|SP>], #<simm>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The second source and destination base register with an immediate offset, constructed with the function: opnd_create_base_disp_aarch64(Rn, DR_REG_NULL, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_0) Rt The first source register, X (Extended, 64 bits). simm The immediate integer offset, must be a multiple of 16 between -4096 and 4080.
◆ INSTR_CREATE_st2g_pre
| #define INSTR_CREATE_st2g_pre | ( | dc, | |
| Rn, | |||
| Rt | |||
| ) |
Value:
opnd_create_reg(opnd_get_base(Rn)), \
OPND_CREATE_INT(opnd_get_disp(Rn)))
Creates a ST2G instruction.
This macro is used to encode the forms:
ST2G <Xt>, [<Xn|SP>, #<simm>]!
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The second source and destination base register with an immediate offset, constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, simm, OPSZ_0) Rt The first source register, X (Extended, 64 bits).
◆ INSTR_CREATE_st2h_sve_pred
| #define INSTR_CREATE_st2h_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) |
Value:
INSTR_PRED(instr_create_1dst_3src(dc, OP_st2h, Rn, Zt, \
opnd_create_increment_reg(Zt, 1), Pg), \
DR_PRED_MASKED)
Creates a ST2H instruction.
This macro is used to encode the forms:
* ST2H { <Zt1>.H, <Zt2>.H }, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
* ST2H { <Zt1>.H, <Zt2>.H }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The first source vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The second source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>, LSL #1] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_2, 1) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm4, OPSZ_2)
The Zt2 parameter is derived from Zt.
◆ INSTR_CREATE_st2w_sve_pred
| #define INSTR_CREATE_st2w_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) |
Value:
INSTR_PRED(instr_create_1dst_3src(dc, OP_st2w, Rn, Zt, \
opnd_create_increment_reg(Zt, 1), Pg), \
DR_PRED_MASKED)
Creates a ST2W instruction.
This macro is used to encode the forms:
* ST2W { <Zt1>.S, <Zt2>.S }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
* ST2W { <Zt1>.S, <Zt2>.S }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The first source vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The second source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>, LSL #2] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_4, 2) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm4, OPSZ_4)
The Zt2 parameter is derived from Zt.
◆ INSTR_CREATE_st3b_sve_pred
| #define INSTR_CREATE_st3b_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) |
Value:
INSTR_PRED(instr_create_1dst_4src(dc, OP_st3b, Rn, Zt, \
opnd_create_increment_reg(Zt, 1), \
opnd_create_increment_reg(Zt, 2), Pg), \
DR_PRED_MASKED)
Creates a ST3B instruction.
This macro is used to encode the forms:
* ST3B { <Zt1>.B, <Zt2>.B, <Zt3>.B }, <Pg>, [<Xn|SP>, <Xm>]
* ST3B { <Zt1>.B, <Zt2>.B, <Zt3>.B }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The first source vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The second source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>] variant: opnd_create_base_disp_aarch64(Rn, Rm, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_1) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_1)
The Zt2 and Zt3 parameters are derived from Zt.
◆ INSTR_CREATE_st3d_sve_pred
| #define INSTR_CREATE_st3d_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) |
Value:
INSTR_PRED(instr_create_1dst_4src(dc, OP_st3d, Rn, Zt, \
opnd_create_increment_reg(Zt, 1), \
opnd_create_increment_reg(Zt, 2), Pg), \
DR_PRED_MASKED)
Creates a ST3D instruction.
This macro is used to encode the forms:
* ST3D { <Zt1>.D, <Zt2>.D, <Zt3>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
* ST3D { <Zt1>.D, <Zt2>.D, <Zt3>.D }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The first source vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The second source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>, LSL #3] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_8, 3) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm4, OPSZ_8)
The Zt2 and Zt3 parameters are derived from Zt.
◆ INSTR_CREATE_st3h_sve_pred
| #define INSTR_CREATE_st3h_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) |
Value:
INSTR_PRED(instr_create_1dst_4src(dc, OP_st3h, Rn, Zt, \
opnd_create_increment_reg(Zt, 1), \
opnd_create_increment_reg(Zt, 2), Pg), \
DR_PRED_MASKED)
Creates a ST3H instruction.
This macro is used to encode the forms:
* ST3H { <Zt1>.H, <Zt2>.H, <Zt3>.H }, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
* ST3H { <Zt1>.H, <Zt2>.H, <Zt3>.H }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The first source vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The second source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>, LSL #1] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_2, 1) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm4, OPSZ_2)
The Zt2 and Zt3 parameters are derived from Zt.
◆ INSTR_CREATE_st3w_sve_pred
| #define INSTR_CREATE_st3w_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) |
Value:
INSTR_PRED(instr_create_1dst_4src(dc, OP_st3w, Rn, Zt, \
opnd_create_increment_reg(Zt, 1), \
opnd_create_increment_reg(Zt, 2), Pg), \
DR_PRED_MASKED)
Creates a ST3W instruction.
This macro is used to encode the forms:
* ST3W { <Zt1>.S, <Zt2>.S, <Zt3>.S }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
* ST3W { <Zt1>.S, <Zt2>.S, <Zt3>.S }, <Pg>, [<Xn|SP>{, #<simm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The first source vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The second source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>, LSL #2] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_4, 2) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm4, OPSZ_4)
The Zt2 and Zt3 parameters are derived from Zt.
◆ INSTR_CREATE_st4b_sve_pred
| #define INSTR_CREATE_st4b_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) |
Value:
INSTR_PRED(instr_create_1dst_5src(dc, OP_st4b, Rn, Zt, \
opnd_create_increment_reg(Zt, 1), \
opnd_create_increment_reg(Zt, 2), \
opnd_create_increment_reg(Zt, 3), Pg), \
DR_PRED_MASKED)
Creates a ST4B instruction.
This macro is used to encode the forms:
* ST4B { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <Pg>, [<Xn|SP>, <Xm>]
* ST4B { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <Pg>, [<Xn|SP>{, #<simm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The first source vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The second source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>] variant: opnd_create_base_disp_aarch64(Rn, Rm, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_1) For the [<Xn|SP>{, #<simm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm4, OPSZ_1)
The Zt2, Zt3 and Zt4 parameters are derived from Zt.
◆ INSTR_CREATE_st4d_sve_pred
| #define INSTR_CREATE_st4d_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) |
Value:
INSTR_PRED(instr_create_1dst_5src(dc, OP_st4d, Rn, Zt, \
opnd_create_increment_reg(Zt, 1), \
opnd_create_increment_reg(Zt, 2), \
opnd_create_increment_reg(Zt, 3), Pg), \
DR_PRED_MASKED)
Creates a ST4D instruction.
This macro is used to encode the forms:
* ST4D { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
* ST4D { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <Pg>, [<Xn|SP>{, #<simm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The first source vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The second source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>, LSL #3] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_8, 3) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm4, OPSZ_8)
The Zt2, Zt3 and Zt4 parameters are derived from Zt.
◆ INSTR_CREATE_st4h_sve_pred
| #define INSTR_CREATE_st4h_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) |
Value:
INSTR_PRED(instr_create_1dst_5src(dc, OP_st4h, Rn, Zt, \
opnd_create_increment_reg(Zt, 1), \
opnd_create_increment_reg(Zt, 2), \
opnd_create_increment_reg(Zt, 3), Pg), \
DR_PRED_MASKED)
Creates a ST4H instruction.
This macro is used to encode the forms:
* ST4H { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
* ST4H { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <Pg>, [<Xn|SP>{, #<simm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The first source vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The second source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>, LSL #1] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_2, 1) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm4, OPSZ_2)
The Zt2, Zt3 and Zt4 parameters are derived from Zt.
◆ INSTR_CREATE_st4w_sve_pred
| #define INSTR_CREATE_st4w_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) |
Value:
INSTR_PRED(instr_create_1dst_5src(dc, OP_st4w, Rn, Zt, \
opnd_create_increment_reg(Zt, 1), \
opnd_create_increment_reg(Zt, 2), \
opnd_create_increment_reg(Zt, 3), Pg), \
DR_PRED_MASKED)
Creates a ST4W instruction.
This macro is used to encode the forms:
* ST4W { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
* ST4W { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <Pg>, [<Xn|SP>{, #<simm>, MUL VL}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The first source vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The second source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>, LSL #2] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_4, 2) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm4, OPSZ_4)
The Zt2, Zt3 and Zt4 parameters are derived from Zt.
◆ INSTR_CREATE_stg_offset
| #define INSTR_CREATE_stg_offset | ( | dc, | |
| Rn, | |||
| Rt | |||
| ) | instr_create_1dst_1src(dc, OP_stg, Rn, Rt) |
Creates a STG instruction.
This macro is used to encode the forms:
STG <Xt>, [<Xn|SP>, #<simm>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The second source and destination base register with an immediate offset, constructed with the function: opnd_create_base_disp_aarch64(Rn, DR_REG_NULL, DR_EXTEND_UXTX, 0, simm, 0, OPSZ_0) Rt The first source register, X (Extended, 64 bits).
◆ INSTR_CREATE_stg_post
| #define INSTR_CREATE_stg_post | ( | dc, | |
| Rn, | |||
| Rt, | |||
| simm | |||
| ) |
Value:
opnd_create_reg(opnd_get_base(Rn)), simm)
Creates a STG instruction.
This macro is used to encode the forms:
STG <Xt>, [<Xn|SP>], #<simm>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The second source and destination base register with an immediate offset, constructed with the function: opnd_create_base_disp_aarch64(Rn, DR_REG_NULL, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_0) Rt The first source register, X (Extended, 64 bits). simm The immediate integer offset, must be a multiple of 16 between -4096 and 4080.
◆ INSTR_CREATE_stg_pre
| #define INSTR_CREATE_stg_pre | ( | dc, | |
| Rn, | |||
| Rt | |||
| ) |
Value:
opnd_create_reg(opnd_get_base(Rn)), \
OPND_CREATE_INT(opnd_get_disp(Rn)))
Creates a STG instruction.
This macro is used to encode the forms:
STG <Xt>, [<Xn|SP>, #<simm>]!
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The second source and destination base register with an immediate offset, constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, simm, OPSZ_0) Rt The first source register, X (Extended, 64 bits).
◆ INSTR_CREATE_stgm
| #define INSTR_CREATE_stgm | ( | dc, | |
| Rn, | |||
| Rt | |||
| ) | instr_create_1dst_1src(dc, OP_stgm, Rn, Rt) |
Creates an STGM instruction.
This macro is used to encode the forms:
STGM <Xt>, [<Xn|SP>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The destination memory operand constructed with the function: opnd_create_base_disp_aarch64(Rn, DR_REG_NULL, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_0) Note that memory tag accesses are not treated as real/data memory accesses by DynamoRIO, similar to prefetch and PC-relative address manipulation instructions. Rt The first source register, X (Extended, 64 bits).
◆ INSTR_CREATE_stgp_offset
| #define INSTR_CREATE_stgp_offset | ( | dc, | |
| Rn, | |||
| Rt, | |||
| Rt2 | |||
| ) | instr_create_1dst_2src(dc, OP_stgp, Rn, Rt, Rt2) |
Creates a STGP instruction.
This macro is used to encode the forms:
STGP <Xt>, <Xt2>, [<Xn|SP>, #<simm>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The third source and destination base register with an immediate offset, constructed with the function: opnd_create_base_disp_aarch64(Rn, DR_REG_NULL, DR_EXTEND_UXTX, 0, simm, 0, OPSZ_16) Rt The first source register, X (Extended, 64 bits). Rt2 The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_stgp_post
| #define INSTR_CREATE_stgp_post | ( | dc, | |
| Rn, | |||
| Rt, | |||
| Rt2, | |||
| simm | |||
| ) |
Value:
opnd_create_reg(opnd_get_base(Rn)), simm)
Creates a STGP instruction.
This macro is used to encode the forms:
STGP <Xt>, <Xt2>, [<Xn|SP>], #<simm>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The third source and destination base register with an immediate offset, constructed with the function: opnd_create_base_disp_aarch64(Rn, DR_REG_NULL, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_16) Rt The first source register, X (Extended, 64 bits). Rt2 The second source register, X (Extended, 64 bits). simm The immediate integer offset, must be a multiple of 16 between -1024 and 1008.
◆ INSTR_CREATE_stgp_pre
| #define INSTR_CREATE_stgp_pre | ( | dc, | |
| Rn, | |||
| Rt, | |||
| Rt2 | |||
| ) |
Value:
opnd_create_reg(opnd_get_base(Rn)), \
OPND_CREATE_INT(opnd_get_disp(Rn)))
Creates a STGP instruction.
This macro is used to encode the forms:
STGP <Xt>, <Xt2>, [<Xn|SP>, #<simm>]!
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The third source and destination base register with an immediate offset, constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, simm, OPSZ_16) Rt The first source register, X (Extended, 64 bits). Rt2 The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_stllr
| #define INSTR_CREATE_stllr | ( | dc, | |
| Rt, | |||
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_stllr, Rt, Rn) |
Creates a STLLR instruction.
This macro is used to encode the forms:
* STLLR <Wt>, [<Xn|SP>] * STLLR <Xt>, [<Xn|SP>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The first destination register. Can be W (Word, 32 bits) or X (Extended, 64 bits) Rn The second source register. Can be X (Extended, 64 bits)
◆ INSTR_CREATE_stllrb
| #define INSTR_CREATE_stllrb | ( | dc, | |
| Rt, | |||
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_stllrb, Rt, Rn) |
Creates a STLLRB instruction.
This macro is used to encode the forms:
* STLLRB <Wt>, [<Xn|SP>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The first destination register, W (Word, 32 bits) Rn The second source register, X (Extended, 64 bits)
◆ INSTR_CREATE_stllrh
| #define INSTR_CREATE_stllrh | ( | dc, | |
| Rt, | |||
| Rn | |||
| ) | instr_create_1dst_1src(dc, OP_stllrh, Rt, Rn) |
Creates a STLLRH instruction.
This macro is used to encode the forms:
* STLLRH <Wt>, [<Xn|SP>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The first destination register, W (Word, 32 bits) Rn The second source register, X (Extended, 64 bits)
◆ INSTR_CREATE_stlur
| #define INSTR_CREATE_stlur | ( | dc, | |
| Rt, | |||
| mem | |||
| ) | instr_create_1dst_1src(dc, OP_stlur, mem, Rt) |
Creates a STLUR instruction.
This macro is used to encode the forms:
* STLUR <Wt>, [<Xn|SP>{, #<simm>}]
* STLUR <Xt>, [<Xn|SP>{, #<simm>}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The source register, W (Word, 32 bits) or X (Extended, 64 bits). mem The destination memory address operand constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, simm, OPSZ_4)
◆ INSTR_CREATE_stlurb
| #define INSTR_CREATE_stlurb | ( | dc, | |
| Rt, | |||
| mem | |||
| ) | instr_create_1dst_1src(dc, OP_stlurb, mem, Rt) |
Creates a STLURB instruction.
This macro is used to encode the forms:
* STLURB <Wt>, [<Xn|SP>{, #<simm>}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The source register, W (Word, 32 bits). mem The destination memory address operand constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, simm, OPSZ_1)
◆ INSTR_CREATE_stlurh
| #define INSTR_CREATE_stlurh | ( | dc, | |
| Rt, | |||
| mem | |||
| ) | instr_create_1dst_1src(dc, OP_stlurh, mem, Rt) |
Creates a STLURH instruction.
This macro is used to encode the forms:
* STLURH <Wt>, [<Xn|SP>{, #<simm>}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The source register, W (Word, 32 bits). mem The destination memory address operand constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, simm, OPSZ_2)
◆ INSTR_CREATE_stnt1b_sve_pred
| #define INSTR_CREATE_stnt1b_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_stnt1b, Rn, Zt, Pg), DR_PRED_MASKED) |
Creates a STNT1B instruction.
This macro is used to encode the forms:
* STNT1B { <Zt>.B }, <Pg>, [<Xn|SP>, <Xm>]
* STNT1B { <Zt>.B }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
* STNT1B { <Zt>.D }, <Pg>, [<Zn>.D{, <Xm>}]
* STNT1B { <Zt>.S }, <Pg>, [<Zn>.S{, <Xm>}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The first source vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The second source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>] variant: opnd_create_base_disp_aarch64(Rn, Rm, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_1) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_1) For the [<Zn>.D{, <Xm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, Xm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_1, 0) For the [<Zn>.S{, <Xm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, Xm, OPSZ_4, DR_EXTEND_UXTX, 0, 0, OPSZ_1, 0)
◆ INSTR_CREATE_stnt1d_sve_pred
| #define INSTR_CREATE_stnt1d_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_stnt1d, Rn, Zt, Pg), DR_PRED_MASKED) |
Creates a STNT1D instruction.
This macro is used to encode the forms:
* STNT1D { <Zt>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
* STNT1D { <Zt>.D }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
* STNT1D { <Zt>.D }, <Pg>, [<Zn>.D{, <Xm>}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The first source vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The second source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>, LSL #3] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_8, 3) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_8) For the [<Zn>.D{, <Xm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, Xm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_8, 0)
◆ INSTR_CREATE_stnt1h_sve_pred
| #define INSTR_CREATE_stnt1h_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_stnt1h, Rn, Zt, Pg), DR_PRED_MASKED) |
Creates a STNT1H instruction.
This macro is used to encode the forms:
* STNT1H { <Zt>.H }, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
* STNT1H { <Zt>.H }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
* STNT1H { <Zt>.D }, <Pg>, [<Zn>.D{, <Xm>}]
* STNT1H { <Zt>.S }, <Pg>, [<Zn>.S{, <Xm>}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The first source vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The second source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>, LSL #1] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_2, 1) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_2) For the [<Zn>.D{, <Xm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, Xm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_2, 0) For the [<Zn>.S{, <Xm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, Xm, OPSZ_4, DR_EXTEND_UXTX, 0, 0, OPSZ_2, 0)
◆ INSTR_CREATE_stnt1w_sve_pred
| #define INSTR_CREATE_stnt1w_sve_pred | ( | dc, | |
| Zt, | |||
| Pg, | |||
| Rn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_stnt1w, Rn, Zt, Pg), DR_PRED_MASKED) |
Creates a STNT1W instruction.
This macro is used to encode the forms:
* STNT1W { <Zt>.S }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
* STNT1W { <Zt>.S }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
* STNT1W { <Zt>.D }, <Pg>, [<Zn>.D{, <Xm>}]
* STNT1W { <Zt>.S }, <Pg>, [<Zn>.S{, <Xm>}]
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zt The first source vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Rn The second source base register with a register offset, constructed with the function: For the [<Xn|SP>, <Xm>, LSL #2] variant: opnd_create_base_disp_shift_aarch64( Rn, Rm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_4, 2) For the [<Xn|SP>{, #<imm>, MUL VL}] variant: opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, OPSZ_4) For the [<Zn>.D{, <Xm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, Xm, OPSZ_8, DR_EXTEND_UXTX, 0, 0, OPSZ_4, 0) For the [<Zn>.S{, <Xm>}] variant: opnd_create_vector_base_disp_aarch64( Zn, Xm, OPSZ_4, DR_EXTEND_UXTX, 0, 0, OPSZ_4, 0)
◆ INSTR_CREATE_str_imm
| #define INSTR_CREATE_str_imm | ( | dc, | |
| Rt, | |||
| Xt, | |||
| Xn, | |||
| imm | |||
| ) | instr_create_2dst_3src(dc, OP_str, Rt, Xn, Xt, Xn, imm) |
Creates a STR immediate instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The output memory disposition. Xt The input register or stack pointer to store. Xn The output register which must be the address base register. imm Immediate int of the output register offset.
◆ INSTR_CREATE_stz2g_offset
| #define INSTR_CREATE_stz2g_offset | ( | dc, | |
| Rn, | |||
| Rt | |||
| ) | instr_create_1dst_1src(dc, OP_stz2g, Rn, Rt) |
Creates a STZ2G instruction.
This macro is used to encode the forms:
STZ2G <Xt>, [<Xn|SP>, #<simm>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The second source and destination base register with an immediate offset, constructed with the function: opnd_create_base_disp_aarch64(Rn, DR_REG_NULL, DR_EXTEND_UXTX, 0, simm, 0, OPSZ_32) Rt The first source register, X (Extended, 64 bits).
◆ INSTR_CREATE_stz2g_post
| #define INSTR_CREATE_stz2g_post | ( | dc, | |
| Rn, | |||
| Rt, | |||
| simm | |||
| ) |
Value:
opnd_create_reg(opnd_get_base(Rn)), simm)
Creates a STZ2G instruction.
This macro is used to encode the forms:
STZ2G <Xt>, [<Xn|SP>], #<simm>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The second source and destination base register with an immediate offset, constructed with the function: opnd_create_base_disp_aarch64(Rn, DR_REG_NULL, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_32) Rt The first source register, X (Extended, 64 bits). simm The immediate integer offset, must be a multiple of 16 between -4096 and 4080.
◆ INSTR_CREATE_stz2g_pre
| #define INSTR_CREATE_stz2g_pre | ( | dc, | |
| Rn, | |||
| Rt | |||
| ) |
Value:
opnd_create_reg(opnd_get_base(Rn)), \
OPND_CREATE_INT(opnd_get_disp(Rn)))
Creates a STZ2G instruction.
This macro is used to encode the forms:
STZ2G <Xt>, [<Xn|SP>, #<simm>]!
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The second source and destination base register with an immediate offset, constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, simm, OPSZ_32) Rt The first source register, X (Extended, 64 bits).
◆ INSTR_CREATE_stzg_offset
| #define INSTR_CREATE_stzg_offset | ( | dc, | |
| Rn, | |||
| Rt | |||
| ) | instr_create_1dst_1src(dc, OP_stzg, Rn, Rt) |
Creates a STZG instruction.
This macro is used to encode the forms:
STZG <Xt>, [<Xn|SP>, #<simm>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The second source and destination base register with an immediate offset, constructed with the function: opnd_create_base_disp_aarch64(Rn, DR_REG_NULL, DR_EXTEND_UXTX, 0, simm, 0, OPSZ_16) Rt The first source register, X (Extended, 64 bits).
◆ INSTR_CREATE_stzg_post
| #define INSTR_CREATE_stzg_post | ( | dc, | |
| Rn, | |||
| Rt, | |||
| simm | |||
| ) |
Value:
opnd_create_reg(opnd_get_base(Rn)), simm)
Creates a STZG instruction.
This macro is used to encode the forms:
STZG <Xt>, [<Xn|SP>], #<simm>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The second source and destination base register with an immediate offset, constructed with the function: opnd_create_base_disp_aarch64(Rn, DR_REG_NULL, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_16) Rt The first source register, X (Extended, 64 bits). simm The immediate integer offset, must be a multiple of 16 between -4096 and 4080.
◆ INSTR_CREATE_stzg_pre
| #define INSTR_CREATE_stzg_pre | ( | dc, | |
| Rn, | |||
| Rt | |||
| ) |
Value:
opnd_create_reg(opnd_get_base(Rn)), \
OPND_CREATE_INT(opnd_get_disp(Rn)))
Creates a STZG instruction.
This macro is used to encode the forms:
STZG <Xt>, [<Xn|SP>, #<simm>]!
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The second source and destination base register with an immediate offset, constructed with the function: opnd_create_base_disp(Rn, DR_REG_NULL, 0, simm, OPSZ_16) Rt The first source register, X (Extended, 64 bits).
◆ INSTR_CREATE_stzgm
| #define INSTR_CREATE_stzgm | ( | dc, | |
| Rn, | |||
| Rt | |||
| ) | instr_create_1dst_1src(dc, OP_stzgm, Rn, Rt) |
Creates an STZGM instruction.
This macro is used to encode the forms:
STZGM <Xt>, [<Xn|SP>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rn The destination memory operand constructed with the function: opnd_create_base_disp_aarch64(Rn, DR_REG_NULL, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_16) Rt The first source register, X (Extended, 64 bits).
◆ INSTR_CREATE_sub_sve
| #define INSTR_CREATE_sub_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_sub, Zd, Zn, Zm) |
Creates a SUB instruction.
This macro is used to encode the forms:
* SUB <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The first destination vector register, Z (Scalable) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_sub_sve_pred
| #define INSTR_CREATE_sub_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_sub, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a SUB instruction.
This macro is used to encode the forms:
* SUB <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The second source and first destination vector register, Z (Scalable) Pg The first source vector register, Z (Scalable) Zm The third source vector register, Z (Scalable)
◆ INSTR_CREATE_sub_sve_shift
| #define INSTR_CREATE_sub_sve_shift | ( | dc, | |
| Zdn, | |||
| imm, | |||
| shift | |||
| ) | instr_create_1dst_4src(dc, OP_sub, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift) |
Creates a SUB instruction.
This macro is used to encode the forms:
* SUB <Zdn>.<Ts>, <Zdn>.<Ts>, #<imm>, <shift> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and first destination vector register, Z (Scalable) imm The immediate imm shift The immediate shiftOp for imm8
◆ INSTR_CREATE_sub_vector
| #define INSTR_CREATE_sub_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_sub, Rd, Rm, Rn, width) |
Creates a SUB vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_subg
| #define INSTR_CREATE_subg | ( | dc, | |
| Rd, | |||
| Rn, | |||
| imm1, | |||
| imm2 | |||
| ) | instr_create_1dst_3src(dc, OP_subg, Rd, Rn, imm1, imm2) |
Creates a SUBG instruction.
This macro is used to encode the forms:
SUBG <Xd|SP>, <Xn|SP>, #<imm1>, #<imm2>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register, X (Extended, 64 bits). Rn The first source register, X (Extended, 64 bits). imm1 The immediate unsigned imm (must be a multiple of 16). imm2 The immediate unsigned imm.
◆ INSTR_CREATE_subhn2_vector
| #define INSTR_CREATE_subhn2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_subhn2, Rd, Rm, Rn, width) |
Creates a SUBHN2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_subhn_vector
| #define INSTR_CREATE_subhn_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_subhn, Rd, Rm, Rn, width) |
Creates a SUBHN vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_subhnb_sve
| #define INSTR_CREATE_subhnb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_subhnb, Zd, Zn, Zm) |
Creates a SUBHNB instruction.
This macro is used to encode the forms:
SUBHNB <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.b, Z.h or Z.s. Zn The first source vector register. Can be Z.h, Z.s or Z.d. Zm The second source vector register. Can be Z.h, Z.s or Z.d.
◆ INSTR_CREATE_subhnt_sve
| #define INSTR_CREATE_subhnt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_subhnt, Zd, Zd, Zn, Zm) |
Creates a SUBHNT instruction.
This macro is used to encode the forms:
SUBHNT <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The source and destination vector register. Can be Z.b, Z.h or Z.s. Zn The second source vector register. Can be Z.h, Z.s or Z.d. Zm The third source vector register. Can be Z.h, Z.s or Z.d.
◆ INSTR_CREATE_subp
| #define INSTR_CREATE_subp | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_subp, Rd, Rn, Rm) |
Creates a SUBP instruction.
This macro is used to encode the forms:
SUBP <Xd>, <Xn|SP>, <Xm|SP>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register, X (Extended, 64 bits). Rn The first source register, X (Extended, 64 bits). Rm The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_subps
| #define INSTR_CREATE_subps | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_subps, Rd, Rn, Rm) |
Creates a SUBPS instruction.
This macro is used to encode the forms:
SUBPS <Xd>, <Xn|SP>, <Xm|SP>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The destination register, X (Extended, 64 bits). Rn The first source register, X (Extended, 64 bits). Rm The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_subr_sve_pred
| #define INSTR_CREATE_subr_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_subr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a SUBR instruction.
This macro is used to encode the forms:
* SUBR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The second source and first destination vector register, Z (Scalable) Pg The first source vector register, Z (Scalable) Zm The third source vector register, Z (Scalable)
◆ INSTR_CREATE_subr_sve_shift
| #define INSTR_CREATE_subr_sve_shift | ( | dc, | |
| Zdn, | |||
| imm, | |||
| shift | |||
| ) | instr_create_1dst_4src(dc, OP_subr, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift) |
Creates a SUBR instruction.
This macro is used to encode the forms:
* SUBR <Zdn>.<Ts>, <Zdn>.<Ts>, #<imm>, <shift> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and first destination vector register, Z (Scalable) imm The immediate imm shift The immediate shiftOp for imm8
◆ INSTR_CREATE_sudot_sve_idx
| #define INSTR_CREATE_sudot_sve_idx | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| index | |||
| ) | instr_create_1dst_4src(dc, OP_sudot, Zda, Zda, Zn, Zm, index) |
Creates a SUDOT instruction.
This macro is used to encode the forms:
* SUDOT <Zda>.S, <Zn>.B, <Zm>.B[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable). index The immediate index
◆ INSTR_CREATE_sudot_vector_idx
| #define INSTR_CREATE_sudot_vector_idx | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| index | |||
| ) | instr_create_1dst_5src(dc, OP_sudot, Rd, Rd, Rn, Rm, index, OPND_CREATE_BYTE()) |
Creates a SUDOT instruction.
This macro is used to encode the forms:
* SUDOT <Vd>.<Ts>, <Vn>.<Tb>, <Vm>.4B[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The third source and destination vector register. Can be Q (quadword, 128 bits) or D (doubleword, 64 bits). Rn The first source vector register. Can be Q (quadword, 128 bits) or D (doubleword, 64 bits). Rm The second source vector register, Q (quadword, 128 bits). index The immediate index for Rm, in the range 0-3.
◆ INSTR_CREATE_sunpkhi_sve
| #define INSTR_CREATE_sunpkhi_sve | ( | dc, | |
| Zd, | |||
| Zn | |||
| ) | instr_create_1dst_1src(dc, OP_sunpkhi, Zd, Zn) |
Creates a SUNPKHI instruction.
This macro is used to encode the forms:
* SUNPKHI <Zd>.<Ts>, <Zn>.<Tb> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The source vector register, Z (Scalable). The destination vector element size, <Ts> (H, S, D) is twice the size of the source vector element size, <Tb> (B, H, S).
◆ INSTR_CREATE_sunpklo_sve
| #define INSTR_CREATE_sunpklo_sve | ( | dc, | |
| Zd, | |||
| Zn | |||
| ) | instr_create_1dst_1src(dc, OP_sunpklo, Zd, Zn) |
Creates a SUNPKLO instruction.
This macro is used to encode the forms:
* SUNPKLO <Zd>.<Ts>, <Zn>.<Tb> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The source vector register, Z (Scalable). The destination vector element size, <Ts> (H, S, D) is twice the size of the source vector element size, <Tb> (B, H, S).
◆ INSTR_CREATE_suqadd_sve_pred
| #define INSTR_CREATE_suqadd_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_suqadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates a SUQADD instruction.
This macro is used to encode the forms:
SUQADD <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_sve_add_vector
| #define INSTR_CREATE_sve_add_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn | |||
| ) | instr_create_1dst_2src(dc, OP_add, Rd, Rm, Rn) |
Creates an ADD vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output SVE register (created with opnd_create_reg_element_vector). Rm The first input SVE register (created with opnd_create_reg_element_vector). Rn The second input SVE register (created with opnd_create_reg_element_vector).
◆ INSTR_CREATE_sxtb_sve_pred
| #define INSTR_CREATE_sxtb_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_sxtb, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a SXTB instruction.
This macro is used to encode the forms:
* SXTB <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable)
◆ INSTR_CREATE_sxth_sve_pred
| #define INSTR_CREATE_sxth_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_sxth, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a SXTH instruction.
This macro is used to encode the forms:
* SXTH <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable)
◆ INSTR_CREATE_sxtw_sve_pred
| #define INSTR_CREATE_sxtw_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_sxtw, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates a SXTW instruction.
This macro is used to encode the forms:
* SXTW <Zd>.D, <Pg>/M, <Zn>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable)
◆ INSTR_CREATE_tbl_sve
| #define INSTR_CREATE_tbl_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_tbl, Zd, Zn, Zm) |
Creates a TBL instruction.
This macro is used to encode the form:
* TBL <Zd>.<Ts>, { <Zn>.<Ts> }, <Zm>.<Ts>
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_tbl_sve_mulvec
| #define INSTR_CREATE_tbl_sve_mulvec | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_tbl, Zd, Zn, opnd_create_increment_reg(Zn, 1), Zm) |
Creates a TBL instruction.
This macro is used to encode the form:
TBL <Zd>.<Ts>, { <Zn1>.<Ts>, <Zn2>.<Ts> }, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h, Z.s or Z.d. Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
The Zn2 parameter is derived from Zn.
◆ INSTR_CREATE_tbx_sve
| #define INSTR_CREATE_tbx_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_tbx, Zd, Zd, Zn, Zm) |
Creates a TBX instruction.
This macro is used to encode the forms:
* TBX <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_trn1_sve_pred
| #define INSTR_CREATE_trn1_sve_pred | ( | dc, | |
| Pd, | |||
| Pn, | |||
| Pm | |||
| ) | instr_create_1dst_2src(dc, OP_trn1, Pd, Pn, Pm) |
Creates a TRN1 instruction.
This macro is used to encode the forms:
* TRN1 <Pd>.<Ts>, <Pn>.<Ts>, <Pm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_trn1_sve_vector
| #define INSTR_CREATE_trn1_sve_vector | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_trn1, Zd, Zn, Zm) |
Creates a TRN1 instruction.
This macro is used to encode the forms:
* TRN1 <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> * TRN1 <Zd>.Q, <Zn>.Q, <Zm>.Q *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_trn2_sve_pred
| #define INSTR_CREATE_trn2_sve_pred | ( | dc, | |
| Pd, | |||
| Pn, | |||
| Pm | |||
| ) | instr_create_1dst_2src(dc, OP_trn2, Pd, Pn, Pm) |
Creates a TRN2 instruction.
This macro is used to encode the forms:
* TRN2 <Pd>.<Ts>, <Pn>.<Ts>, <Pm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_trn2_sve_vector
| #define INSTR_CREATE_trn2_sve_vector | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_trn2, Zd, Zn, Zm) |
Creates a TRN2 instruction.
This macro is used to encode the forms:
* TRN2 <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> * TRN2 <Zd>.Q, <Zn>.Q, <Zm>.Q *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_uaba_sve
| #define INSTR_CREATE_uaba_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_uaba, Zda, Zda, Zn, Zm) |
Creates an UABA instruction.
This macro is used to encode the forms:
* UABA <Zda>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_uaba_vector
| #define INSTR_CREATE_uaba_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_uaba, Rd, Rm, Rn, width) |
Creates a UABA vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_uabal2_vector
| #define INSTR_CREATE_uabal2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_uabal2, Rd, Rm, Rn, width) |
Creates a UABAL2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_uabal_vector
| #define INSTR_CREATE_uabal_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_uabal, Rd, Rm, Rn, width) |
Creates a UABAL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_uabalb_sve
| #define INSTR_CREATE_uabalb_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_uabalb, Zda, Zda, Zn, Zm) |
Creates an UABALB instruction.
This macro is used to encode the forms:
UABALB <Zda>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h or Z.s. Zm The third source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_uabalt_sve
| #define INSTR_CREATE_uabalt_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_uabalt, Zda, Zda, Zn, Zm) |
Creates an UABALT instruction.
This macro is used to encode the forms:
UABALT <Zda>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h or Z.s. Zm The third source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_uabd_sve_pred
| #define INSTR_CREATE_uabd_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_uabd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an UABD instruction.
This macro is used to encode the forms:
* UABD <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_uabd_vector
| #define INSTR_CREATE_uabd_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_uabd, Rd, Rm, Rn, width) |
Creates a UABD vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_uabdl2_vector
| #define INSTR_CREATE_uabdl2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_uabdl2, Rd, Rm, Rn, width) |
Creates a UABDL2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_uabdl_vector
| #define INSTR_CREATE_uabdl_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_uabdl, Rd, Rm, Rn, width) |
Creates a UABDL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_uabdlb_sve
| #define INSTR_CREATE_uabdlb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_uabdlb, Zd, Zn, Zm) |
Creates an UABDLB instruction.
This macro is used to encode the forms:
UABDLB <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h or Z.s. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_uabdlt_sve
| #define INSTR_CREATE_uabdlt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_uabdlt, Zd, Zn, Zm) |
Creates an UABDLT instruction.
This macro is used to encode the forms:
UABDLT <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h or Z.s. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_uadalp_sve_pred
| #define INSTR_CREATE_uadalp_sve_pred | ( | dc, | |
| Zda, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_uadalp, Zda, Zda, Pg, Zn), DR_PRED_MASKED) |
Creates an UADALP instruction.
This macro is used to encode the forms:
UADALP <Zda>.<Ts>, <Pg>/M, <Zn>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zn The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_uaddl2_vector
| #define INSTR_CREATE_uaddl2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_uaddl2, Rd, Rm, Rn, width) |
Creates a UADDL2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_uaddl_vector
| #define INSTR_CREATE_uaddl_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_uaddl, Rd, Rm, Rn, width) |
Creates a UADDL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_uaddlb_sve
| #define INSTR_CREATE_uaddlb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_uaddlb, Zd, Zn, Zm) |
Creates an UADDLB instruction.
This macro is used to encode the forms:
UADDLB <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h or Z.s. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_uaddlt_sve
| #define INSTR_CREATE_uaddlt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_uaddlt, Zd, Zn, Zm) |
Creates an UADDLT instruction.
This macro is used to encode the forms:
UADDLT <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h or Z.s. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_uaddv_sve_pred
| #define INSTR_CREATE_uaddv_sve_pred | ( | dc, | |
| Vd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_uaddv, Vd, Pg, Zn), DR_PRED_MASKED) |
Creates an UADDV instruction.
This macro is used to encode the forms:
* UADDV <Dd>, <Pg>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vd The destination register, D (doubleword, 64 bits). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_uaddw2_vector
| #define INSTR_CREATE_uaddw2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_uaddw2, Rd, Rm, Rn, width) |
Creates a UADDW2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_uaddw_vector
| #define INSTR_CREATE_uaddw_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_uaddw, Rd, Rm, Rn, width) |
Creates a UADDW vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_uaddwb_sve
| #define INSTR_CREATE_uaddwb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_uaddwb, Zd, Zn, Zm) |
Creates an UADDWB instruction.
This macro is used to encode the forms:
UADDWB <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.h, Z.s or Z.d. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_uaddwt_sve
| #define INSTR_CREATE_uaddwt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_uaddwt, Zd, Zn, Zm) |
Creates an UADDWT instruction.
This macro is used to encode the forms:
UADDWT <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.h, Z.s or Z.d. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_ucvtf_scalar
| #define INSTR_CREATE_ucvtf_scalar | ( | dc, | |
| Rd, | |||
| Rm | |||
| ) | instr_create_1dst_1src(dc, OP_ucvtf, Rd, Rm) |
Creates a UCVTF floating point instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd Floating-point output register. Rm Integer input register.
◆ INSTR_CREATE_ucvtf_scalar_fixed
| #define INSTR_CREATE_ucvtf_scalar_fixed | ( | dc, | |
| Rd, | |||
| Rm, | |||
| fbits | |||
| ) | instr_create_1dst_2src(dc, OP_ucvtf, Rd, Rm, fbits) |
Creates a UCVTF scalar floating-point to fixed-point convert instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd Floating-point output register. Rm Integer input register. fbits The number of bits after the binary point in the fixed-point input.
◆ INSTR_CREATE_ucvtf_sve_pred
| #define INSTR_CREATE_ucvtf_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ucvtf, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates an UCVTF instruction.
This macro is used to encode the forms:
* UCVTF <Zd>.H, <Pg>/M, <Zn>.H * UCVTF <Zd>.D, <Pg>/M, <Zn>.S * UCVTF <Zd>.H, <Pg>/M, <Zn>.S * UCVTF <Zd>.S, <Pg>/M, <Zn>.S * UCVTF <Zd>.D, <Pg>/M, <Zn>.D * UCVTF <Zd>.H, <Pg>/M, <Zn>.D * UCVTF <Zd>.S, <Pg>/M, <Zn>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_ucvtf_vector
| #define INSTR_CREATE_ucvtf_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| width | |||
| ) | instr_create_1dst_2src(dc, OP_ucvtf, Rd, Rm, width) |
Creates a UCVTF vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. width Immediate int of the vector element width. Must be OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE() or OPND_CREATE_HALF().
◆ INSTR_CREATE_ucvtf_vector_fixed
| #define INSTR_CREATE_ucvtf_vector_fixed | ( | dc, | |
| Rd, | |||
| Rm, | |||
| width, | |||
| fbits | |||
| ) | instr_create_1dst_3src(dc, OP_ucvtf, Rd, Rm, width, fbits) |
Creates a UCVTF vector floating-point to fixed-point convert instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The input register. width The vector element width. Must be OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE() or OPND_CREATE_HALF(). fbits The number of bits after the binary point in the fixed-point destination element.
◆ INSTR_CREATE_udiv_sve_pred
| #define INSTR_CREATE_udiv_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_udiv, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an UDIV instruction.
This macro is used to encode the forms:
* UDIV <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_udivr_sve_pred
| #define INSTR_CREATE_udivr_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_udivr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an UDIVR instruction.
This macro is used to encode the forms:
* UDIVR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_udot_sve
| #define INSTR_CREATE_udot_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_udot, Zda, Zda, Zn, Zm) |
Creates an UDOT instruction.
This macro is used to encode the forms:
* UDOT <Zda>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_udot_sve_idx
| #define INSTR_CREATE_udot_sve_idx | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| index | |||
| ) | instr_create_1dst_4src(dc, OP_udot, Zda, Zda, Zn, Zm, index) |
Creates an UDOT instruction.
This macro is used to encode the forms:
* UDOT <Zda>.D, <Zn>.H, <Zm>.H[<index>] * UDOT <Zda>.S, <Zn>.B, <Zm>.B[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable). index The immediate index for Zm. In the range 0-1 for the 64-bit (D) variant or 0-3 for the 32-bit (S) variant.
◆ INSTR_CREATE_udot_vector
| #define INSTR_CREATE_udot_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_4src(dc, OP_udot, Rd, Rd, Rn, Rm, OPND_CREATE_BYTE()) |
Creates a UDOT instruction.
This macro is used to encode the forms:
* UDOT <Sd>.<Ts>, <Bn>.<Tb>, <Bm>.<Tb> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm The third source vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits)
◆ INSTR_CREATE_udot_vector_indexed
| #define INSTR_CREATE_udot_vector_indexed | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| index | |||
| ) | instr_create_1dst_5src(dc, OP_udot, Rd, Rd, Rn, Rm, index, OPND_CREATE_BYTE()) |
Creates a UDOT instruction.
This macro is used to encode the forms:
* UDOT <Sd>.<Ts>, <Bn>.<Tb>, <Bm>.4B[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first source and destination vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits) Rn The second source vector register, D (doubleword, 64 bits) or Q (quadword, 128 bits) Rm The third source vector register, Q (quadword, 128 bits) index The immediate index for Rm
◆ INSTR_CREATE_uhadd_sve_pred
| #define INSTR_CREATE_uhadd_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_uhadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an UHADD instruction.
This macro is used to encode the forms:
UHADD <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_uhadd_vector
| #define INSTR_CREATE_uhadd_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_uhadd, Rd, Rm, Rn, width) |
Creates a UHADD vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_uhsub_sve_pred
| #define INSTR_CREATE_uhsub_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_uhsub, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an UHSUB instruction.
This macro is used to encode the forms:
UHSUB <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_uhsub_vector
| #define INSTR_CREATE_uhsub_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_uhsub, Rd, Rm, Rn, width) |
Creates a UHSUB vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_uhsubr_sve_pred
| #define INSTR_CREATE_uhsubr_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_uhsubr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an UHSUBR instruction.
This macro is used to encode the forms:
UHSUBR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_umax_sve
| #define INSTR_CREATE_umax_sve | ( | dc, | |
| Zdn, | |||
| imm | |||
| ) | instr_create_1dst_2src(dc, OP_umax, Zdn, Zdn, imm) |
Creates an UMAX instruction.
This macro is used to encode the forms:
* UMAX <Zdn>.<Ts>, <Zdn>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable) imm The immediate imm
◆ INSTR_CREATE_umax_sve_pred
| #define INSTR_CREATE_umax_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_umax, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an UMAX instruction.
This macro is used to encode the forms:
* UMAX <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_umax_vector
| #define INSTR_CREATE_umax_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_umax, Rd, Rm, Rn, width) |
Creates a UMAX vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_umaxp_sve_pred
| #define INSTR_CREATE_umaxp_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_umaxp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an UMAXP instruction.
This macro is used to encode the forms:
UMAXP <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_umaxp_vector
| #define INSTR_CREATE_umaxp_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_umaxp, Rd, Rm, Rn, width) |
Creates a UMAXP vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_umaxv_sve_pred
| #define INSTR_CREATE_umaxv_sve_pred | ( | dc, | |
| Vd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_umaxv, Vd, Pg, Zn), DR_PRED_MASKED) |
Creates an UMAXV instruction.
This macro is used to encode the forms:
* UMAXV <V><d>, <Pg>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vd The destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits), B (byte, 8 bits) or D (doubleword, 64 bits). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_umin_sve
| #define INSTR_CREATE_umin_sve | ( | dc, | |
| Zdn, | |||
| imm | |||
| ) | instr_create_1dst_2src(dc, OP_umin, Zdn, Zdn, imm) |
Creates an UMIN instruction.
This macro is used to encode the forms:
* UMIN <Zdn>.<Ts>, <Zdn>.<Ts>, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable) imm The immediate imm
◆ INSTR_CREATE_umin_sve_pred
| #define INSTR_CREATE_umin_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_umin, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an UMIN instruction.
This macro is used to encode the forms:
* UMIN <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_umin_vector
| #define INSTR_CREATE_umin_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_umin, Rd, Rm, Rn, width) |
Creates a UMIN vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_uminp_sve_pred
| #define INSTR_CREATE_uminp_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_uminp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an UMINP instruction.
This macro is used to encode the forms:
UMINP <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_uminp_vector
| #define INSTR_CREATE_uminp_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_uminp, Rd, Rm, Rn, width) |
Creates a UMINP vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_uminv_sve_pred
| #define INSTR_CREATE_uminv_sve_pred | ( | dc, | |
| Vd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_uminv, Vd, Pg, Zn), DR_PRED_MASKED) |
Creates an UMINV instruction.
This macro is used to encode the forms:
* UMINV <V><d>, <Pg>, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Vd The destination register. Can be H (halfword, 16 bits), S (singleword, 32 bits), B (byte, 8 bits) or D (doubleword, 64 bits). Pg The governing predicate register, P (Predicate). Zn The source vector register, Z (Scalable).
◆ INSTR_CREATE_umlal2_vector
| #define INSTR_CREATE_umlal2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_4src(dc, OP_umlal2, Rd, Rd, Rm, Rn, width) |
Creates a UMLAL2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_umlal_vector
| #define INSTR_CREATE_umlal_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_4src(dc, OP_umlal, Rd, Rd, Rm, Rn, width) |
Creates a UMLAL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_umlalb_sve
| #define INSTR_CREATE_umlalb_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_umlalb, Zda, Zda, Zn, Zm) |
Creates an UMLALB instruction.
This macro is used to encode the forms:
UMLALB <Zda>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h or Z.s. Zm The third source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_umlalb_sve_idx_vector
| #define INSTR_CREATE_umlalb_sve_idx_vector | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| i2 | |||
| ) | instr_create_1dst_4src(dc, OP_umlalb, Zda, Zda, Zn, Zm, i2) |
Creates an UMLALB instruction.
This macro is used to encode the forms:
UMLALB <Zda>.D, <Zn>.S, <Zm>.S[<index>] UMLALB <Zda>.S, <Zn>.H, <Zm>.H[<index>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.d or Z.s. Zn The second source vector register. Can be Z.s or Z.h. Zm The third source vector register. Can be Z.s or Z.h. i2 The immediate index for Zm.
◆ INSTR_CREATE_umlalt_sve
| #define INSTR_CREATE_umlalt_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_umlalt, Zda, Zda, Zn, Zm) |
Creates an UMLALT instruction.
This macro is used to encode the forms:
UMLALT <Zda>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h or Z.s. Zm The third source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_umlalt_sve_idx_vector
| #define INSTR_CREATE_umlalt_sve_idx_vector | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| i2 | |||
| ) | instr_create_1dst_4src(dc, OP_umlalt, Zda, Zda, Zn, Zm, i2) |
Creates an UMLALT instruction.
This macro is used to encode the forms:
UMLALT <Zda>.D, <Zn>.S, <Zm>.S[<index>] UMLALT <Zda>.S, <Zn>.H, <Zm>.H[<index>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.d or Z.s. Zn The second source vector register. Can be Z.s or Z.h. Zm The third source vector register. Can be Z.s or Z.h. i2 The immediate index for Zm.
◆ INSTR_CREATE_umlsl2_vector
| #define INSTR_CREATE_umlsl2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_4src(dc, OP_umlsl2, Rd, Rd, Rm, Rn, width) |
Creates a UMLSL2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_umlsl_vector
| #define INSTR_CREATE_umlsl_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_4src(dc, OP_umlsl, Rd, Rd, Rm, Rn, width) |
Creates a UMLSL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_umlslb_sve
| #define INSTR_CREATE_umlslb_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_umlslb, Zda, Zda, Zn, Zm) |
Creates an UMLSLB instruction.
This macro is used to encode the forms:
UMLSLB <Zda>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h or Z.s. Zm The third source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_umlslb_sve_idx_vector
| #define INSTR_CREATE_umlslb_sve_idx_vector | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| i2 | |||
| ) | instr_create_1dst_4src(dc, OP_umlslb, Zda, Zda, Zn, Zm, i2) |
Creates an UMLSLB instruction.
This macro is used to encode the forms:
UMLSLB <Zda>.D, <Zn>.S, <Zm>.S[<index>] UMLSLB <Zda>.S, <Zn>.H, <Zm>.H[<index>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.d or Z.s. Zn The second source vector register. Can be Z.s or Z.h. Zm The third source vector register. Can be Z.s or Z.h. i2 The immediate index for Zm.
◆ INSTR_CREATE_umlslt_sve
| #define INSTR_CREATE_umlslt_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_umlslt, Zda, Zda, Zn, Zm) |
Creates an UMLSLT instruction.
This macro is used to encode the forms:
UMLSLT <Zda>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h or Z.s. Zm The third source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_umlslt_sve_idx_vector
| #define INSTR_CREATE_umlslt_sve_idx_vector | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| i2 | |||
| ) | instr_create_1dst_4src(dc, OP_umlslt, Zda, Zda, Zn, Zm, i2) |
Creates an UMLSLT instruction.
This macro is used to encode the forms:
UMLSLT <Zda>.D, <Zn>.S, <Zm>.S[<index>] UMLSLT <Zda>.S, <Zn>.H, <Zm>.H[<index>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.d or Z.s. Zn The second source vector register. Can be Z.s or Z.h. Zm The third source vector register. Can be Z.s or Z.h. i2 The immediate index for Zm.
◆ INSTR_CREATE_ummla_sve
| #define INSTR_CREATE_ummla_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_ummla, Zda, Zda, Zn, Zm) |
Creates an UMMLA instruction.
This macro is used to encode the forms:
* UMMLA <Zda>.S, <Zn>.B, <Zm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_ummla_vector
| #define INSTR_CREATE_ummla_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_4src(dc, OP_ummla, Rd, Rd, Rn, Rm, OPND_CREATE_BYTE()) |
Creates an UMMLA instruction.
This macro is used to encode the forms:
* UMMLA <Vd>.4S, <Vn>.16B, <Vm>.16B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The third source and destination vector register, Q (quadword, 128 bits). Rn The first source vector register, Q (quadword, 128 bits). Rm The second source vector register, Q (quadword, 128 bits).
◆ INSTR_CREATE_umulh_sve_pred
| #define INSTR_CREATE_umulh_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_umulh, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an UMULH instruction.
This macro is used to encode the forms:
* UMULH <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_umull2_vector
| #define INSTR_CREATE_umull2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_umull2, Rd, Rm, Rn, width) |
Creates a UMULL2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_umull_vector
| #define INSTR_CREATE_umull_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_umull, Rd, Rm, Rn, width) |
Creates a UMULL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_umullb_sve
| #define INSTR_CREATE_umullb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_umullb, Zd, Zn, Zm) |
Creates an UMULLB instruction.
This macro is used to encode the forms:
UMULLB <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h or Z.s. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_umullb_sve_idx_vector
| #define INSTR_CREATE_umullb_sve_idx_vector | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm, | |||
| i2 | |||
| ) | instr_create_1dst_3src(dc, OP_umullb, Zd, Zn, Zm, i2) |
Creates an UMULLB instruction.
This macro is used to encode the forms:
UMULLB <Zd>.D, <Zn>.S, <Zm>.S[<index>] UMULLB <Zd>.S, <Zn>.H, <Zm>.H[<index>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.d or Z.s. Zn The first source vector register. Can be Z.s or Z.h. Zm The second source vector register. Can be Z.s or Z.h. i2 The immediate index for Zm.
◆ INSTR_CREATE_umullt_sve
| #define INSTR_CREATE_umullt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_umullt, Zd, Zn, Zm) |
Creates an UMULLT instruction.
This macro is used to encode the forms:
UMULLT <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h or Z.s. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_umullt_sve_idx_vector
| #define INSTR_CREATE_umullt_sve_idx_vector | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm, | |||
| i2 | |||
| ) | instr_create_1dst_3src(dc, OP_umullt, Zd, Zn, Zm, i2) |
Creates an UMULLT instruction.
This macro is used to encode the forms:
UMULLT <Zd>.D, <Zn>.S, <Zm>.S[<index>] UMULLT <Zd>.S, <Zn>.H, <Zm>.H[<index>]
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.d or Z.s. Zn The first source vector register. Can be Z.s or Z.h. Zm The second source vector register. Can be Z.s or Z.h. i2 The immediate index for Zm.
◆ INSTR_CREATE_uqadd_sve
| #define INSTR_CREATE_uqadd_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_uqadd, Zd, Zn, Zm) |
Creates a UQADD instruction.
This macro is used to encode the forms:
* UQADD <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The first destination vector register, Z (Scalable) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_uqadd_sve_shift
| #define INSTR_CREATE_uqadd_sve_shift | ( | dc, | |
| Zdn, | |||
| imm, | |||
| shift | |||
| ) | instr_create_1dst_4src(dc, OP_uqadd, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift) |
Creates a UQADD instruction.
This macro is used to encode the forms:
* UQADD <Zdn>.<Ts>, <Zdn>.<Ts>, #<imm>, <shift> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and first destination vector register, Z (Scalable) imm The immediate imm shift The immediate shiftOp for imm8
◆ INSTR_CREATE_uqadd_vector
| #define INSTR_CREATE_uqadd_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_uqadd, Rd, Rm, Rn, width) |
Creates a UQADD vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_uqdecb
| #define INSTR_CREATE_uqdecb | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_uqdecb, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
Creates an UQDECB instruction.
This macro is used to encode the forms:
* UQDECB <Wdn>{, <pattern>{, MUL #<imm>}}
* UQDECB <Xdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register. Can be W (Word, 32 bits) or X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_uqdecd
| #define INSTR_CREATE_uqdecd | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_uqdecd, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
Creates an UQDECD instruction.
This macro is used to encode the forms:
* UQDECD <Wdn>{, <pattern>{, MUL #<imm>}}
* UQDECD <Xdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register. Can be W (Word, 32 bits) or X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_uqdecd_sve
| #define INSTR_CREATE_uqdecd_sve | ( | dc, | |
| Zdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_uqdecd, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
Creates an UQDECD instruction.
This macro is used to encode the forms:
* UQDECD <Zdn>.D{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z (Scalable). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_uqdech
| #define INSTR_CREATE_uqdech | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_uqdech, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
Creates an UQDECH instruction.
This macro is used to encode the forms:
* UQDECH <Wdn>{, <pattern>{, MUL #<imm>}}
* UQDECH <Xdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register. Can be W (Word, 32 bits) or X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_uqdech_sve
| #define INSTR_CREATE_uqdech_sve | ( | dc, | |
| Zdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_uqdech, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
Creates an UQDECH instruction.
This macro is used to encode the forms:
* UQDECH <Zdn>.H{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z (Scalable). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_uqdecp_sve
| #define INSTR_CREATE_uqdecp_sve | ( | dc, | |
| Rdn, | |||
| Pm | |||
| ) | instr_create_1dst_2src(dc, OP_uqdecp, Rdn, Rdn, Pm) |
Creates an UQDECP instruction.
This macro is used to encode the forms:
* UQDECP <Wdn>, <Pm>.<Ts> * UQDECP <Xdn>, <Pm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register. Can be W (Word, 32 bits) or X (Extended, 64 bits). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_uqdecp_sve_vector
| #define INSTR_CREATE_uqdecp_sve_vector | ( | dc, | |
| Zdn, | |||
| Pm | |||
| ) | instr_create_1dst_2src(dc, OP_uqdecp, Zdn, Zdn, Pm) |
Creates an UQDECP instruction.
This macro is used to encode the forms:
* UQDECP <Zdn>.<Ts>, <Pm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z (Scalable). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_uqdecw
| #define INSTR_CREATE_uqdecw | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_uqdecw, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
Creates an UQDECW instruction.
This macro is used to encode the forms:
* UQDECW <Wdn>{, <pattern>{, MUL #<imm>}}
* UQDECW <Xdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register. Can be W (Word, 32 bits) or X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_uqdecw_sve
| #define INSTR_CREATE_uqdecw_sve | ( | dc, | |
| Zdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_uqdecw, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
Creates an UQDECW instruction.
This macro is used to encode the forms:
* UQDECW <Zdn>.S{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z (Scalable). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_uqincb
| #define INSTR_CREATE_uqincb | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_uqincb, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
Creates an UQINCB instruction.
This macro is used to encode the forms:
* UQINCB <Wdn>{, <pattern>{, MUL #<imm>}}
* UQINCB <Xdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register. Can be W (Word, 32 bits) or X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_uqincd
| #define INSTR_CREATE_uqincd | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_uqincd, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
Creates an UQINCD instruction.
This macro is used to encode the forms:
* UQINCD <Wdn>{, <pattern>{, MUL #<imm>}}
* UQINCD <Xdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register. Can be W (Word, 32 bits) or X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_uqincd_sve
| #define INSTR_CREATE_uqincd_sve | ( | dc, | |
| Zdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_uqincd, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
Creates an UQINCD instruction.
This macro is used to encode the forms:
* UQINCD <Zdn>.D{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z (Scalable). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_uqinch
| #define INSTR_CREATE_uqinch | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_uqinch, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
Creates an UQINCH instruction.
This macro is used to encode the forms:
* UQINCH <Wdn>{, <pattern>{, MUL #<imm>}}
* UQINCH <Xdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register. Can be W (Word, 32 bits) or X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_uqinch_sve
| #define INSTR_CREATE_uqinch_sve | ( | dc, | |
| Zdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_uqinch, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
Creates an UQINCH instruction.
This macro is used to encode the forms:
* UQINCH <Zdn>.H{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z (Scalable). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_uqincp_sve
| #define INSTR_CREATE_uqincp_sve | ( | dc, | |
| Rdn, | |||
| Pm | |||
| ) | instr_create_1dst_2src(dc, OP_uqincp, Rdn, Rdn, Pm) |
Creates an UQINCP instruction.
This macro is used to encode the forms:
* UQINCP <Wdn>, <Pm>.<Ts> * UQINCP <Xdn>, <Pm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register. Can be W (Word, 32 bits) or X (Extended, 64 bits). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_uqincp_sve_vector
| #define INSTR_CREATE_uqincp_sve_vector | ( | dc, | |
| Zdn, | |||
| Pm | |||
| ) | instr_create_1dst_2src(dc, OP_uqincp, Zdn, Zdn, Pm) |
Creates an UQINCP instruction.
This macro is used to encode the forms:
* UQINCP <Zdn>.<Ts>, <Pm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z (Scalable). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_uqincw
| #define INSTR_CREATE_uqincw | ( | dc, | |
| Rdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_uqincw, Rdn, Rdn, pattern, OPND_CREATE_MUL(), imm) |
Creates an UQINCW instruction.
This macro is used to encode the forms:
* UQINCW <Wdn>{, <pattern>{, MUL #<imm>}}
* UQINCW <Xdn>{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rdn The first source and destination register. Can be W (Word, 32 bits) or X (Extended, 64 bits). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_uqincw_sve
| #define INSTR_CREATE_uqincw_sve | ( | dc, | |
| Zdn, | |||
| pattern, | |||
| imm | |||
| ) | instr_create_1dst_4src(dc, OP_uqincw, Zdn, Zdn, pattern, OPND_CREATE_MUL(), imm) |
Creates an UQINCW instruction.
This macro is used to encode the forms:
* UQINCW <Zdn>.S{, <pattern>{, MUL #<imm>}}
* - Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The source and destination vector register, Z (Scalable). pattern The predicate constraint, see dr_pred_constr_type_t. imm The imm used as the predicate constraint multiplier.
◆ INSTR_CREATE_uqrshl_sve_pred
| #define INSTR_CREATE_uqrshl_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_uqrshl, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an UQRSHL instruction.
This macro is used to encode the forms:
UQRSHL <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_uqrshl_vector
| #define INSTR_CREATE_uqrshl_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_uqrshl, Rd, Rm, Rn, width) |
Creates a UQRSHL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_uqrshlr_sve_pred
| #define INSTR_CREATE_uqrshlr_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_uqrshlr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an UQRSHLR instruction.
This macro is used to encode the forms:
UQRSHLR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_uqrshrnb_sve
| #define INSTR_CREATE_uqrshrnb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_2src(dc, OP_uqrshrnb, Zd, Zn, imm) |
Creates an UQRSHRNB instruction.
This macro is used to encode the forms:
UQRSHRNB <Zd>.<Ts>, <Zn>.<Tb>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.b, Z.h or Z.s. Zn The first source vector register. Can be Z.h, Z.s or Z.d. imm The immediate imm1.
◆ INSTR_CREATE_uqrshrnt_sve
| #define INSTR_CREATE_uqrshrnt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_3src(dc, OP_uqrshrnt, Zd, Zd, Zn, imm) |
Creates an UQRSHRNT instruction.
This macro is used to encode the forms:
UQRSHRNT <Zd>.<Ts>, <Zn>.<Tb>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The source and destination vector register. Can be Z.b, Z.h or Z.s. Zn The second source vector register. Can be Z.h, Z.s or Z.d. imm The immediate imm1.
◆ INSTR_CREATE_uqshl_sve_pred
| #define INSTR_CREATE_uqshl_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm_imm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_uqshl, Zdn, Pg, Zdn, Zm_imm), DR_PRED_MASKED) |
Creates an UQSHL instruction.
This macro is used to encode the forms:
UQSHL <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts> SQSHL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm_imm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d or can be an immediate.
◆ INSTR_CREATE_uqshl_vector
| #define INSTR_CREATE_uqshl_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_uqshl, Rd, Rm, Rn, width) |
Creates a UQSHL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_uqshlr_sve_pred
| #define INSTR_CREATE_uqshlr_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_uqshlr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an UQSHLR instruction.
This macro is used to encode the forms:
UQSHLR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_uqshrn_vector
| #define INSTR_CREATE_uqshrn_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| width, | |||
| shift | |||
| ) | instr_create_1dst_3src(dc, OP_uqshrn, Rd, Rn, width, shift) |
Creates an UQSHRN vector unsigned saturating shift right narrow (immediate) instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rn The input register. width The output vector element width. Use OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE(). shift The number of bits to shift the result by.
◆ INSTR_CREATE_uqshrnb_sve
| #define INSTR_CREATE_uqshrnb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_2src(dc, OP_uqshrnb, Zd, Zn, imm) |
Creates an UQSHRNB instruction.
This macro is used to encode the forms:
UQSHRNB <Zd>.<Ts>, <Zn>.<Tb>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.b, Z.h or Z.s. Zn The first source vector register. Can be Z.h, Z.s or Z.d. imm The immediate imm1.
◆ INSTR_CREATE_uqshrnt_sve
| #define INSTR_CREATE_uqshrnt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_3src(dc, OP_uqshrnt, Zd, Zd, Zn, imm) |
Creates an UQSHRNT instruction.
This macro is used to encode the forms:
UQSHRNT <Zd>.<Ts>, <Zn>.<Tb>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The source and destination vector register. Can be Z.b, Z.h or Z.s. Zn The second source vector register. Can be Z.h, Z.s or Z.d. imm The immediate imm1.
◆ INSTR_CREATE_uqsub_sve
| #define INSTR_CREATE_uqsub_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_uqsub, Zd, Zn, Zm) |
Creates a UQSUB instruction.
This macro is used to encode the forms:
* UQSUB <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The first destination vector register, Z (Scalable) Zn The first source vector register, Z (Scalable) Zm The second source vector register, Z (Scalable)
◆ INSTR_CREATE_uqsub_sve_shift
| #define INSTR_CREATE_uqsub_sve_shift | ( | dc, | |
| Zdn, | |||
| imm, | |||
| shift | |||
| ) | instr_create_1dst_4src(dc, OP_uqsub, Zdn, Zdn, imm, OPND_CREATE_LSL(), shift) |
Creates a UQSUB instruction.
This macro is used to encode the forms:
* UQSUB <Zdn>.<Ts>, <Zdn>.<Ts>, #<imm>, <shift> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and first destination vector register, Z (Scalable) imm The immediate imm shift The immediate shiftOp for imm8
◆ INSTR_CREATE_uqsub_vector
| #define INSTR_CREATE_uqsub_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_uqsub, Rd, Rm, Rn, width) |
Creates a UQSUB vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_uqsubr_sve_pred
| #define INSTR_CREATE_uqsubr_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_uqsubr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an UQSUBR instruction.
This macro is used to encode the forms:
UQSUBR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_uqxtnb_sve
| #define INSTR_CREATE_uqxtnb_sve | ( | dc, | |
| Zd, | |||
| Zn | |||
| ) | instr_create_1dst_1src(dc, OP_uqxtnb, Zd, Zn) |
Creates an UQXTNB instruction.
This macro is used to encode the forms:
UQXTNB <Zd>.<Ts>, <Zn>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.b, Z.h or Z.s. Zn The source vector register. Can be Z.h, Z.s or Z.d.
◆ INSTR_CREATE_uqxtnt_sve
| #define INSTR_CREATE_uqxtnt_sve | ( | dc, | |
| Zd, | |||
| Zn | |||
| ) | instr_create_1dst_2src(dc, OP_uqxtnt, Zd, Zd, Zn) |
Creates an UQXTNT instruction.
This macro is used to encode the forms:
UQXTNT <Zd>.<Ts>, <Zn>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The source and destination vector register. Can be Z.b, Z.h or Z.s. Zn The second source vector register. Can be Z.h, Z.s or Z.d.
◆ INSTR_CREATE_urecpe_sve_pred
| #define INSTR_CREATE_urecpe_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_urecpe, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates an URECPE instruction.
This macro is used to encode the forms:
URECPE <Zd>.S, <Pg>/M, <Zn>.S
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z.s. Pg The governing predicate register, P (Predicate). Zn The source vector register, Z.s.
◆ INSTR_CREATE_urhadd_sve_pred
| #define INSTR_CREATE_urhadd_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_urhadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an URHADD instruction.
This macro is used to encode the forms:
URHADD <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_urhadd_vector
| #define INSTR_CREATE_urhadd_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_urhadd, Rd, Rm, Rn, width) |
Creates a URHADD vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_urshl_sve_pred
| #define INSTR_CREATE_urshl_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_urshl, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an URSHL instruction.
This macro is used to encode the forms:
URSHL <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_urshl_vector
| #define INSTR_CREATE_urshl_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_urshl, Rd, Rm, Rn, width) |
Creates a URSHL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_urshlr_sve_pred
| #define INSTR_CREATE_urshlr_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_urshlr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an URSHLR instruction.
This macro is used to encode the forms:
URSHLR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_urshr_sve_pred
| #define INSTR_CREATE_urshr_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| imm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_urshr, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) |
Creates an URSHR instruction.
This macro is used to encode the forms:
URSHR <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). imm The immediate imm1.
◆ INSTR_CREATE_ursqrte_sve_pred
| #define INSTR_CREATE_ursqrte_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_ursqrte, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates an URSQRTE instruction.
This macro is used to encode the forms:
URSQRTE <Zd>.S, <Pg>/M, <Zn>.S
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z.s. Pg The governing predicate register, P (Predicate). Zn The source vector register, Z.s.
◆ INSTR_CREATE_ursra_sve
| #define INSTR_CREATE_ursra_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_3src(dc, OP_ursra, Zda, Zda, Zn, imm) |
Creates an URSRA instruction.
This macro is used to encode the forms:
URSRA <Zda>.<Ts>, <Zn>.<Ts>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. imm The immediate imm1.
◆ INSTR_CREATE_usdot_sve
| #define INSTR_CREATE_usdot_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_usdot, Zda, Zda, Zn, Zm) |
Creates an USDOT instruction.
This macro is used to encode the forms:
* USDOT <Zda>.S, <Zn>.B, <Zm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_usdot_sve_idx
| #define INSTR_CREATE_usdot_sve_idx | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm, | |||
| index | |||
| ) | instr_create_1dst_4src(dc, OP_usdot, Zda, Zda, Zn, Zm, index) |
Creates an USDOT instruction.
This macro is used to encode the forms:
* USDOT <Zda>.S, <Zn>.B, <Zm>.B[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable). index The immediate index
◆ INSTR_CREATE_usdot_vector
| #define INSTR_CREATE_usdot_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_4src(dc, OP_usdot, Rd, Rd, Rn, Rm, OPND_CREATE_BYTE()) |
Creates an USDOT instruction.
This macro is used to encode the forms:
* USDOT <Vd>.<Ts>, <Vn>.<Tb>, <Vm>.<Tb> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The third source and destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits). Rn The first source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits). Rm The second source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits).
◆ INSTR_CREATE_usdot_vector_idx
| #define INSTR_CREATE_usdot_vector_idx | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| index | |||
| ) | instr_create_1dst_5src(dc, OP_usdot, Rd, Rd, Rn, Rm, index, OPND_CREATE_BYTE()) |
Creates an USDOT instruction.
This macro is used to encode the forms:
* USDOT <Vd>.<Ts>, <Vn>.<Tb>, <Vm>.4B[<index>] *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The third source and destination vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits). Rn The first source vector register. Can be D (doubleword, 64 bits) or Q (quadword, 128 bits). Rm The second source vector register, Q (quadword, 128 bits). index The immediate index for Rm, in the range 0-3.
◆ INSTR_CREATE_ushl_vector
| #define INSTR_CREATE_ushl_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_ushl, Rd, Rm, Rn, width) |
Creates a USHL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
◆ INSTR_CREATE_ushllb_sve
| #define INSTR_CREATE_ushllb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_2src(dc, OP_ushllb, Zd, Zn, imm) |
Creates an USHLLB instruction.
This macro is used to encode the forms:
USHLLB <Zd>.<Ts>, <Zn>.<Tb>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h or Z.s. imm The immediate imm.
◆ INSTR_CREATE_ushllt_sve
| #define INSTR_CREATE_ushllt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_2src(dc, OP_ushllt, Zd, Zn, imm) |
Creates an USHLLT instruction.
This macro is used to encode the forms:
USHLLT <Zd>.<Ts>, <Zn>.<Tb>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h or Z.s. imm The immediate imm.
◆ INSTR_CREATE_usmmla_sve
| #define INSTR_CREATE_usmmla_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_3src(dc, OP_usmmla, Zda, Zda, Zn, Zm) |
Creates an USMMLA instruction.
This macro is used to encode the forms:
* USMMLA <Zda>.S, <Zn>.B, <Zm>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register, Z (Scalable). Zn The second source vector register, Z (Scalable). Zm The third source vector register, Z (Scalable).
◆ INSTR_CREATE_usmmla_vector
| #define INSTR_CREATE_usmmla_vector | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_4src(dc, OP_usmmla, Rd, Rd, Rn, Rm, OPND_CREATE_BYTE()) |
Creates an USMMLA instruction.
This macro is used to encode the forms:
* USMMLA <Vd>.4S, <Vn>.16B, <Vm>.16B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The third source and destination vector register, Q (quadword, 128 bits). Rn The first source vector register, Q (quadword, 128 bits). Rm The second source vector register, Q (quadword, 128 bits).
◆ INSTR_CREATE_usqadd_sve_pred
| #define INSTR_CREATE_usqadd_sve_pred | ( | dc, | |
| Zdn, | |||
| Pg, | |||
| Zm | |||
| ) | INSTR_PRED(instr_create_1dst_3src(dc, OP_usqadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) |
Creates an USQADD instruction.
This macro is used to encode the forms:
USQADD <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Pg The governing predicate register, P (Predicate). Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d.
◆ INSTR_CREATE_usra_sve
| #define INSTR_CREATE_usra_sve | ( | dc, | |
| Zda, | |||
| Zn, | |||
| imm | |||
| ) | instr_create_1dst_3src(dc, OP_usra, Zda, Zda, Zn, imm) |
Creates an USRA instruction.
This macro is used to encode the forms:
USRA <Zda>.<Ts>, <Zn>.<Ts>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zda The source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Zn The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. imm The immediate imm1.
◆ INSTR_CREATE_usubl2_vector
| #define INSTR_CREATE_usubl2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_usubl2, Rd, Rm, Rn, width) |
Creates a USUBL2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_usubl_vector
| #define INSTR_CREATE_usubl_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_usubl, Rd, Rm, Rn, width) |
Creates a USUBL vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_usublb_sve
| #define INSTR_CREATE_usublb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_usublb, Zd, Zn, Zm) |
Creates an USUBLB instruction.
This macro is used to encode the forms:
USUBLB <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h or Z.s. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_usublt_sve
| #define INSTR_CREATE_usublt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_usublt, Zd, Zn, Zm) |
Creates an USUBLT instruction.
This macro is used to encode the forms:
USUBLT <Zd>.<Ts>, <Zn>.<Tb>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.b, Z.h or Z.s. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_usubw2_vector
| #define INSTR_CREATE_usubw2_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_usubw2, Rd, Rm, Rn, width) |
Creates a USUBW2 vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_usubw_vector
| #define INSTR_CREATE_usubw_vector | ( | dc, | |
| Rd, | |||
| Rm, | |||
| Rn, | |||
| width | |||
| ) | instr_create_1dst_3src(dc, OP_usubw, Rd, Rm, Rn, width) |
Creates a USUBW vector instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The output register. Rm The first input register. Rn The second input register. width The input vector element width. Use either OPND_CREATE_BYTE(), OPND_CREATE_HALF() or OPND_CREATE_SINGLE().
◆ INSTR_CREATE_usubwb_sve
| #define INSTR_CREATE_usubwb_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_usubwb, Zd, Zn, Zm) |
Creates an USUBWB instruction.
This macro is used to encode the forms:
USUBWB <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.h, Z.s or Z.d. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_usubwt_sve
| #define INSTR_CREATE_usubwt_sve | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_usubwt, Zd, Zn, Zm) |
Creates an USUBWT instruction.
This macro is used to encode the forms:
USUBWT <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Tb>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register. Can be Z.h, Z.s or Z.d. Zn The first source vector register. Can be Z.h, Z.s or Z.d. Zm The second source vector register. Can be Z.b, Z.h or Z.s.
◆ INSTR_CREATE_uunpkhi_sve
| #define INSTR_CREATE_uunpkhi_sve | ( | dc, | |
| Zd, | |||
| Zn | |||
| ) | instr_create_1dst_1src(dc, OP_uunpkhi, Zd, Zn) |
Creates an UUNPKHI instruction.
This macro is used to encode the forms:
* UUNPKHI <Zd>.<Ts>, <Zn>.<Tb> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The source vector register, Z (Scalable). The destination vector element size, <Ts> (H, S, D) is twice the size of the source vector element size, <Tb> (B, H, S).
◆ INSTR_CREATE_uunpklo_sve
| #define INSTR_CREATE_uunpklo_sve | ( | dc, | |
| Zd, | |||
| Zn | |||
| ) | instr_create_1dst_1src(dc, OP_uunpklo, Zd, Zn) |
Creates an UUNPKLO instruction.
This macro is used to encode the forms:
* UUNPKLO <Zd>.<Ts>, <Zn>.<Tb> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The source vector register, Z (Scalable). The destination vector element size, <Ts> (H, S, D) is twice the size of the source vector element size, <Tb> (B, H, S).
◆ INSTR_CREATE_uxtb_sve_pred
| #define INSTR_CREATE_uxtb_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_uxtb, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates an UXTB instruction.
This macro is used to encode the forms:
* UXTB <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable)
◆ INSTR_CREATE_uxth_sve_pred
| #define INSTR_CREATE_uxth_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_uxth, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates an UXTH instruction.
This macro is used to encode the forms:
* UXTH <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable)
◆ INSTR_CREATE_uxtw_sve_pred
| #define INSTR_CREATE_uxtw_sve_pred | ( | dc, | |
| Zd, | |||
| Pg, | |||
| Zn | |||
| ) | INSTR_PRED(instr_create_1dst_2src(dc, OP_uxtw, Zd, Pg, Zn), DR_PRED_MASKED) |
Creates an UXTW instruction.
This macro is used to encode the forms:
* UXTW <Zd>.D, <Pg>/M, <Zn>.D *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable) Pg The governing predicate register, P (Predicate) Zn The source vector register, Z (Scalable)
◆ INSTR_CREATE_uzp1_sve_pred
| #define INSTR_CREATE_uzp1_sve_pred | ( | dc, | |
| Pd, | |||
| Pn, | |||
| Pm | |||
| ) | instr_create_1dst_2src(dc, OP_uzp1, Pd, Pn, Pm) |
Creates an UZP1 instruction.
This macro is used to encode the forms:
* UZP1 <Pd>.<Ts>, <Pn>.<Ts>, <Pm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_uzp1_sve_vector
| #define INSTR_CREATE_uzp1_sve_vector | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_uzp1, Zd, Zn, Zm) |
Creates an UZP1 instruction.
This macro is used to encode the forms:
UZP1 <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> UZP1 <Zd>.Q, <Zn>.Q, <Zm>.Q
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_uzp2_sve_pred
| #define INSTR_CREATE_uzp2_sve_pred | ( | dc, | |
| Pd, | |||
| Pn, | |||
| Pm | |||
| ) | instr_create_1dst_2src(dc, OP_uzp2, Pd, Pn, Pm) |
Creates an UZP2 instruction.
This macro is used to encode the forms:
* UZP2 <Pd>.<Ts>, <Pn>.<Ts>, <Pm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_uzp2_sve_vector
| #define INSTR_CREATE_uzp2_sve_vector | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_uzp2, Zd, Zn, Zm) |
Creates an UZP2 instruction.
This macro is used to encode the forms:
* UZP2 <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> * UZP2 <Zd>.Q, <Zn>.Q, <Zm>.Q *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_wfe
| #define INSTR_CREATE_wfe | ( | dc | ) | instr_create_0dst_0src(dc, OP_wfe) |
Creates a WFE instruction.
This macro is used to encode the forms:
WFE
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_wfet
| #define INSTR_CREATE_wfet | ( | dc, | |
| Rt | |||
| ) | instr_create_0dst_1src(dc, OP_wfet, Rt) |
Creates a WFET instruction.
This macro is used to encode the forms:
* WFET <Xt> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The source register, X (Extended, 64 bits).
◆ INSTR_CREATE_wfi
| #define INSTR_CREATE_wfi | ( | dc | ) | instr_create_0dst_0src(dc, OP_wfi) |
Creates a WFI instruction.
This macro is used to encode the forms:
WFI
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_wfit
| #define INSTR_CREATE_wfit | ( | dc, | |
| Rt | |||
| ) | instr_create_0dst_1src(dc, OP_wfit, Rt) |
Creates a WFIT instruction.
This macro is used to encode the forms:
* WFIT <Xt> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rt The source register, X (Extended, 64 bits).
◆ INSTR_CREATE_whilege_sve
| #define INSTR_CREATE_whilege_sve | ( | dc, | |
| Pd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_whilege, Pd, Rn, Rm) |
Creates a WHILEGE instruction.
This macro is used to encode the forms:
WHILEGE <Pd>.<Ts>, <R><n>, <R><m>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register. Can be P.b, P.h, P.s or P.d. Rn The first source register. Can be W (Word, 32 bits) or X (Extended, 64 bits). Rm The second source register. Can be W (Word, 32 bits) or X (Extended, 64 bits).
◆ INSTR_CREATE_whilegt_sve
| #define INSTR_CREATE_whilegt_sve | ( | dc, | |
| Pd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_whilegt, Pd, Rn, Rm) |
Creates a WHILEGT instruction.
This macro is used to encode the forms:
WHILEGT <Pd>.<Ts>, <R><n>, <R><m>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register. Can be P.b, P.h, P.s or P.d. Rn The first source register. Can be W (Word, 32 bits) or X (Extended, 64 bits). Rm The second source register. Can be W (Word, 32 bits) or X (Extended, 64 bits).
◆ INSTR_CREATE_whilehi_sve
| #define INSTR_CREATE_whilehi_sve | ( | dc, | |
| Pd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_whilehi, Pd, Rn, Rm) |
Creates a WHILEHI instruction.
This macro is used to encode the forms:
WHILEHI <Pd>.<Ts>, <R><n>, <R><m>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register. Can be P.b, P.h, P.s or P.d. Rn The first source register. Can be W (Word, 32 bits) or X (Extended, 64 bits). Rm The second source register. Can be W (Word, 32 bits) or X (Extended, 64 bits).
◆ INSTR_CREATE_whilehs_sve
| #define INSTR_CREATE_whilehs_sve | ( | dc, | |
| Pd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_whilehs, Pd, Rn, Rm) |
Creates a WHILEHS instruction.
This macro is used to encode the forms:
WHILEHS <Pd>.<Ts>, <R><n>, <R><m>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register. Can be P.b, P.h, P.s or P.d. Rn The first source register. Can be W (Word, 32 bits) or X (Extended, 64 bits). Rm The second source register. Can be W (Word, 32 bits) or X (Extended, 64 bits).
◆ INSTR_CREATE_whilele_sve
| #define INSTR_CREATE_whilele_sve | ( | dc, | |
| Pd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_whilele, Pd, Rn, Rm) |
Creates a WHILELE instruction.
This macro is used to encode the forms:
* WHILELE <Pd>.<Ts>, <R><n>, <R><m> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Rn The first source register. Can be W (Word, 32 bits) or X (Extended, 64 bits). Rm The second source register. Can be W (Word, 32 bits) or X (Extended, 64 bits).
◆ INSTR_CREATE_whilelo_sve
| #define INSTR_CREATE_whilelo_sve | ( | dc, | |
| Pd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_whilelo, Pd, Rn, Rm) |
Creates a WHILELO instruction.
This macro is used to encode the forms:
* WHILELO <Pd>.<Ts>, <R><n>, <R><m> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Rn The first source register. Can be W (Word, 32 bits) or X (Extended, 64 bits). Rm The second source register. Can be W (Word, 32 bits) or X (Extended, 64 bits).
◆ INSTR_CREATE_whilels_sve
| #define INSTR_CREATE_whilels_sve | ( | dc, | |
| Pd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_whilels, Pd, Rn, Rm) |
Creates a WHILELS instruction.
This macro is used to encode the forms:
* WHILELS <Pd>.<Ts>, <R><n>, <R><m> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Rn The first source register. Can be W (Word, 32 bits) or X (Extended, 64 bits). Rm The second source register. Can be W (Word, 32 bits) or X (Extended, 64 bits).
◆ INSTR_CREATE_whilelt_sve
| #define INSTR_CREATE_whilelt_sve | ( | dc, | |
| Pd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_whilelt, Pd, Rn, Rm) |
Creates a WHILELT instruction.
This macro is used to encode the forms:
* WHILELT <Pd>.<Ts>, <R><n>, <R><m> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Rn The first source register. Can be W (Word, 32 bits) or X (Extended, 64 bits). Rm The second source register. Can be W (Word, 32 bits) or X (Extended, 64 bits).
◆ INSTR_CREATE_whilerw_sve
| #define INSTR_CREATE_whilerw_sve | ( | dc, | |
| Pd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_whilerw, Pd, Rn, Rm) |
Creates a WHILERW instruction.
This macro is used to encode the forms:
WHILERW <Pd>.<Ts>, <Xn>, <Xm>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register. Can be P.b, P.h, P.s or P.d. Rn The first source register, X (Extended, 64 bits). Rm The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_whilewr_sve
| #define INSTR_CREATE_whilewr_sve | ( | dc, | |
| Pd, | |||
| Rn, | |||
| Rm | |||
| ) | instr_create_1dst_2src(dc, OP_whilewr, Pd, Rn, Rm) |
Creates a WHILEWR instruction.
This macro is used to encode the forms:
WHILEWR <Pd>.<Ts>, <Xn>, <Xm>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register. Can be P.b, P.h, P.s or P.d. Rn The first source register, X (Extended, 64 bits). Rm The second source register, X (Extended, 64 bits).
◆ INSTR_CREATE_wrffr_sve
| #define INSTR_CREATE_wrffr_sve | ( | dc, | |
| Pn | |||
| ) | instr_create_0dst_1src(dc, OP_wrffr, Pn) |
Creates a WRFFR instruction.
This macro is used to encode the forms:
* WRFFR <Pn>.B *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pn The source predicate register, P (Predicate)
◆ INSTR_CREATE_xaflag
| #define INSTR_CREATE_xaflag | ( | dc | ) | instr_create_0dst_0src(dc, OP_xaflag) |
Creates a XAFLAG instruction.
This macro is used to encode the forms:
XAFLAG
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_xar
| #define INSTR_CREATE_xar | ( | dc, | |
| Rd, | |||
| Rn, | |||
| Rm, | |||
| imm6 | |||
| ) | instr_create_1dst_4src(dc, OP_xar, Rd, Rn, Rm, imm6, OPND_CREATE_DOUBLE()) |
Creates a XAR instruction.
This macro is used to encode the forms:
* XAR <Dd>.2D, <Dn>.2D, <Dm>.2D, #<imm> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The first destination vector register, Q (quadword, 128 bits) Rn The second source vector register, Q (quadword, 128 bits) Rm The third source vector register, Q (quadword, 128 bits) imm6 The immediate imm
◆ INSTR_CREATE_xar_sve
| #define INSTR_CREATE_xar_sve | ( | dc, | |
| Zdn, | |||
| Zm, | |||
| imm | |||
| ) | instr_create_1dst_3src(dc, OP_xar, Zdn, Zdn, Zm, imm) |
Creates a XAR instruction.
This macro is used to encode the forms:
XAR <Zdn>.<Ts>, <Zdn>.<Ts>, <Zm>.<Ts>, #<const>
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zdn The first source and destination vector register. Can be Z.b, Z.h, Z.s or Z.d. Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. imm The immediate imm1.
◆ INSTR_CREATE_xpacd
| #define INSTR_CREATE_xpacd | ( | dc, | |
| Rd | |||
| ) | instr_create_1dst_1src(dc, OP_xpacd, Rd, Rd) |
Creates a XPACD instruction.
This macro is used to encode the forms:
* XPACD <Xd> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination register, X (Extended, 64 bits).
◆ INSTR_CREATE_xpaci
| #define INSTR_CREATE_xpaci | ( | dc, | |
| Rd | |||
| ) | instr_create_1dst_1src(dc, OP_xpaci, Rd, Rd) |
Creates a XPACI instruction.
This macro is used to encode the forms:
* XPACI <Xd> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Rd The source and destination register, X (Extended, 64 bits).
◆ INSTR_CREATE_xpaclri
| #define INSTR_CREATE_xpaclri | ( | dc | ) |
Value:
instr_create_1dst_1src(dc, OP_xpaclri, opnd_create_reg(DR_REG_X30), \
opnd_create_reg(DR_REG_X30))
Creates a XPACLRI instruction.
This macro is used to encode the forms:
* XPACLRI *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t.
◆ INSTR_CREATE_zip1_sve_pred
| #define INSTR_CREATE_zip1_sve_pred | ( | dc, | |
| Pd, | |||
| Pn, | |||
| Pm | |||
| ) | instr_create_1dst_2src(dc, OP_zip1, Pd, Pn, Pm) |
Creates a ZIP1 instruction.
This macro is used to encode the forms:
* ZIP1 <Pd>.<Ts>, <Pn>.<Ts>, <Pm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_zip1_sve_vector
| #define INSTR_CREATE_zip1_sve_vector | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_zip1, Zd, Zn, Zm) |
Creates a ZIP1 instruction.
This macro is used to encode the forms:
* ZIP1 <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> * ZIP1 <Zd>.Q, <Zn>.Q, <Zm>.Q *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ INSTR_CREATE_zip2_sve_pred
| #define INSTR_CREATE_zip2_sve_pred | ( | dc, | |
| Pd, | |||
| Pn, | |||
| Pm | |||
| ) | instr_create_1dst_2src(dc, OP_zip2, Pd, Pn, Pm) |
Creates a ZIP2 instruction.
This macro is used to encode the forms:
* ZIP2 <Pd>.<Ts>, <Pn>.<Ts>, <Pm>.<Ts> *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Pd The destination predicate register, P (Predicate). Pn The first source predicate register, P (Predicate). Pm The second source predicate register, P (Predicate).
◆ INSTR_CREATE_zip2_sve_vector
| #define INSTR_CREATE_zip2_sve_vector | ( | dc, | |
| Zd, | |||
| Zn, | |||
| Zm | |||
| ) | instr_create_1dst_2src(dc, OP_zip2, Zd, Zn, Zm) |
Creates a ZIP2 instruction.
This macro is used to encode the forms:
* ZIP2 <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts> * ZIP2 <Zd>.Q, <Zn>.Q, <Zm>.Q *
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. Zd The destination vector register, Z (Scalable). Zn The first source vector register, Z (Scalable). Zm The second source vector register, Z (Scalable).
◆ OPND_CREATE_ABSMEM
| #define OPND_CREATE_ABSMEM | ( | addr, | |
| size | |||
| ) | opnd_create_rel_addr(addr, size) |
Create an absolute address operand encoded as pc-relative. Encoding will fail if addr is out of the maximum signed displacement reach for the architecture.
◆ OPND_CREATE_ASR
| #define OPND_CREATE_ASR | ( | ) | opnd_add_flags(OPND_CREATE_INT(DR_SHIFT_ASR), DR_OPND_IS_SHIFT) |
Create an operand specifying ASR (Arithmetic Shift Right).
◆ OPND_CREATE_BYTE
| #define OPND_CREATE_BYTE | ( | ) | OPND_CREATE_INT8(VECTOR_ELEM_WIDTH_BYTE) |
Operand denoting 8 bit vector element width for the other operands of the containing instruction.
◆ OPND_CREATE_DOUBLE
| #define OPND_CREATE_DOUBLE | ( | ) | OPND_CREATE_INT8(VECTOR_ELEM_WIDTH_DOUBLE) |
Operand denoting 64 bit vector element width for the other operands of the containing instruction.
◆ OPND_CREATE_HALF
| #define OPND_CREATE_HALF | ( | ) | OPND_CREATE_INT8(VECTOR_ELEM_WIDTH_HALF) |
Operand denoting 16 bit vector element width for the other operands of the containing instruction.
◆ OPND_CREATE_INT
| #define OPND_CREATE_INT | ( | val | ) | OPND_CREATE_INTPTR(val) |
Create an immediate integer operand. For AArch64 the size of an immediate is ignored when encoding, so there is no need to specify the final size.
◆ OPND_CREATE_LSL
| #define OPND_CREATE_LSL | ( | ) | opnd_add_flags(OPND_CREATE_INT(DR_SHIFT_LSL), DR_OPND_IS_SHIFT) |
Create an operand specifying LSL (Logical Shift Left), the default shift type when there is no shift.
◆ OPND_CREATE_LSR
| #define OPND_CREATE_LSR | ( | ) | opnd_add_flags(OPND_CREATE_INT(DR_SHIFT_LSR), DR_OPND_IS_SHIFT) |
Create an operand specifying LSR (Logical Shift Right).
◆ OPND_CREATE_MUL
| #define OPND_CREATE_MUL | ( | ) | opnd_add_flags(OPND_CREATE_INT(DR_SHIFT_MUL), DR_OPND_IS_SHIFT) |
Create an operand specifying MUL, a multiplier operand.
◆ OPND_CREATE_ROR
| #define OPND_CREATE_ROR | ( | ) | opnd_add_flags(OPND_CREATE_INT(DR_SHIFT_ROR), DR_OPND_IS_SHIFT) |
Create an operand specifying ROR (ROtate Right).
◆ OPND_CREATE_SINGLE
| #define OPND_CREATE_SINGLE | ( | ) | OPND_CREATE_INT8(VECTOR_ELEM_WIDTH_SINGLE) |
Operand denoting 32 bit vector element width for the other operands of the containing instruction.
◆ OPND_CREATE_ZR
| #define OPND_CREATE_ZR | ( | reg | ) | opnd_create_reg(opnd_get_size(reg) == OPSZ_4 ? DR_REG_WZR : DR_REG_XZR) |
Create a zero register operand of the same size as reg.
◆ VECTOR_ELEM_WIDTH_BYTE
| #define VECTOR_ELEM_WIDTH_BYTE 0 |
Used in an additional immediate source operand to a vector operation, denotes 8 bit vector element width. See AArch64 IR Variations.
◆ VECTOR_ELEM_WIDTH_DOUBLE
| #define VECTOR_ELEM_WIDTH_DOUBLE 3 |
Used in an additional immediate source operand to a vector operation, denotes 64 bit vector element width. See AArch64 IR Variations.
◆ VECTOR_ELEM_WIDTH_HALF
| #define VECTOR_ELEM_WIDTH_HALF 1 |
Used in an additional immediate source operand to a vector operation, denotes 16 bit vector element width. See AArch64 IR Variations.
◆ VECTOR_ELEM_WIDTH_QUAD
| #define VECTOR_ELEM_WIDTH_QUAD 4 |
Used in an additional immediate source operand to a vector operation, denotes full size 128 bit vector width. See AArch64 IR Variations.
◆ VECTOR_ELEM_WIDTH_SINGLE
| #define VECTOR_ELEM_WIDTH_SINGLE 2 |
Used in an additional immediate source operand to a vector operation, denotes 32 bit vector element width. See AArch64 IR Variations.
◆ XINST_CREATE_add
| #define XINST_CREATE_add | ( | dc, | |
| d, | |||
| s | |||
| ) | INSTR_CREATE_add(dc, d, d, s) |
This platform-independent macro creates an instr_t for an addition instruction that does not affect the status flags.
◆ XINST_CREATE_add_2src
| #define XINST_CREATE_add_2src | ( | dc, | |
| d, | |||
| s1, | |||
| s2 | |||
| ) | INSTR_CREATE_add(dc, d, s1, s2) |
This platform-independent macro creates an instr_t for an addition instruction that does not affect the status flags and takes two sources plus a destination.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. d The opnd_t explicit destination operand for the instruction. s1 The opnd_t explicit first source operand for the instruction. This must be a register. s2 The opnd_t explicit source operand for the instruction. This can be either a register or an immediate integer.
◆ XINST_CREATE_add_s
| #define XINST_CREATE_add_s | ( | dc, | |
| d, | |||
| s | |||
| ) | INSTR_CREATE_adds(dc, d, d, s) |
This platform-independent macro creates an instr_t for an addition instruction that does affect the status flags.
◆ XINST_CREATE_add_sll
| #define XINST_CREATE_add_sll | ( | dc, | |
| d, | |||
| s1, | |||
| s2_toshift, | |||
| shift_amount | |||
| ) |
Value:
INSTR_CREATE_add_shift((dc), (d), (s1), (s2_toshift), OPND_CREATE_LSL(), \
OPND_CREATE_INT8(shift_amount))
This platform-independent macro creates an instr_t for an addition instruction that does not affect the status flags and takes two register sources plus a destination, with one source being shifted logically left by an immediate amount that is limited to either 0, 1, 2, or 3.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. d The opnd_t explicit destination operand for the instruction. s1 The opnd_t explicit first source operand for the instruction. This must be a register. s2_toshift The opnd_t explicit source operand for the instruction. This must be a register. shift_amount An integer value that must be either 0, 1, 2, or 3.
◆ XINST_CREATE_and_s
| #define XINST_CREATE_and_s | ( | dc, | |
| d, | |||
| s | |||
| ) | INSTR_CREATE_ands(dc, d, d, s) |
This platform-independent macro creates an instr_t for a bitwise and instruction that does affect the status flags.
◆ XINST_CREATE_call
| #define XINST_CREATE_call | ( | dc, | |
| t | |||
| ) | INSTR_CREATE_bl(dc, t) |
This platform-independent macro creates an instr_t for an unconditional branch instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. t The opnd_t target operand for the instruction, which can be either a pc (opnd_create_pc)()) or an instr_t (opnd_create_instr()). Be sure to ensure that the limited reach of this short branch will reach the target (a pc operand is not suitable for most uses unless you know precisely where this instruction will be encoded).
◆ XINST_CREATE_call_reg
| #define XINST_CREATE_call_reg | ( | dc, | |
| r | |||
| ) | INSTR_CREATE_blr(dc, r) |
◆ XINST_CREATE_cmp
| #define XINST_CREATE_cmp | ( | dc, | |
| s1, | |||
| s2 | |||
| ) | INSTR_CREATE_cmp(dc, s1, s2) |
◆ XINST_CREATE_debug_instr
| #define XINST_CREATE_debug_instr | ( | dc | ) | INSTR_CREATE_brk((dc), OPND_CREATE_INT16(0)) |
◆ XINST_CREATE_interrupt
| #define XINST_CREATE_interrupt | ( | dc, | |
| i | |||
| ) | INSTR_CREATE_svc(dc, (i)) |
◆ XINST_CREATE_jump
| #define XINST_CREATE_jump | ( | dc, | |
| t | |||
| ) | INSTR_CREATE_b((dc), (t)) |
This platform-independent macro creates an instr_t for an unconditional branch instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. t The opnd_t target operand for the instruction, which can be either a pc (opnd_create_pc)()) or an instr_t (opnd_create_instr()). Be sure to ensure that the limited reach of this short branch will reach the target (a pc operand is not suitable for most uses unless you know precisely where this instruction will be encoded).
◆ XINST_CREATE_jump_cond
| #define XINST_CREATE_jump_cond | ( | dc, | |
| pred, | |||
| t | |||
| ) | (INSTR_PRED(INSTR_CREATE_bcond((dc), (t)), (pred))) |
This platform-independent macro creates an instr_t for a conditional branch instruction that branches if the previously-set condition codes indicate the condition indicated by pred.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. pred The dr_pred_type_t condition to match. t The opnd_t target operand for the instruction, which can be either a pc (opnd_create_pc)()) or an instr_t (opnd_create_instr()). Be sure to ensure that the limited reach of this short branch will reach the target (a pc operand is not suitable for most uses unless you know precisely where this instruction will be encoded).
◆ XINST_CREATE_jump_reg
| #define XINST_CREATE_jump_reg | ( | dc, | |
| r | |||
| ) | INSTR_CREATE_br((dc), (r)) |
◆ XINST_CREATE_jump_short
| #define XINST_CREATE_jump_short | ( | dc, | |
| t | |||
| ) | INSTR_CREATE_b((dc), (t)) |
This platform-independent macro creates an instr_t for an unconditional branch instruction with the smallest available reach.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. t The opnd_t target operand for the instruction, which can be either a pc (opnd_create_pc)()) or an instr_t (opnd_create_instr()). Be sure to ensure that the limited reach of this short branch will reach the target (a pc operand is not suitable for most uses unless you know precisely where this instruction will be encoded).
◆ XINST_CREATE_load
| #define XINST_CREATE_load | ( | dc, | |
| r, | |||
| m | |||
| ) |
Value:
((opnd_is_base_disp(m) && \
(opnd_get_disp(m) < 0 || \
opnd_get_disp(m) % opnd_size_in_bytes(opnd_get_size(m)) != 0)) \
? INSTR_CREATE_ldur( \
dc, \
m) \
: INSTR_CREATE_ldr( \
dc, \
m))
This platform-independent macro creates an instr_t for a 4-byte or 8-byte memory load instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. r The destination register opnd. m The source memory opnd.
◆ XINST_CREATE_load_1byte
| #define XINST_CREATE_load_1byte | ( | dc, | |
| r, | |||
| m | |||
| ) | INSTR_CREATE_ldrb(dc, r, m) |
◆ XINST_CREATE_load_1byte_zext4
| #define XINST_CREATE_load_1byte_zext4 | ( | dc, | |
| r, | |||
| m | |||
| ) | INSTR_CREATE_ldrb(dc, r, m) |
◆ XINST_CREATE_load_2bytes
| #define XINST_CREATE_load_2bytes | ( | dc, | |
| r, | |||
| m | |||
| ) | INSTR_CREATE_ldrh(dc, r, m) |
◆ XINST_CREATE_load_int
| #define XINST_CREATE_load_int | ( | dc, | |
| r, | |||
| i | |||
| ) |
Value:
(opnd_get_immed_int(i) < 0 \
? INSTR_CREATE_movn((dc), (r), OPND_CREATE_INT32(~opnd_get_immed_int(i)), \
OPND_CREATE_INT(0)) \
: INSTR_CREATE_movz((dc), (r), (i), OPND_CREATE_INT(0)))
This platform-independent macro creates an instr_t for an immediate integer load instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. r The destination register opnd. i The source immediate integer opnd.
◆ XINST_CREATE_load_pair
| #define XINST_CREATE_load_pair | ( | dc, | |
| r1, | |||
| r2, | |||
| m | |||
| ) | INSTR_CREATE_ldp(dc, r1, r2, m) |
◆ XINST_CREATE_load_simd
| #define XINST_CREATE_load_simd | ( | dc, | |
| r, | |||
| m | |||
| ) | INSTR_CREATE_ldr((dc), (r), (m)) |
◆ XINST_CREATE_move
| #define XINST_CREATE_move | ( | dc, | |
| d, | |||
| s | |||
| ) |
Value:
opnd_get_reg(d) == DR_REG_WSP || opnd_get_reg(s) == DR_REG_WSP) \
OPND_CREATE_LSL(), OPND_CREATE_INT(0)) \
OPND_CREATE_LSL(), OPND_CREATE_INT(0)))
This platform-independent macro creates an instr_t for a register to register move instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. d The destination register opnd. s The source register opnd.
◆ XINST_CREATE_nop
| #define XINST_CREATE_nop | ( | dc | ) | INSTR_CREATE_nop(dc) |
◆ XINST_CREATE_return
| #define XINST_CREATE_return | ( | dc | ) | INSTR_CREATE_ret(dc, opnd_create_reg(DR_REG_X30)) |
◆ XINST_CREATE_slr_s
| #define XINST_CREATE_slr_s | ( | dc, | |
| d, | |||
| rm_or_imm | |||
| ) |
Value:
(opnd_is_reg(rm_or_imm) \
? instr_create_1dst_2src(dc, OP_lsrv, d, d, rm_or_imm) \
: instr_create_1dst_3src(dc, OP_ubfm, d, d, rm_or_imm, \
: OPND_CREATE_INT(63)))
This platform-independent macro creates an instr_t for a logical right shift instruction that does affect the status flags.
◆ XINST_CREATE_store
| #define XINST_CREATE_store | ( | dc, | |
| m, | |||
| r | |||
| ) |
Value:
((opnd_is_base_disp(m) && \
(opnd_get_disp(m) < 0 || \
opnd_get_disp(m) % opnd_size_in_bytes(opnd_get_size(m)) != 0)) \
? INSTR_CREATE_stur( \
dc, m, \
: INSTR_CREATE_str( \
dc, m, \
This platform-independent macro creates an instr_t for a 4-byte or 8-byte memory store instruction.
- Parameters
-
dc The void * dcontext used to allocate memory for the instr_t. m The destination memory opnd. r The source register opnd.
◆ XINST_CREATE_store_1byte
| #define XINST_CREATE_store_1byte | ( | dc, | |
| m, | |||
| r | |||
| ) | INSTR_CREATE_strb(dc, m, opnd_create_reg(reg_resize_to_opsz(opnd_get_reg(r), OPSZ_4))) |
◆ XINST_CREATE_store_2bytes
| #define XINST_CREATE_store_2bytes | ( | dc, | |
| m, | |||
| r | |||
| ) | INSTR_CREATE_strh(dc, m, opnd_create_reg(reg_resize_to_opsz(opnd_get_reg(r), OPSZ_4))) |
◆ XINST_CREATE_store_pair
| #define XINST_CREATE_store_pair | ( | dc, | |
| m, | |||
| r1, | |||
| r2 | |||
| ) | INSTR_CREATE_stp(dc, m, r1, r2) |
◆ XINST_CREATE_store_simd
| #define XINST_CREATE_store_simd | ( | dc, | |
| m, | |||
| r | |||
| ) | INSTR_CREATE_str((dc), (m), (r)) |
◆ XINST_CREATE_sub
| #define XINST_CREATE_sub | ( | dc, | |
| d, | |||
| s | |||
| ) | INSTR_CREATE_sub(dc, d, d, s) |
This platform-independent macro creates an instr_t for a subtraction instruction that does not affect the status flags.
◆ XINST_CREATE_sub_s
| #define XINST_CREATE_sub_s | ( | dc, | |
| d, | |||
| s | |||
| ) | INSTR_CREATE_subs(dc, d, d, s) |
This platform-independent macro creates an instr_t for a subtraction instruction that does affect the status flags.
DR_API instr_t * instr_create_2dst_2src(void *drcontext, int opcode, opnd_t dst1, opnd_t dst2, opnd_t src1, opnd_t src2)
DR_API instr_t * instr_create_1dst_0src(void *drcontext, int opcode, opnd_t dst)
#define INSTR_CREATE_eor_sve_pred_b(dc, Pd, Pg, Pn, Pm)
Definition: dr_ir_macros_aarch64.h:7256
DR_API INSTR_INLINE opnd_t opnd_create_predicate_reg(reg_id_t r, bool is_merge)
DR_API instr_t * instr_create_1dst_1src(void *drcontext, int opcode, opnd_t dst, opnd_t src)
DR_API opnd_size_t opnd_get_size(opnd_t opnd)
DR_API opnd_t opnd_create_increment_reg(opnd_t opnd, uint increment)
DR_API instr_t * instr_create_1dst_4src(void *drcontext, int opcode, opnd_t dst, opnd_t src1, opnd_t src2, opnd_t src3, opnd_t src4)
DR_API instr_t * instr_create_0dst_1src(void *drcontext, int opcode, opnd_t src)
DR_API bool opnd_is_base_disp(opnd_t opnd)
DR_API opnd_t opnd_create_immed_float(float f)
DR_API opnd_t opnd_create_base_disp(reg_id_t base_reg, reg_id_t index_reg, int scale, int disp, opnd_size_t data_size)
DR_API instr_t * instr_create_0dst_2src(void *drcontext, int opcode, opnd_t src1, opnd_t src2)
DR_API instr_t * instr_create_3dst_2src(void *drcontext, int opcode, opnd_t dst1, opnd_t dst2, opnd_t dst3, opnd_t src1, opnd_t src2)
DR_API reg_id_t reg_resize_to_opsz(reg_id_t reg, opnd_size_t sz)
DR_API INSTR_INLINE opnd_t opnd_create_reg(reg_id_t r)
DR_API reg_id_t opnd_get_base(opnd_t opnd)
DR_API INSTR_INLINE opnd_t opnd_create_reg_element_vector(reg_id_t r, opnd_size_t element_size)
DR_API instr_t * instr_create_5dst_5src(void *drcontext, int opcode, opnd_t dst1, opnd_t dst2, opnd_t dst3, opnd_t dst4, opnd_t dst5, opnd_t src1, opnd_t src2, opnd_t src3, opnd_t src4, opnd_t src5)
DR_API instr_t * instr_create_1dst_2src(void *drcontext, int opcode, opnd_t dst, opnd_t src1, opnd_t src2)
DR_API uint opnd_size_in_bytes(opnd_size_t size)
DR_API bool opnd_is_reg(opnd_t opnd)
DR_API instr_t * instr_create_2dst_4src(void *drcontext, int opcode, opnd_t dst1, opnd_t dst2, opnd_t src1, opnd_t src2, opnd_t src3, opnd_t src4)
DR_API ptr_int_t opnd_get_immed_int(opnd_t opnd)
DR_API instr_t * instr_create_1dst_5src(void *drcontext, int opcode, opnd_t dst, opnd_t src1, opnd_t src2, opnd_t src3, opnd_t src4, opnd_t src5)
DR_API int opnd_get_disp(opnd_t opnd)
DR_API bool reg_is_32bit(reg_id_t reg)
DR_API instr_t * instr_create_1dst_3src(void *drcontext, int opcode, opnd_t dst, opnd_t src1, opnd_t src2, opnd_t src3)
DR_API instr_t * instr_create_2dst_3src(void *drcontext, int opcode, opnd_t dst1, opnd_t dst2, opnd_t src1, opnd_t src2, opnd_t src3)
DR_API INSTR_INLINE bool opnd_is_immed(opnd_t opnd)
DR_API reg_id_t opnd_get_reg(opnd_t opnd)
DR_API instr_t * instr_create_4dst_2src(void *drcontext, int opcode, opnd_t dst1, opnd_t dst2, opnd_t dst3, opnd_t dst4, opnd_t src1, opnd_t src2)
DR_API opnd_t opnd_create_immed_int(ptr_int_t i, opnd_size_t data_size)
DynamoRIO version 11.2.0 --- Fri Dec 20 2024 17:44:39