drcpusim is a DynamoRIO client tool for testing that applications will run correctly on legacy processors.

Overview

The DynamoRIO tool drcpusim emulates execution on a specified CPU model in order to validate that a target application does not execute any instructions that are illegal or not implemented on a legacy processor.

Running the Simulator

To launch drcpusim, use the -t flag to drrun and specify a CPU model via the -cpu parameter:

bin64/drrun -t drcpusim -cpu PentiumPro -- /path/to/target/app <args> <for> <app>

The target application will be launched under a DynamoRIO client that monitors every instruction executed. If an instruction is attempted to be executed that is not supported on the requested CPU model, drcpusim will abort the execution and report the offending instruction. Any child processes will be followed into and checked as well.

Simulator Parameters

drcpusim's behavior can be controlled through options passed after the -c drcpusim but prior to the "--" delimiter on the command line:

bin64/drrun -t drcpusim <options> <to> <drcpusim> -- /path/to/target/app <args> <for> <app>

Boolean options can be disabled using a "-no_" prefix.

The parameters available are described below:

-cpu
default value: Westmere
Specifies the CPU model to simulate. It can be one of the following names, which correspond to the given CPU family, model, and major ISA features (as well as numerous other minor features):

Parameter	Notes	Family	Model	Major ISA Features
Pentium		5	2
PentiumMMX		5	4	MMX
PentiumPro		6	1
Pentium2	alias for Klamath	6	3	MMX
Klamath	Pentium2	6	3	MMX
Deschutes	Pentium2	6	5	MMX
Pentium3	alias for Coppermine	6	7	MMX, SSE
Coppermine	Pentium3	6	7	MMX, SSE
Tualatin	Pentium3	6	7	MMX, SSE
PentiumM	alias for Banias	15	2	MMX, SSE, SSE2
Banias	PentiumM	15	2	MMX, SSE, SSE2
Dothan	PentiumM	15	2	MMX, SSE, SSE2
Willamette	early Pentium4	15	2	MMX, SSE, SSE2
Northwood	early Pentium4	15	2	MMX, SSE, SSE2
Pentium4	alias for Prescott	15	4	MMX, SSE, SSE2, SSE3
Prescott	Pentium4	15	4	MMX, SSE, SSE2, SSE3
Presler	Pentium4	15	4	MMX, SSE, SSE2, SSE3
Core2	alias for Merom	6	15	MMX, SSE, SSE2, SSE3, SSSE3
Merom	Core2	6	15	MMX, SSE, SSE2, SSE3, SSSE3
Penryn	Core2	6	23	MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1
Nehalem	Core i7	6	26	MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2
Westmere	Core i7	6	44	MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2
Sandybridge	Core i7	6	42	MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX
Ivybridge	Core i7	6	58	MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, F16C

Some simplifications are made: for example, drcpusim assumes that all Prescott models support 64-bit, ignoring the early E-series models. Furthermore, drcpusim focuses on cpuid features rather than the family, and ends up treating requests for slightly different cpu models that have insignificant cpuid feature differences as identical: for example, a request for Northwood will result in a Banias model.

-continue
default value: false
By default, drcpusim aborts when it encounters an invalid instruction. This option requests that the tool continue, simply printing each invalid instruction it encounters. It may print the same instruction twice, depending on whether the underlying tool engine needs to re-translate that code again.
-fool_cpuid
default value: true
When the application executes the CPUID instruction, when this option is enabled, drcpusim will supply CPUID results that match the CPU model being simulated.
-allow_prefetchw
default value: true
The PREFETCHW instruction is only fully supported by AMD processors, yet most Intel processors, while they do not officially support it, will turn it into a NOP. As it is commonly seen on Windows, by default drcpusim does not complain about it.
-blocklist
default value: ""
The blocklist is a :-separated list of library names for which violations should not be reported.
-ignore_all_libs
default value: false
Violations in libraries are ignored: only violations in the application executable itself are reported.
-verbose
default value: 0
Verbosity level for notifications.