drcachesim consists of two components: a tracer
drmemtrace and an analyzer. The tracer collects a memory access trace from each thread within each application process. The analyzer consumes the traces (online or offline) and performs customized analysis. It is designed to be extensible, allowing users to easily implement a simulator for different devices, such as CPU caches, TLBs, page caches, etc. (see Extending the Simulator), or to build arbitrary trace analysis tools (see Creating New Analysis Tools). The default analyzer simulates the architectural behavior of caching devices for a target application (or multiple applications).